From nobody Fri Dec 19 21:50:00 2025 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7BF192FF176; Tue, 2 Dec 2025 07:40:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764661256; cv=none; b=NHS0Lc3us9d/TtqKKZlKC72TUeu62vpOPH+420pOvBBHh1oLhxf3JEzusOP8gQEmc8tO3GKWGfyfjalfL/AQduwKrdfdmXbXeN9bZxPDXQLlOeANJTJMsxidrFCWXSk804sRXp+prSvvz4gmtEdehi2PcWws5uhyixNfQ7soHdU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764661256; c=relaxed/simple; bh=s+fYGnA08QTeIzgiSM2+Kw5/k+uUaAOCCoUBmKF+exg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=fIx80207+6dnVYRdR2FLH1BNduKgrgnMffajDfQHfAvCOXs8FRjnluB/a8UiDwPbefbEtfInvSTiJgO2njJTtRFO/MCZ/zCbxwODKYFwgDsxXnFCFVR7CVQ7+3quZBTBDKnWLi4uOiV3oy8X8PjOJ772Z9UFpcZAHd6Nz5II5U8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=qBDx9+mR; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="qBDx9+mR" X-UUID: 35fdfd24cf5211f0b2bf0b349165d6e0-20251202 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=mDYeX9hnxM609HsQNMFBzZYeMea5lku9+jD+ltF6O3E=; b=qBDx9+mRgjdkS4H7macoW7Bg2iZu42uYIr+3wYBMXhemHfCNzQGwion65yDHDoroZ5rBSP++G3E1VjeAP9tVQZ0cwhMGZG5ZlRFwaWfjGR7we0kRhOxVu2jjWkHM8Gv2p+CUToklU+xHT2Ld3hGHOuUpyk258FsBzLSu8tV4K74=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.6,REQID:7997289f-4357-4add-9b9c-1c0f9338a2a6,IP:0,UR L:0,TC:0,Content:0,EDM:-25,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-25 X-CID-META: VersionHash:a9d874c,CLOUDID:41bfbaa9-6421-45b1-b8b8-e73e3dc9a90f,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|888|898,TC:-5,Content: 0|15|50,EDM:2,IP:nil,URL:0,File:130,RT:0,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI :0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 35fdfd24cf5211f0b2bf0b349165d6e0-20251202 Received: from mtkmbs09n2.mediatek.inc [(172.21.101.94)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1126577580; Tue, 02 Dec 2025 15:40:44 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.26; Tue, 2 Dec 2025 15:40:43 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1748.26 via Frontend Transport; Tue, 2 Dec 2025 15:40:42 +0800 From: Kyrie Wu To: Tiffany Lin , Andrew-CT Chen , Yunfei Dong , "Mauro Carvalho Chehab" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Kyrie Wu , Hans Verkuil , Nicolas Dufresne , Nathan Hebert , "Arnd Bergmann" , Irui Wang , George Sun , , , , , CC: Neil Armstrong , Andrzej Pietrasiewicz , Yilong Zhou Subject: [PATCH v6 01/10] dt-bindings: media: mediatek: decoder: Add MT8189 mediatek,vcodec-decoder Date: Tue, 2 Dec 2025 15:40:28 +0800 Message-ID: <20251202074038.3173-2-kyrie.wu@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20251202074038.3173-1-kyrie.wu@mediatek.com> References: <20251202074038.3173-1-kyrie.wu@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" Add compatible for video decoder on MT8189 platform. Compared with former ICs, the MT8189 decoder use iommu to instead of smmu, and use scp architecture, the frequency is only 406MHZ, and cannot reach more than 700MHZ. It used only one clock. At the same time, the decoder supports the vp9 decoding protocol for the first time in single IC. Signed-off-by: Kyrie Wu Acked-by: Rob Herring (Arm) --- .../bindings/media/mediatek,vcodec-subdev-decoder.yaml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev= -decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-sub= dev-decoder.yaml index 74e1d88d3056..ee2bbbdb2d50 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decode= r.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decode= r.yaml @@ -75,6 +75,7 @@ properties: - mediatek,mt8192-vcodec-dec - mediatek,mt8186-vcodec-dec - mediatek,mt8188-vcodec-dec + - mediatek,mt8189-vcodec-dec - mediatek,mt8195-vcodec-dec - mediatek,mt8196-vcodec-dec =20 @@ -132,11 +133,11 @@ patternProperties: Refer to bindings/iommu/mediatek,iommu.yaml. =20 clocks: - minItems: 4 + minItems: 1 maxItems: 5 =20 clock-names: - minItems: 4 + minItems: 1 maxItems: 5 =20 assigned-clocks: --=20 2.45.2 From nobody Fri Dec 19 21:50:00 2025 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 275AF30214D; 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Tue, 02 Dec 2025 15:40:50 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.26; Tue, 2 Dec 2025 15:40:44 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1748.26 via Frontend Transport; Tue, 2 Dec 2025 15:40:43 +0800 From: Kyrie Wu To: Tiffany Lin , Andrew-CT Chen , Yunfei Dong , "Mauro Carvalho Chehab" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Kyrie Wu , Hans Verkuil , Nicolas Dufresne , Nathan Hebert , "Arnd Bergmann" , Irui Wang , George Sun , , , , , CC: Neil Armstrong , Andrzej Pietrasiewicz , Yilong Zhou Subject: [PATCH v6 02/10] media: mediatek: decoder: Add a new platform data member Date: Tue, 2 Dec 2025 15:40:29 +0800 Message-ID: <20251202074038.3173-3-kyrie.wu@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20251202074038.3173-1-kyrie.wu@mediatek.com> References: <20251202074038.3173-1-kyrie.wu@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" Add a new platform data member to indicate each decoder IC to avoid the chip name definition keep growing. Signed-off-by: Kyrie Wu --- .../mediatek/vcodec/decoder/mtk_vcodec_dec.h | 5 + .../vcodec/decoder/mtk_vcodec_dec_drv.c | 35 +---- .../vcodec/decoder/mtk_vcodec_dec_drv.h | 15 +- .../vcodec/decoder/mtk_vcodec_dec_hw.c | 2 +- .../vcodec/decoder/mtk_vcodec_dec_stateful.c | 1 + .../vcodec/decoder/mtk_vcodec_dec_stateless.c | 137 +++++++++++++++--- 6 files changed, 131 insertions(+), 64 deletions(-) diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.= h b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.h index 1af075fc0194..80cb46f1cded 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.h +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.h @@ -69,6 +69,11 @@ extern const struct v4l2_m2m_ops mtk_vdec_m2m_ops; extern const struct media_device_ops mtk_vcodec_media_ops; extern const struct mtk_vcodec_dec_pdata mtk_vdec_8173_pdata; extern const struct mtk_vcodec_dec_pdata mtk_vdec_8183_pdata; +extern const struct mtk_vcodec_dec_pdata mtk_vdec_8186_pdata; +extern const struct mtk_vcodec_dec_pdata mtk_vdec_8188_pdata; +extern const struct mtk_vcodec_dec_pdata mtk_vdec_8192_pdata; +extern const struct mtk_vcodec_dec_pdata mtk_vdec_8195_pdata; +extern const struct mtk_vcodec_dec_pdata mtk_vdec_8196_pdata; extern const struct mtk_vcodec_dec_pdata mtk_lat_sig_core_pdata; extern const struct mtk_vcodec_dec_pdata mtk_vdec_single_core_pdata; =20 diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= drv.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c index 6fb05bb00641..d7a269045fd6 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c @@ -331,24 +331,7 @@ static const struct v4l2_file_operations mtk_vcodec_fo= ps =3D { =20 static void mtk_vcodec_dec_get_chip_name(struct mtk_vcodec_dec_dev *vdec_d= ev) { - struct device *dev =3D &vdec_dev->plat_dev->dev; - - if (of_device_is_compatible(dev->of_node, "mediatek,mt8173-vcodec-dec")) - vdec_dev->chip_name =3D MTK_VDEC_MT8173; - else if (of_device_is_compatible(dev->of_node, "mediatek,mt8183-vcodec-de= c")) - vdec_dev->chip_name =3D MTK_VDEC_MT8183; - else if (of_device_is_compatible(dev->of_node, "mediatek,mt8192-vcodec-de= c")) - vdec_dev->chip_name =3D MTK_VDEC_MT8192; - else if (of_device_is_compatible(dev->of_node, "mediatek,mt8195-vcodec-de= c")) - vdec_dev->chip_name =3D MTK_VDEC_MT8195; - else if (of_device_is_compatible(dev->of_node, "mediatek,mt8186-vcodec-de= c")) - vdec_dev->chip_name =3D MTK_VDEC_MT8186; - else if (of_device_is_compatible(dev->of_node, "mediatek,mt8188-vcodec-de= c")) - vdec_dev->chip_name =3D MTK_VDEC_MT8188; - else if (of_device_is_compatible(dev->of_node, "mediatek,mt8196-vcodec-de= c")) - vdec_dev->chip_name =3D MTK_VDEC_MT8196; - else - vdec_dev->chip_name =3D MTK_VDEC_INVAL; + vdec_dev->chip_name =3D vdec_dev->vdec_pdata->chip_name; } =20 static int mtk_vcodec_probe(struct platform_device *pdev) @@ -367,10 +350,6 @@ static int mtk_vcodec_probe(struct platform_device *pd= ev) dev->plat_dev =3D pdev; =20 mtk_vcodec_dec_get_chip_name(dev); - if (dev->chip_name =3D=3D MTK_VDEC_INVAL) { - dev_err(&pdev->dev, "Failed to get decoder chip name"); - return -EINVAL; - } =20 dev->vdec_pdata =3D of_device_get_match_data(&pdev->dev); if (!of_property_read_u32(pdev->dev.of_node, "mediatek,vpu", @@ -387,7 +366,7 @@ static int mtk_vcodec_probe(struct platform_device *pde= v) return -ENODEV; } dma_set_max_seg_size(&pdev->dev, UINT_MAX); - if (dev->chip_name =3D=3D MTK_VDEC_MT8196) { + if (dev->chip_name =3D=3D 8196) { ret =3D dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(36)); if (ret) { dev_err(&pdev->dev, "Failed to enable 36-bit DMA: %d\n", ret); @@ -556,23 +535,23 @@ static const struct of_device_id mtk_vcodec_match[] = =3D { }, { .compatible =3D "mediatek,mt8192-vcodec-dec", - .data =3D &mtk_lat_sig_core_pdata, + .data =3D &mtk_vdec_8192_pdata, }, { .compatible =3D "mediatek,mt8186-vcodec-dec", - .data =3D &mtk_vdec_single_core_pdata, + .data =3D &mtk_vdec_8186_pdata, }, { .compatible =3D "mediatek,mt8195-vcodec-dec", - .data =3D &mtk_lat_sig_core_pdata, + .data =3D &mtk_vdec_8195_pdata, }, { .compatible =3D "mediatek,mt8188-vcodec-dec", - .data =3D &mtk_lat_sig_core_pdata, + .data =3D &mtk_vdec_8188_pdata, }, { .compatible =3D "mediatek,mt8196-vcodec-dec", - .data =3D &mtk_lat_sig_core_pdata, + .data =3D &mtk_vdec_8196_pdata, }, {}, }; diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= drv.h b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h index 429b32952194..2dbde8d00e6f 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h @@ -19,17 +19,6 @@ #define IS_VDEC_INNER_RACING(capability) ((capability) & MTK_VCODEC_INNER_= RACING) #define IS_VDEC_SUPPORT_EXT(capability) ((capability) & MTK_VDEC_IS_SUPPOR= T_EXT) =20 -enum mtk_vcodec_dec_chip_name { - MTK_VDEC_INVAL =3D 0, - MTK_VDEC_MT8173 =3D 8173, - MTK_VDEC_MT8183 =3D 8183, - MTK_VDEC_MT8186 =3D 8186, - MTK_VDEC_MT8188 =3D 8188, - MTK_VDEC_MT8192 =3D 8192, - MTK_VDEC_MT8195 =3D 8195, - MTK_VDEC_MT8196 =3D 8196, -}; - /* * enum mtk_vdec_format_types - Structure used to get supported * format types according to decoder capability @@ -106,6 +95,7 @@ struct vdec_pic_info { * * @is_subdev_supported: whether support parent-node architecture(subdev) * @uses_stateless_api: whether the decoder uses the stateless API with re= quests + * @chip_name: platforms configuration values */ struct mtk_vcodec_dec_pdata { void (*init_vdec_params)(struct mtk_vcodec_dec_ctx *ctx); @@ -127,6 +117,7 @@ struct mtk_vcodec_dec_pdata { =20 bool is_subdev_supported; bool uses_stateless_api; + unsigned int chip_name; }; =20 /** @@ -307,7 +298,7 @@ struct mtk_vcodec_dec_dev { struct mutex dec_racing_info_mutex; struct mtk_vcodec_dbgfs dbgfs; =20 - enum mtk_vcodec_dec_chip_name chip_name; + unsigned int chip_name; }; =20 static inline struct mtk_vcodec_dec_ctx *fh_to_dec_ctx(struct v4l2_fh *fh) diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= hw.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_hw.c index e4e527fe54dc..a926dc14d39d 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_hw.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_hw.c @@ -76,7 +76,7 @@ static void mtk_vdec_hw_clean_xpc(struct mtk_vdec_hw_dev = *dev) { u32 val, mask, addr =3D VDEC_XPC_CLEAN_ADDR; =20 - if (dev->main_dev->chip_name !=3D MTK_VDEC_MT8196) + if (dev->main_dev->chip_name !=3D 8196) return; =20 val =3D dev->hw_idx =3D=3D MTK_VDEC_LAT0 ? VDEC_XPC_LAT_VAL : VDEC_XPC_CO= RE_VAL; diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= stateful.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= stateful.c index aa9bdee7a96c..8ddb61670dc6 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statefu= l.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statefu= l.c @@ -618,4 +618,5 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8173_pdata = =3D { .flush_decoder =3D mtk_vdec_flush_decoder, .is_subdev_supported =3D false, .hw_arch =3D MTK_VDEC_PURE_SINGLE_CORE, + .chip_name =3D 8173, }; diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= stateless.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec= _stateless.c index c1cef78471a9..d249a8774948 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statele= ss.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statele= ss.c @@ -550,16 +550,16 @@ static void mtk_vcodec_dec_fill_h264_level(struct v4l= 2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { switch (ctx->dev->chip_name) { - case MTK_VDEC_MT8192: - case MTK_VDEC_MT8188: + case 8192: + case 8188: cfg->max =3D V4L2_MPEG_VIDEO_H264_LEVEL_5_2; break; - case MTK_VDEC_MT8195: - case MTK_VDEC_MT8196: + case 8195: + case 8196: cfg->max =3D V4L2_MPEG_VIDEO_H264_LEVEL_6_0; break; - case MTK_VDEC_MT8183: - case MTK_VDEC_MT8186: + case 8183: + case 8186: cfg->max =3D V4L2_MPEG_VIDEO_H264_LEVEL_4_2; break; default: @@ -572,9 +572,9 @@ static void mtk_vcodec_dec_fill_h264_profile(struct v4l= 2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { switch (ctx->dev->chip_name) { - case MTK_VDEC_MT8188: - case MTK_VDEC_MT8195: - case MTK_VDEC_MT8196: + case 8188: + case 8195: + case 8196: cfg->max =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10; break; default: @@ -587,11 +587,11 @@ static void mtk_vcodec_dec_fill_h265_level(struct v4l= 2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { switch (ctx->dev->chip_name) { - case MTK_VDEC_MT8188: + case 8188: cfg->max =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1; break; - case MTK_VDEC_MT8195: - case MTK_VDEC_MT8196: + case 8195: + case 8196: cfg->max =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2; break; default: @@ -604,9 +604,9 @@ static void mtk_vcodec_dec_fill_h265_profile(struct v4l= 2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { switch (ctx->dev->chip_name) { - case MTK_VDEC_MT8188: - case MTK_VDEC_MT8195: - case MTK_VDEC_MT8196: + case 8188: + case 8195: + case 8196: cfg->max =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10; break; default: @@ -619,15 +619,15 @@ static void mtk_vcodec_dec_fill_vp9_level(struct v4l2= _ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { switch (ctx->dev->chip_name) { - case MTK_VDEC_MT8192: - case MTK_VDEC_MT8188: + case 8192: + case 8188: cfg->max =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_1; break; - case MTK_VDEC_MT8195: - case MTK_VDEC_MT8196: + case 8195: + case 8196: cfg->max =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_2; break; - case MTK_VDEC_MT8186: + case 8186: cfg->max =3D V4L2_MPEG_VIDEO_VP9_LEVEL_4_1; break; default: @@ -640,9 +640,9 @@ static void mtk_vcodec_dec_fill_vp9_profile(struct v4l2= _ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { switch (ctx->dev->chip_name) { - case MTK_VDEC_MT8188: - case MTK_VDEC_MT8195: - case MTK_VDEC_MT8196: + case 8188: + case 8195: + case 8196: cfg->max =3D V4L2_MPEG_VIDEO_VP9_PROFILE_2; break; default: @@ -886,6 +886,7 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8183_pdata = =3D { .get_cap_buffer =3D vdec_get_cap_buffer, .is_subdev_supported =3D false, .hw_arch =3D MTK_VDEC_PURE_SINGLE_CORE, + .chip_name =3D 8183, }; =20 /* This platform data is used for one lat and one core architecture. */ @@ -906,6 +907,78 @@ const struct mtk_vcodec_dec_pdata mtk_lat_sig_core_pda= ta =3D { .hw_arch =3D MTK_VDEC_LAT_SINGLE_CORE, }; =20 +const struct mtk_vcodec_dec_pdata mtk_vdec_8188_pdata =3D { + .init_vdec_params =3D mtk_init_vdec_params, + .ctrls_setup =3D mtk_vcodec_dec_ctrls_setup, + .vdec_vb2_ops =3D &mtk_vdec_request_vb2_ops, + .vdec_formats =3D mtk_video_formats, + .num_formats =3D &num_formats, + .default_out_fmt =3D &default_out_format, + .default_cap_fmt =3D &default_cap_format, + .uses_stateless_api =3D true, + .worker =3D mtk_vdec_worker, + .flush_decoder =3D mtk_vdec_flush_decoder, + .cap_to_disp =3D mtk_vdec_stateless_cap_to_disp, + .get_cap_buffer =3D vdec_get_cap_buffer, + .is_subdev_supported =3D true, + .hw_arch =3D MTK_VDEC_LAT_SINGLE_CORE, + .chip_name =3D 8188, +}; + +const struct mtk_vcodec_dec_pdata mtk_vdec_8192_pdata =3D { + .init_vdec_params =3D mtk_init_vdec_params, + .ctrls_setup =3D mtk_vcodec_dec_ctrls_setup, + .vdec_vb2_ops =3D &mtk_vdec_request_vb2_ops, + .vdec_formats =3D mtk_video_formats, + .num_formats =3D &num_formats, + .default_out_fmt =3D &default_out_format, + .default_cap_fmt =3D &default_cap_format, + .uses_stateless_api =3D true, + .worker =3D mtk_vdec_worker, + .flush_decoder =3D mtk_vdec_flush_decoder, + .cap_to_disp =3D mtk_vdec_stateless_cap_to_disp, + .get_cap_buffer =3D vdec_get_cap_buffer, + .is_subdev_supported =3D true, + .hw_arch =3D MTK_VDEC_LAT_SINGLE_CORE, + .chip_name =3D 8192, +}; + +const struct mtk_vcodec_dec_pdata mtk_vdec_8195_pdata =3D { + .init_vdec_params =3D mtk_init_vdec_params, + .ctrls_setup =3D mtk_vcodec_dec_ctrls_setup, + .vdec_vb2_ops =3D &mtk_vdec_request_vb2_ops, + .vdec_formats =3D mtk_video_formats, + .num_formats =3D &num_formats, + .default_out_fmt =3D &default_out_format, + .default_cap_fmt =3D &default_cap_format, + .uses_stateless_api =3D true, + .worker =3D mtk_vdec_worker, + .flush_decoder =3D mtk_vdec_flush_decoder, + .cap_to_disp =3D mtk_vdec_stateless_cap_to_disp, + .get_cap_buffer =3D vdec_get_cap_buffer, + .is_subdev_supported =3D true, + .hw_arch =3D MTK_VDEC_LAT_SINGLE_CORE, + .chip_name =3D 8195, +}; + +const struct mtk_vcodec_dec_pdata mtk_vdec_8196_pdata =3D { + .init_vdec_params =3D mtk_init_vdec_params, + .ctrls_setup =3D mtk_vcodec_dec_ctrls_setup, + .vdec_vb2_ops =3D &mtk_vdec_request_vb2_ops, + .vdec_formats =3D mtk_video_formats, + .num_formats =3D &num_formats, + .default_out_fmt =3D &default_out_format, + .default_cap_fmt =3D &default_cap_format, + .uses_stateless_api =3D true, + .worker =3D mtk_vdec_worker, + .flush_decoder =3D mtk_vdec_flush_decoder, + .cap_to_disp =3D mtk_vdec_stateless_cap_to_disp, + .get_cap_buffer =3D vdec_get_cap_buffer, + .is_subdev_supported =3D true, + .hw_arch =3D MTK_VDEC_LAT_SINGLE_CORE, + .chip_name =3D 8196, +}; + const struct mtk_vcodec_dec_pdata mtk_vdec_single_core_pdata =3D { .init_vdec_params =3D mtk_init_vdec_params, .ctrls_setup =3D mtk_vcodec_dec_ctrls_setup, @@ -922,3 +995,21 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_single_core= _pdata =3D { .is_subdev_supported =3D true, .hw_arch =3D MTK_VDEC_PURE_SINGLE_CORE, }; + +const struct mtk_vcodec_dec_pdata mtk_vdec_8186_pdata =3D { + .init_vdec_params =3D mtk_init_vdec_params, + .ctrls_setup =3D mtk_vcodec_dec_ctrls_setup, + .vdec_vb2_ops =3D &mtk_vdec_request_vb2_ops, + .vdec_formats =3D mtk_video_formats, + .num_formats =3D &num_formats, + .default_out_fmt =3D &default_out_format, + .default_cap_fmt =3D &default_cap_format, + .uses_stateless_api =3D true, + .worker =3D mtk_vdec_worker, + .flush_decoder =3D mtk_vdec_flush_decoder, + .cap_to_disp =3D mtk_vdec_stateless_cap_to_disp, + .get_cap_buffer =3D vdec_get_cap_buffer, + .is_subdev_supported =3D true, + .hw_arch =3D MTK_VDEC_PURE_SINGLE_CORE, + .chip_name =3D 8186, +}; --=20 2.45.2 From nobody Fri Dec 19 21:50:00 2025 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3ADF730217C; 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Tue, 02 Dec 2025 15:40:47 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS09N2.mediatek.inc (172.21.101.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.26; Tue, 2 Dec 2025 15:40:45 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1748.26 via Frontend Transport; Tue, 2 Dec 2025 15:40:44 +0800 From: Kyrie Wu To: Tiffany Lin , Andrew-CT Chen , Yunfei Dong , "Mauro Carvalho Chehab" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Kyrie Wu , Hans Verkuil , Nicolas Dufresne , Nathan Hebert , "Arnd Bergmann" , Irui Wang , George Sun , , , , , CC: Neil Armstrong , Andrzej Pietrasiewicz , Yilong Zhou Subject: [PATCH v6 03/10] media: mediatek: vcodec: add decoder compatible to support MT8189 Date: Tue, 2 Dec 2025 15:40:30 +0800 Message-ID: <20251202074038.3173-4-kyrie.wu@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20251202074038.3173-1-kyrie.wu@mediatek.com> References: <20251202074038.3173-1-kyrie.wu@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" MT8189 is pure single core architecture. Add its compatible to initialize platform data. Signed-off-by: Kyrie Wu Reviewed-by: AngeloGioacchino Del Regno --- .../mediatek/vcodec/decoder/mtk_vcodec_dec.h | 1 + .../vcodec/decoder/mtk_vcodec_dec_drv.c | 4 ++++ .../vcodec/decoder/mtk_vcodec_dec_stateless.c | 18 ++++++++++++++++++ 3 files changed, 23 insertions(+) diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.= h b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.h index 80cb46f1cded..2bde871c0224 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.h +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.h @@ -71,6 +71,7 @@ extern const struct mtk_vcodec_dec_pdata mtk_vdec_8173_pd= ata; extern const struct mtk_vcodec_dec_pdata mtk_vdec_8183_pdata; extern const struct mtk_vcodec_dec_pdata mtk_vdec_8186_pdata; extern const struct mtk_vcodec_dec_pdata mtk_vdec_8188_pdata; +extern const struct mtk_vcodec_dec_pdata mtk_vdec_8189_pdata; extern const struct mtk_vcodec_dec_pdata mtk_vdec_8192_pdata; extern const struct mtk_vcodec_dec_pdata mtk_vdec_8195_pdata; extern const struct mtk_vcodec_dec_pdata mtk_vdec_8196_pdata; diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= drv.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c index d7a269045fd6..2d1a545e727c 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c @@ -553,6 +553,10 @@ static const struct of_device_id mtk_vcodec_match[] = =3D { .compatible =3D "mediatek,mt8196-vcodec-dec", .data =3D &mtk_vdec_8196_pdata, }, + { + .compatible =3D "mediatek,mt8189-vcodec-dec", + .data =3D &mtk_vdec_8189_pdata, + }, {}, }; =20 diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= stateless.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec= _stateless.c index d249a8774948..9e43c54f8c4d 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statele= ss.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statele= ss.c @@ -1013,3 +1013,21 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8186_pdat= a =3D { .hw_arch =3D MTK_VDEC_PURE_SINGLE_CORE, .chip_name =3D 8186, }; + +const struct mtk_vcodec_dec_pdata mtk_vdec_8189_pdata =3D { + .init_vdec_params =3D mtk_init_vdec_params, + .ctrls_setup =3D mtk_vcodec_dec_ctrls_setup, + .vdec_vb2_ops =3D &mtk_vdec_request_vb2_ops, + .vdec_formats =3D mtk_video_formats, + .num_formats =3D &num_formats, + .default_out_fmt =3D &default_out_format, + .default_cap_fmt =3D &default_cap_format, + .uses_stateless_api =3D true, + .worker =3D mtk_vdec_worker, + .flush_decoder =3D mtk_vdec_flush_decoder, + .cap_to_disp =3D mtk_vdec_stateless_cap_to_disp, + .get_cap_buffer =3D vdec_get_cap_buffer, + .is_subdev_supported =3D true, + .hw_arch =3D MTK_VDEC_PURE_SINGLE_CORE, + .chip_name =3D 8189, +}; --=20 2.45.2 From nobody Fri Dec 19 21:50:00 2025 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 11660302177; Tue, 2 Dec 2025 07:40:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Tue, 02 Dec 2025 15:40:50 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.26; Tue, 2 Dec 2025 15:40:47 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1748.26 via Frontend Transport; Tue, 2 Dec 2025 15:40:45 +0800 From: Kyrie Wu To: Tiffany Lin , Andrew-CT Chen , Yunfei Dong , "Mauro Carvalho Chehab" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Kyrie Wu , Hans Verkuil , Nicolas Dufresne , Nathan Hebert , "Arnd Bergmann" , Irui Wang , George Sun , , , , , CC: Neil Armstrong , Andrzej Pietrasiewicz , Yilong Zhou Subject: [PATCH v6 04/10] media: mediatek: vcodec: add profile and level supporting for MT8189 Date: Tue, 2 Dec 2025 15:40:31 +0800 Message-ID: <20251202074038.3173-5-kyrie.wu@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20251202074038.3173-1-kyrie.wu@mediatek.com> References: <20251202074038.3173-1-kyrie.wu@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" add profile and level supporting for H264 and vp9 of MT8189 Signed-off-by: Kyrie Wu Reviewed-by: AngeloGioacchino Del Regno --- .../vcodec/decoder/mtk_vcodec_dec_drv.h | 16 ++ .../vcodec/decoder/mtk_vcodec_dec_stateful.c | 12 ++ .../vcodec/decoder/mtk_vcodec_dec_stateless.c | 177 ++++++++++-------- 3 files changed, 130 insertions(+), 75 deletions(-) diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= drv.h b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h index 2dbde8d00e6f..a8baeab98477 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h @@ -76,6 +76,16 @@ struct vdec_pic_info { unsigned int reserved; }; =20 +/** + * struct mtk_vcodec_dec_params - decoder supported parameters + * @level: decoder supported vcodec level + * @profile: decoder supported vcodec profile + */ +struct mtk_vcodec_dec_params { + s64 level; + s64 profile; +}; + /** * struct mtk_vcodec_dec_pdata - compatible data for each IC * @init_vdec_params: init vdec params @@ -96,6 +106,9 @@ struct vdec_pic_info { * @is_subdev_supported: whether support parent-node architecture(subdev) * @uses_stateless_api: whether the decoder uses the stateless API with re= quests * @chip_name: platforms configuration values + * @h264_params: H264 decoder default supported params + * @h265_params: H265 decoder default supported params + * @vp9_params: VP9 decoder default supported params */ struct mtk_vcodec_dec_pdata { void (*init_vdec_params)(struct mtk_vcodec_dec_ctx *ctx); @@ -118,6 +131,9 @@ struct mtk_vcodec_dec_pdata { bool is_subdev_supported; bool uses_stateless_api; unsigned int chip_name; + struct mtk_vcodec_dec_params h264_params; + struct mtk_vcodec_dec_params h265_params; + struct mtk_vcodec_dec_params vp9_params; }; =20 /** diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= stateful.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= stateful.c index 8ddb61670dc6..a47906b9d717 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statefu= l.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statefu= l.c @@ -619,4 +619,16 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8173_pdata = =3D { .is_subdev_supported =3D false, .hw_arch =3D MTK_VDEC_PURE_SINGLE_CORE, .chip_name =3D 8173, + .h264_params =3D { + .level =3D V4L2_MPEG_VIDEO_H264_LEVEL_4_1, + .profile =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, + }, + .h265_params =3D { + .level =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_4, + .profile =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE, + }, + .vp9_params =3D { + .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_4_0, + .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_1, + }, }; diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= stateless.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec= _stateless.c index 9e43c54f8c4d..dc3e9a2ccc2c 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statele= ss.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statele= ss.c @@ -549,106 +549,49 @@ static const struct v4l2_ctrl_ops mtk_vcodec_dec_ctr= l_ops =3D { static void mtk_vcodec_dec_fill_h264_level(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_name) { - case 8192: - case 8188: - cfg->max =3D V4L2_MPEG_VIDEO_H264_LEVEL_5_2; - break; - case 8195: - case 8196: - cfg->max =3D V4L2_MPEG_VIDEO_H264_LEVEL_6_0; - break; - case 8183: - case 8186: - cfg->max =3D V4L2_MPEG_VIDEO_H264_LEVEL_4_2; - break; - default: - cfg->max =3D V4L2_MPEG_VIDEO_H264_LEVEL_4_1; - break; - } + struct mtk_vcodec_dec_dev *pdev =3D ctx->dev; + + cfg->max =3D pdev->vdec_pdata->h264_params.level; } =20 static void mtk_vcodec_dec_fill_h264_profile(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_name) { - case 8188: - case 8195: - case 8196: - cfg->max =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10; - break; - default: - cfg->max =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH; - break; - } + struct mtk_vcodec_dec_dev *pdev =3D ctx->dev; + + cfg->max =3D pdev->vdec_pdata->h264_params.profile; } =20 static void mtk_vcodec_dec_fill_h265_level(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_name) { - case 8188: - cfg->max =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1; - break; - case 8195: - case 8196: - cfg->max =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2; - break; - default: - cfg->max =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_4; - break; - } + struct mtk_vcodec_dec_dev *pdev =3D ctx->dev; + + cfg->max =3D pdev->vdec_pdata->h265_params.level; } =20 static void mtk_vcodec_dec_fill_h265_profile(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_name) { - case 8188: - case 8195: - case 8196: - cfg->max =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10; - break; - default: - cfg->max =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE; - break; - } + struct mtk_vcodec_dec_dev *pdev =3D ctx->dev; + + cfg->max =3D pdev->vdec_pdata->h265_params.profile; } =20 static void mtk_vcodec_dec_fill_vp9_level(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_name) { - case 8192: - case 8188: - cfg->max =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_1; - break; - case 8195: - case 8196: - cfg->max =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_2; - break; - case 8186: - cfg->max =3D V4L2_MPEG_VIDEO_VP9_LEVEL_4_1; - break; - default: - cfg->max =3D V4L2_MPEG_VIDEO_VP9_LEVEL_4_0; - break; - } + struct mtk_vcodec_dec_dev *pdev =3D ctx->dev; + + cfg->max =3D pdev->vdec_pdata->vp9_params.level; } =20 static void mtk_vcodec_dec_fill_vp9_profile(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_name) { - case 8188: - case 8195: - case 8196: - cfg->max =3D V4L2_MPEG_VIDEO_VP9_PROFILE_2; - break; - default: - cfg->max =3D V4L2_MPEG_VIDEO_VP9_PROFILE_1; - break; - } + struct mtk_vcodec_dec_dev *pdev =3D ctx->dev; + + cfg->max =3D pdev->vdec_pdata->vp9_params.profile; } =20 static void mtk_vcodec_dec_reset_controls(struct v4l2_ctrl_config *cfg, @@ -887,6 +830,18 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8183_pdata = =3D { .is_subdev_supported =3D false, .hw_arch =3D MTK_VDEC_PURE_SINGLE_CORE, .chip_name =3D 8183, + .h264_params =3D { + .level =3D V4L2_MPEG_VIDEO_H264_LEVEL_4_2, + .profile =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, + }, + .h265_params =3D { + .level =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_4, + .profile =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE, + }, + .vp9_params =3D { + .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_4_0, + .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_1, + }, }; =20 /* This platform data is used for one lat and one core architecture. */ @@ -923,6 +878,18 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8188_pdata = =3D { .is_subdev_supported =3D true, .hw_arch =3D MTK_VDEC_LAT_SINGLE_CORE, .chip_name =3D 8188, + .h264_params =3D { + .level =3D V4L2_MPEG_VIDEO_H264_LEVEL_5_2, + .profile =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10, + }, + .h265_params =3D { + .level =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1, + .profile =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, + }, + .vp9_params =3D { + .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_1, + .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_2, + }, }; =20 const struct mtk_vcodec_dec_pdata mtk_vdec_8192_pdata =3D { @@ -941,6 +908,18 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8192_pdata = =3D { .is_subdev_supported =3D true, .hw_arch =3D MTK_VDEC_LAT_SINGLE_CORE, .chip_name =3D 8192, + .h264_params =3D { + .level =3D V4L2_MPEG_VIDEO_H264_LEVEL_5_2, + .profile =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, + }, + .h265_params =3D { + .level =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_4, + .profile =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE, + }, + .vp9_params =3D { + .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_1, + .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_1, + }, }; =20 const struct mtk_vcodec_dec_pdata mtk_vdec_8195_pdata =3D { @@ -959,6 +938,18 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8195_pdata = =3D { .is_subdev_supported =3D true, .hw_arch =3D MTK_VDEC_LAT_SINGLE_CORE, .chip_name =3D 8195, + .h264_params =3D { + .level =3D V4L2_MPEG_VIDEO_H264_LEVEL_6_0, + .profile =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10, + }, + .h265_params =3D { + .level =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2, + .profile =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, + }, + .vp9_params =3D { + .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_2, + .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_2, + }, }; =20 const struct mtk_vcodec_dec_pdata mtk_vdec_8196_pdata =3D { @@ -977,6 +968,18 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8196_pdata = =3D { .is_subdev_supported =3D true, .hw_arch =3D MTK_VDEC_LAT_SINGLE_CORE, .chip_name =3D 8196, + .h264_params =3D { + .level =3D V4L2_MPEG_VIDEO_H264_LEVEL_6_0, + .profile =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10, + }, + .h265_params =3D { + .level =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2, + .profile =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, + }, + .vp9_params =3D { + .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_2, + .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_2, + }, }; =20 const struct mtk_vcodec_dec_pdata mtk_vdec_single_core_pdata =3D { @@ -1012,6 +1015,18 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8186_pdat= a =3D { .is_subdev_supported =3D true, .hw_arch =3D MTK_VDEC_PURE_SINGLE_CORE, .chip_name =3D 8186, + .h264_params =3D { + .level =3D V4L2_MPEG_VIDEO_H264_LEVEL_4_2, + .profile =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, + }, + .h265_params =3D { + .level =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_4, + .profile =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE, + }, + .vp9_params =3D { + .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_4_1, + .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_1, + }, }; =20 const struct mtk_vcodec_dec_pdata mtk_vdec_8189_pdata =3D { @@ -1030,4 +1045,16 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8189_pdat= a =3D { .is_subdev_supported =3D true, .hw_arch =3D MTK_VDEC_PURE_SINGLE_CORE, .chip_name =3D 8189, + .h264_params =3D { + .level =3D V4L2_MPEG_VIDEO_H264_LEVEL_5_2, + .profile =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10, + }, + .h265_params =3D { + .level =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_4, + .profile =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE, + }, + .vp9_params =3D { + .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_2, + .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_2, + }, }; --=20 2.45.2 From nobody Fri Dec 19 21:50:00 2025 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 08E7D301485; Tue, 2 Dec 2025 07:40:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; 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Tue, 02 Dec 2025 15:40:49 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS09N2.mediatek.inc (172.21.101.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.26; Tue, 2 Dec 2025 15:40:48 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1748.26 via Frontend Transport; Tue, 2 Dec 2025 15:40:46 +0800 From: Kyrie Wu To: Tiffany Lin , Andrew-CT Chen , Yunfei Dong , "Mauro Carvalho Chehab" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Kyrie Wu , Hans Verkuil , Nicolas Dufresne , Nathan Hebert , "Arnd Bergmann" , Irui Wang , George Sun , , , , , CC: Neil Armstrong , Andrzej Pietrasiewicz , Yilong Zhou Subject: [PATCH v6 05/10] media: mediatek: vcodec: refactor setup dst buffer metadata interface for VP9 decoder Date: Tue, 2 Dec 2025 15:40:32 +0800 Message-ID: <20251202074038.3173-6-kyrie.wu@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20251202074038.3173-1-kyrie.wu@mediatek.com> References: <20251202074038.3173-1-kyrie.wu@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" Previously, calling vdec_vp9_slice_setup_single_from_src_to_dst with v4l2_m2m_next_src_buf to obtain both buffers resulted in -EINVAL, interrupting the decoding process. To resolve this, the interface should be updated to set both src and dst buffers for metadata configuration. Signed-off-by: Kyrie Wu --- .../vcodec/decoder/vdec/vdec_vp9_req_lat_if.c | 21 ++++++++++--------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_r= eq_lat_if.c b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_= req_lat_if.c index fa0f406f7726..9513ddde7c7c 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_= if.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_= if.c @@ -696,21 +696,22 @@ static int vdec_vp9_slice_tile_offset(int idx, int mi= _num, int tile_log2) return min(offset, mi_num); } =20 -static -int vdec_vp9_slice_setup_single_from_src_to_dst(struct vdec_vp9_slice_inst= ance *instance) +static int vdec_vp9_slice_setup_single_from_src_to_dst(struct vdec_vp9_sli= ce_instance *instance, + struct mtk_vcodec_mem *bs, + struct vdec_fb *fb) { - struct vb2_v4l2_buffer *src; - struct vb2_v4l2_buffer *dst; + struct mtk_video_dec_buf *src_buf_info; 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charset="utf-8" From: Kyrie Wu add config to support prob size both 3840 and 2560. Signed-off-by: Kyrie Wu --- .../platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h | 2 ++ .../mediatek/vcodec/decoder/mtk_vcodec_dec_stateful.c | 1 + .../mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c | 7 +++++++ .../mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c | 4 ++-- 4 files changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= drv.h b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h index a8baeab98477..ecf0d7ad0d54 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h @@ -80,10 +80,12 @@ struct vdec_pic_info { * struct mtk_vcodec_dec_params - decoder supported parameters * @level: decoder supported vcodec level * @profile: decoder supported vcodec profile + * @prob_size: vp9 decoder prob size */ struct mtk_vcodec_dec_params { s64 level; s64 profile; + size_t prob_size; }; =20 /** diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= stateful.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= stateful.c index a47906b9d717..99c252e0a2e1 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statefu= l.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statefu= l.c @@ -630,5 +630,6 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8173_pdata = =3D { .vp9_params =3D { .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_4_0, .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_1, + .prob_size =3D 2560, }, }; diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= stateless.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec= _stateless.c index dc3e9a2ccc2c..f18aafd08c76 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statele= ss.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statele= ss.c @@ -841,6 +841,7 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8183_pdata = =3D { .vp9_params =3D { .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_4_0, .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_1, + .prob_size =3D 2560, }, }; =20 @@ -889,6 +890,7 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8188_pdata = =3D { .vp9_params =3D { .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_1, .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_2, + .prob_size =3D 2560, }, }; =20 @@ -919,6 +921,7 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8192_pdata = =3D { .vp9_params =3D { .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_1, .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_1, + .prob_size =3D 2560, }, }; =20 @@ -949,6 +952,7 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8195_pdata = =3D { .vp9_params =3D { .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_2, .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_2, + .prob_size =3D 2560, }, }; =20 @@ -979,6 +983,7 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8196_pdata = =3D { .vp9_params =3D { .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_2, .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_2, + .prob_size =3D 3840, }, }; =20 @@ -1026,6 +1031,7 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8186_pdata= =3D { .vp9_params =3D { .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_4_1, .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_1, + .prob_size =3D 2560, }, }; =20 @@ -1056,5 +1062,6 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8189_pdata= =3D { .vp9_params =3D { .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_2, .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_2, + .prob_size =3D 3840, }, }; diff --git a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_r= eq_lat_if.c b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_= req_lat_if.c index 9513ddde7c7c..36a87b455d11 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_= if.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_= if.c @@ -22,7 +22,6 @@ #define VP9_RESET_FRAME_CONTEXT_ALL 3 =20 #define VP9_TILE_BUF_SIZE 4096 -#define VP9_PROB_BUF_SIZE 2560 #define VP9_COUNTS_BUF_SIZE 16384 =20 #define HDR_FLAG(x) (!!((hdr)->flags & V4L2_VP9_FRAME_FLAG_##x)) @@ -546,6 +545,7 @@ static int vdec_vp9_slice_alloc_working_buffer(struct v= dec_vp9_slice_instance *i struct vdec_vp9_slice_vsi *vsi) { struct mtk_vcodec_dec_ctx *ctx =3D instance->ctx; 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Tue, 02 Dec 2025 15:40:52 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS09N2.mediatek.inc (172.21.101.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.26; Tue, 2 Dec 2025 15:40:50 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1748.26 via Frontend Transport; Tue, 2 Dec 2025 15:40:49 +0800 From: Kyrie Wu To: Tiffany Lin , Andrew-CT Chen , Yunfei Dong , "Mauro Carvalho Chehab" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Kyrie Wu , Hans Verkuil , Nicolas Dufresne , Nathan Hebert , "Arnd Bergmann" , Irui Wang , George Sun , , , , , CC: Neil Armstrong , Andrzej Pietrasiewicz , Yilong Zhou Subject: [PATCH v6 07/10] media: mediatek: vcodec: Fix vp9 4096x2176 fail for profile2 Date: Tue, 2 Dec 2025 15:40:34 +0800 Message-ID: <20251202074038.3173-8-kyrie.wu@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20251202074038.3173-1-kyrie.wu@mediatek.com> References: <20251202074038.3173-1-kyrie.wu@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" The DRAM address of the VP9 decoder tile info buffers may require as much as 36bits for 4096x2176 resolution. Fold the 4 most significant bits into the lower (padding) four bits of address. Fixes: 5d418351ca8f1 ("media: mediatek: vcodec: support stateless VP9 decod= ing") Signed-off-by: Kyrie Wu Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Nicolas Dufresne --- .../mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_r= eq_lat_if.c b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_= req_lat_if.c index 36a87b455d11..eca6280098be 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_= if.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_= if.c @@ -1134,9 +1134,17 @@ static int vdec_vp9_slice_setup_tile_buffer(struct v= dec_vp9_slice_instance *inst return -EINVAL; } tiles->size[i][j] =3D size; + /* + * If the system supports 64-bit DMA addresses, the upper 4 bits + * of the address are also encoded into the buffer entry. + * The buffer pointer (tb) is incremented after each entry is written. + */ if (tiles->mi_rows[i]) { *tb++ =3D (size << 3) + ((offset << 3) & 0x7f); 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charset="utf-8" change media register device node number to a correct value. The vfd minor is used to record the number of registered video device nodes. The mdev_dec.devnode minor counter is used to record the number of registered media device nodes. Fixes: 41f03c673cb7b ("media: mediatek: vcodec: replace pr_* with dev_* for= v4l2 debug message") Signed-off-by: Kyrie Wu Reviewed-by: Nicolas Dufresne --- .../platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= drv.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c index 2d1a545e727c..bf6e792283a1 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c @@ -493,7 +493,8 @@ static int mtk_vcodec_probe(struct platform_device *pde= v) goto err_media_reg; } =20 - dev_dbg(&pdev->dev, "media registered as /dev/media%d", vfd_dec->minor); + dev_dbg(&pdev->dev, "media registered as /dev/media%d", + dev->mdev_dec.devnode->minor); } =20 mtk_vcodec_dbgfs_init(dev, false); --=20 2.45.2 From nobody Fri Dec 19 21:50:00 2025 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 19AB8303A28; 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charset="utf-8" Add MT8189 encoder compatible string to distinguish former ICs MTK's. Compared with MT8196, the maximum resolution of MT8189 encoder is only 4K, and the fps is only 30, which cannot reach the highest parameter of MT8196: level6.2, 8K@60fps. Compared with MT8188, the level can only support 5.1, which is less than 5.2 of MT8188. But the maximum bitrate is 100Mbps, which is twice that of MT8188. And MT8189 could support NBM mode. Signed-off-by: Kyrie Wu Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno --- .../devicetree/bindings/media/mediatek,vcodec-encoder.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-encode= r.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.ya= ml index bb4dbf23ccc5..7f355470b63c 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml @@ -22,6 +22,7 @@ properties: - mediatek,mt8173-vcodec-enc - mediatek,mt8183-vcodec-enc - mediatek,mt8188-vcodec-enc + - mediatek,mt8189-vcodec-enc - mediatek,mt8192-vcodec-enc - mediatek,mt8195-vcodec-enc - mediatek,mt8196-vcodec-enc @@ -100,6 +101,7 @@ allOf: enum: - mediatek,mt8183-vcodec-enc - mediatek,mt8188-vcodec-enc + - mediatek,mt8189-vcodec-enc - mediatek,mt8192-vcodec-enc - mediatek,mt8195-vcodec-enc =20 --=20 2.45.2 From nobody Fri Dec 19 21:50:00 2025 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7A1D5303CAE; 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charset="utf-8" add MT8189 compatible data to initialize platform data for encoder. Signed-off-by: Kyrie Wu Reviewed-by: AngeloGioacchino Del Regno --- .../mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_= drv.c b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c index 6b3d2e72fad9..2cc92a8f7a0d 100644 --- a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c +++ b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c @@ -467,6 +467,19 @@ static const struct mtk_vcodec_enc_pdata mt8196_pdata = =3D { .set_dma_bit_mask =3D true, }; =20 +static const struct mtk_vcodec_enc_pdata mt8189_pdata =3D { + .venc_model_num =3D 8189, + .capture_formats =3D mtk_video_formats_capture_h264, + .num_capture_formats =3D ARRAY_SIZE(mtk_video_formats_capture_h264), + .output_formats =3D mtk_video_formats_output, + .num_output_formats =3D ARRAY_SIZE(mtk_video_formats_output), + .min_bitrate =3D 64, + .max_bitrate =3D 100000000, + .core_id =3D VENC_SYS, + .uses_common_fw_iface =3D true, + .set_dma_bit_mask =3D true, +}; + static const struct of_device_id mtk_vcodec_enc_match[] =3D { {.compatible =3D "mediatek,mt8173-vcodec-enc", .data =3D &mt8173_avc_pdata}, @@ -477,6 +490,7 @@ static const struct of_device_id mtk_vcodec_enc_match[]= =3D { {.compatible =3D "mediatek,mt8192-vcodec-enc", .data =3D &mt8192_pdata}, {.compatible =3D "mediatek,mt8195-vcodec-enc", .data =3D &mt8195_pdata}, {.compatible =3D "mediatek,mt8196-vcodec-enc", .data =3D &mt8196_pdata}, + {.compatible =3D "mediatek,mt8189-vcodec-enc", .data =3D &mt8189_pdata}, {}, }; MODULE_DEVICE_TABLE(of, mtk_vcodec_enc_match); --=20 2.45.2