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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2025 16:32:46.4718 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3bfdee40-09bc-430e-e8a0-08de30f742a6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB55.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5793 Content-Type: text/plain; charset="utf-8" Add device tree support to the CMDQV driver to enable usage on Tegra264 SoCs. The implementation parses the nvidia,cmdqv phandle from the SMMU device tree node to associate each SMMU with its corresponding CMDQV instance based on compatible string. Remove the dependency from Kconfig as the driver now supports both ACPI and device tree initialization through conditional compilation and ARM_SMMU_V3 depends on ARM64 which implies at least OF. Reviewed-by: Nicolin Chen Signed-off-by: Ashish Mhetre --- drivers/iommu/arm/Kconfig | 1 - drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 32 ++++++++++++++ .../iommu/arm/arm-smmu-v3/tegra241-cmdqv.c | 43 ++++++++++++++++++- 3 files changed, 74 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/Kconfig b/drivers/iommu/arm/Kconfig index ef42bbe07dbe..5fac08b89dee 100644 --- a/drivers/iommu/arm/Kconfig +++ b/drivers/iommu/arm/Kconfig @@ -121,7 +121,6 @@ config ARM_SMMU_V3_KUNIT_TEST =20 config TEGRA241_CMDQV bool "NVIDIA Tegra241 CMDQ-V extension support for ARM SMMUv3" - depends on ACPI help Support for NVIDIA CMDQ-Virtualization extension for ARM SMMUv3. The CMDQ-V extension is similar to v3.3 ECMDQ for multi command queues diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index a33fbd12a0dd..206dffabc9c0 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -4530,6 +4530,35 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_= device *smmu) return 0; } =20 +#ifdef CONFIG_TEGRA241_CMDQV +static void tegra_cmdqv_dt_probe(struct device_node *smmu_node, + struct arm_smmu_device *smmu) +{ + struct platform_device *pdev; + struct device_node *np; + + np =3D of_parse_phandle(smmu_node, "nvidia,cmdqv", 0); + if (!np) + return; + + pdev =3D of_find_device_by_node(np); + of_node_put(np); + if (!pdev) + return; + + smmu->impl_dev =3D &pdev->dev; + smmu->options |=3D ARM_SMMU_OPT_TEGRA241_CMDQV; + dev_info(smmu->dev, "found companion CMDQV device: %s\n", + dev_name(smmu->impl_dev)); + put_device(&pdev->dev); +} +#else +static void tegra_cmdqv_dt_probe(struct device_node *smmu_node, + struct arm_smmu_device *smmu) +{ +} +#endif + #ifdef CONFIG_ACPI #ifdef CONFIG_TEGRA241_CMDQV static void acpi_smmu_dsdt_probe_tegra241_cmdqv(struct acpi_iort_node *nod= e, @@ -4634,6 +4663,9 @@ static int arm_smmu_device_dt_probe(struct platform_d= evice *pdev, if (of_dma_is_coherent(dev->of_node)) smmu->features |=3D ARM_SMMU_FEAT_COHERENCY; =20 + if (of_device_is_compatible(dev->of_node, "nvidia,tegra264-smmu")) + tegra_cmdqv_dt_probe(dev->of_node, smmu); + return ret; } =20 diff --git a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c b/drivers/iommu= /arm/arm-smmu-v3/tegra241-cmdqv.c index 378104cd395e..2608bf6518b4 100644 --- a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c +++ b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c @@ -11,6 +11,8 @@ #include #include #include +#include +#include =20 #include =20 @@ -917,6 +919,26 @@ tegra241_cmdqv_find_acpi_resource(struct device *dev, = int *irq) return res; } =20 +static struct resource * +tegra241_cmdqv_find_dt_resource(struct device *dev, int *irq) +{ + struct platform_device *pdev =3D to_platform_device(dev); + struct resource *res; + + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(dev, "no memory resource found for CMDQV\n"); + return NULL; + } + + if (irq) + *irq =3D platform_get_irq_optional(pdev, 0); + if (!irq || *irq <=3D 0) + dev_warn(dev, "no interrupt. errors will not be reported\n"); + + return res; +} + static int tegra241_cmdqv_init_structures(struct arm_smmu_device *smmu) { struct tegra241_cmdqv *cmdqv =3D @@ -1048,11 +1070,14 @@ struct arm_smmu_device *tegra241_cmdqv_probe(struct= arm_smmu_device *smmu) =20 if (!smmu->dev->of_node) res =3D tegra241_cmdqv_find_acpi_resource(smmu->impl_dev, &irq); + else + res =3D tegra241_cmdqv_find_dt_resource(smmu->impl_dev, &irq); if (!res) goto out_fallback; =20 new_smmu =3D __tegra241_cmdqv_probe(smmu, res, irq); - kfree(res); + if (!smmu->dev->of_node) + kfree(res); =20 if (new_smmu) return new_smmu; @@ -1346,4 +1371,20 @@ tegra241_cmdqv_init_vintf_user(struct arm_vsmmu *vsm= mu, return ret; } =20 +static const struct of_device_id tegra241_cmdqv_of_match[] =3D { + { .compatible =3D "nvidia,tegra264-cmdqv" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, tegra241_cmdqv_of_match); + +static struct platform_driver tegra241_cmdqv_driver =3D { + .driver =3D { + .name =3D "tegra241-cmdqv", + .of_match_table =3D tegra241_cmdqv_of_match, + }, +}; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2025 16:32:47.1794 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 61551213-d5f9-4f24-a1d1-08de30f74312 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB53.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB8735 Content-Type: text/plain; charset="utf-8" The Command Queue Virtualization (CMDQV) hardware is part of the SMMUv3 implementation on NVIDIA Tegra SoCs. It assists in virtualizing the command queue for the SMMU. Add a new device tree binding document for nvidia,tegra264-cmdqv. Also update the arm,smmu-v3 binding to include an optional nvidia,cmdqv property. This property is a phandle to the CMDQV device node, allowing the SMMU driver to associate with its corresponding CMDQV instance. Restrict this property usage to Nvidia Tegra264 only. Signed-off-by: Ashish Mhetre --- .../bindings/iommu/arm,smmu-v3.yaml | 30 ++++++++++++- .../bindings/iommu/nvidia,tegra264-cmdqv.yaml | 42 +++++++++++++++++++ 2 files changed, 70 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/iommu/nvidia,tegra264= -cmdqv.yaml diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Doc= umentation/devicetree/bindings/iommu/arm,smmu-v3.yaml index 75fcf4cb52d9..1c03482e4c61 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml @@ -20,7 +20,12 @@ properties: $nodename: pattern: "^iommu@[0-9a-f]*" compatible: - const: arm,smmu-v3 + oneOf: + - const: arm,smmu-v3 + - items: + - enum: + - nvidia,tegra264-smmu + - const: arm,smmu-v3 =20 reg: maxItems: 1 @@ -58,6 +63,15 @@ properties: =20 msi-parent: true =20 + nvidia,cmdqv: + description: | + A phandle to its pairing CMDQV extension for an implementation on NV= IDIA + Tegra SoC. + + If this property is absent, CMDQ-Virtualization won't be used and SM= MU + will only use its own CMDQ. + $ref: /schemas/types.yaml#/definitions/phandle + hisilicon,broken-prefetch-cmd: type: boolean description: Avoid sending CMD_PREFETCH_* commands to the SMMU. @@ -69,6 +83,17 @@ properties: register access with page 0 offsets. Set for Cavium ThunderX2 silico= n that doesn't support SMMU page1 register space. =20 +allOf: + - if: + not: + properties: + compatible: + contains: + const: nvidia,tegra264-smmu + then: + properties: + nvidia,cmdqv: false + required: - compatible - reg @@ -82,7 +107,7 @@ examples: #include =20 iommu@2b400000 { - compatible =3D "arm,smmu-v3"; + compatible =3D "nvidia,tegra264-smmu", "arm,smmu-v3"; reg =3D <0x2b400000 0x20000>; interrupts =3D , , @@ -92,4 +117,5 @@ examples: dma-coherent; #iommu-cells =3D <1>; msi-parent =3D <&its 0xff0000>; + nvidia,cmdqv =3D <&cmdqv>; }; diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.= yaml b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml new file mode 100644 index 000000000000..3f5006a59805 --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iommu/nvidia,tegra264-cmdqv.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra264 CMDQV + +description: + The CMDQ-Virtualization hardware block is part of the SMMUv3 implementat= ion + on Tegra264 SoCs. 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2025 16:32:48.8201 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6905fd36-009d-4ae6-3009-08de30f7440d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB53.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5594 Content-Type: text/plain; charset="utf-8" The Command Queue Virtualization (CMDQV) hardware is part of the SMMUv3 implementation on NVIDIA Tegra SoCs. It assists in virtualizing the command queue for the SMMU. Update SMMU compatible strings to use nvidia,tegra264-smmu to enable CMDQV support. Add device tree nodes for the CMDQV hardware and enable them on the tegra264-p3834 platform where SMMUs are enabled. Each SMMU instance is paired with its corresponding CMDQV instance via the nvidia,cmdqv property. Signed-off-by: Ashish Mhetre --- .../arm64/boot/dts/nvidia/tegra264-p3834.dtsi | 8 +++ arch/arm64/boot/dts/nvidia/tegra264.dtsi | 55 +++++++++++++++++-- 2 files changed, 58 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi b/arch/arm64/bo= ot/dts/nvidia/tegra264-p3834.dtsi index 06795c82427a..7e2c3e66c2ab 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi @@ -23,8 +23,16 @@ iommu@5000000 { status =3D "okay"; }; =20 + cmdqv@5200000 { + status =3D "okay"; + }; + iommu@6000000 { status =3D "okay"; }; + + cmdqv@6200000 { + status =3D "okay"; + }; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts= /nvidia/tegra264.dtsi index f137565da804..5124715caeb3 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -3361,7 +3361,7 @@ bus@8100000000 { <0x02 0x00000000 0xd0 0x00000000 0x08 0x80000000>; /* ECAM, prefetchab= le memory, I/O */ =20 smmu1: iommu@5000000 { - compatible =3D "arm,smmu-v3"; + compatible =3D "nvidia,tegra264-smmu", "arm,smmu-v3"; reg =3D <0x00 0x5000000 0x0 0x200000>; interrupts =3D , ; @@ -3370,10 +3370,19 @@ smmu1: iommu@5000000 { =20 #iommu-cells =3D <1>; dma-coherent; + nvidia,cmdqv =3D <&cmdqv1>; + }; + + cmdqv1: cmdqv@5200000 { + compatible =3D "nvidia,tegra264-cmdqv"; + status =3D "disabled"; + + reg =3D <0x00 0x5200000 0x0 0x830000>; + interrupts =3D ; }; =20 smmu2: iommu@6000000 { - compatible =3D "arm,smmu-v3"; + compatible =3D "nvidia,tegra264-smmu", "arm,smmu-v3"; reg =3D <0x00 0x6000000 0x0 0x200000>; interrupts =3D , ; @@ -3382,6 +3391,15 @@ smmu2: iommu@6000000 { =20 #iommu-cells =3D <1>; dma-coherent; + nvidia,cmdqv =3D <&cmdqv2>; + }; + + cmdqv2: cmdqv@6200000 { + compatible =3D "nvidia,tegra264-cmdqv"; + status =3D "disabled"; + + reg =3D <0x00 0x6200000 0x0 0x830000>; + interrupts =3D ; }; =20 mc: memory-controller@8020000 { @@ -3437,7 +3455,7 @@ emc: external-memory-controller@8800000 { }; =20 smmu0: iommu@a000000 { - compatible =3D "arm,smmu-v3"; + compatible =3D "nvidia,tegra264-smmu", "arm,smmu-v3"; reg =3D <0x00 0xa000000 0x0 0x200000>; interrupts =3D , ; @@ -3446,10 +3464,19 @@ smmu0: iommu@a000000 { =20 #iommu-cells =3D <1>; dma-coherent; + nvidia,cmdqv =3D <&cmdqv0>; + }; + + cmdqv0: cmdqv@a200000 { + compatible =3D "nvidia,tegra264-cmdqv"; + status =3D "disabled"; + + reg =3D <0x00 0xa200000 0x0 0x830000>; + interrupts =3D ; }; =20 smmu4: iommu@b000000 { - compatible =3D "arm,smmu-v3"; + compatible =3D "nvidia,tegra264-smmu", "arm,smmu-v3"; reg =3D <0x00 0xb000000 0x0 0x200000>; interrupts =3D , ; @@ -3458,6 +3485,15 @@ smmu4: iommu@b000000 { =20 #iommu-cells =3D <1>; dma-coherent; + nvidia,cmdqv =3D <&cmdqv4>; + }; + + cmdqv4: cmdqv@b200000 { + compatible =3D "nvidia,tegra264-cmdqv"; + status =3D "disabled"; + + reg =3D <0x00 0xb200000 0x0 0x830000>; + interrupts =3D ; }; =20 i2c14: i2c@c410000 { @@ -3690,7 +3726,7 @@ bus@8800000000 { ranges =3D <0x00 0x00000000 0x88 0x00000000 0x01 0x00000000>; =20 smmu3: iommu@6000000 { - compatible =3D "arm,smmu-v3"; + compatible =3D "nvidia,tegra264-smmu", "arm,smmu-v3"; reg =3D <0x00 0x6000000 0x0 0x200000>; interrupts =3D , ; @@ -3699,6 +3735,15 @@ smmu3: iommu@6000000 { =20 #iommu-cells =3D <1>; dma-coherent; + nvidia,cmdqv =3D <&cmdqv3>; + }; + + cmdqv3: cmdqv@6200000 { + compatible =3D "nvidia,tegra264-cmdqv"; + status =3D "disabled"; + + reg =3D <0x00 0x6200000 0x0 0x830000>; + interrupts =3D ; }; =20 hda@90b0000 { --=20 2.25.1