From nobody Mon Dec 1 21:31:53 2025 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 620BD2580F9; Mon, 1 Dec 2025 11:30:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588633; cv=none; b=k546PynBc9zwiTjzFekE6XKlAAzb3IhSn1Uw5hgMVi4IADmTVhkUb0hum41PP4itzsL7mXi49m8ZKCSxEwzbxnCt2y3tR5xXP0dw1IJZA76etK/tD8cmEiBIhvwlWR+c+OQ4y8EXlYKQnpoezpnVf9slpyBBegPiAB1EIEIWOE8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588633; c=relaxed/simple; bh=ncUoSBBF0siZIgTRVQ+AGl9Oln+p2ahq5ALrIeaQF3U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=R16pSleCuUqeCMDmc2UmHGR14LG9H9VH/30Xt7J+a4mCwIYCgf9eCrjImz2Olqd6aNgSGmt8bMO8xWba3l5PbgdKt15p/MnWUIUpUOV1mr1HzNaXgG0YdS/7m5rDMbGS6qDRIvMslpj4+6UDRwD+5qi1OHFchuKu5/J6UVqvMyA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: V19apZybQK2l3lOAZJ5XfQ== X-CSE-MsgGUID: PEWELNlaTImz9L/5/yjLhA== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 01 Dec 2025 20:30:25 +0900 Received: from demon-pc.localdomain (unknown [10.226.93.83]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id C9E0141F1B9E; Mon, 1 Dec 2025 20:30:21 +0900 (JST) From: Cosmin Tanislav To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Cosmin Tanislav Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH v2 1/4] dt-bindings: interrupt-controller: document RZ/{T2H,N2H} ICU Date: Mon, 1 Dec 2025 13:29:30 +0200 Message-ID: <20251201112933.488801-2-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251201112933.488801-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20251201112933.488801-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Renesas RZ/T2H (R9A09G077) and Renesas RZ/N2H (R9A09G087) SoCs have an Interrupt Controller (ICU) block that routes external interrupts to the GIC's SPIs, with the ability of level-translation, and can also produce software interrupts and aggregate error interrupts. It has 16 software triggered interrupts (INTCPUn), 16 external pin interrupts (IRQn), a System error interrupt (SEI), two Cortex-A55 error interrupts (CA55_ERRn), two Cortex-R52 error interrupts for each of the two cores (CR52x_ERRn), two Peripheral error interrupts (PERI_ERRn), two DSMIF error interrupts (DSMIF_ERRn), and two ENCIF error interrupts (ENCIF_ERRn). The IRQn and SEI interrupts are exposed externally, while the others are software triggered. INTCPU0 to INTCPU13, IRQ 0 to IRQ13 are non-safety interrupts, while INTCPU14, INTCPU15, IRQ14, IRQ15 and SEI are safety interrupts, and are exposed via a separate register space. Document them, and use RZ/T2H as a fallback for RZ/N2H as the ICU is entirely compatible. Signed-off-by: Cosmin Tanislav --- V2: * move reg property after compatible .../renesas,r9a09g077-icu.yaml | 236 ++++++++++++++++++ 1 file changed, 236 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= renesas,r9a09g077-icu.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas= ,r9a09g077-icu.yaml b/Documentation/devicetree/bindings/interrupt-controlle= r/renesas,r9a09g077-icu.yaml new file mode 100644 index 000000000000..78c01d14e765 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,r9a09g= 077-icu.yaml @@ -0,0 +1,236 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/renesas,r9a09g077-= icu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/{T2H,N2H} Interrupt Controller + +maintainers: + - Cosmin Tanislav + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +description: + The Interrupt Controller (ICU) handles software-triggered interrupts + (INTCPU), external interrupts (IRQ and SEI), error interrupts and DMAC + requests. + +properties: + compatible: + oneOf: + - const: renesas,r9a09g077-icu # RZ/T2H + + - items: + - enum: + - renesas,r9a09g087-icu # RZ/N2H + - const: renesas,r9a09g077-icu + + reg: + items: + - description: Non-safety registers (INTCPU0-13, IRQ0-13) + - description: Safety registers (INTCPU14-15, IRQ14-15, SEI) + + '#interrupt-cells': + description: The first cell is the SPI number of the interrupt, as per= user + manual. The second cell is used to specify the flag. + const: 2 + + '#address-cells': + const: 0 + + interrupt-controller: true + + interrupts: + items: + - description: Software interrupt 0 + - description: Software interrupt 1 + - description: Software interrupt 2 + - description: Software interrupt 3 + - description: Software interrupt 4 + - description: Software interrupt 5 + - description: Software interrupt 6 + - description: Software interrupt 7 + - description: Software interrupt 8 + - description: Software interrupt 9 + - description: Software interrupt 10 + - description: Software interrupt 11 + - description: Software interrupt 12 + - description: Software interrupt 13 + - description: Software interrupt 14 + - description: Software interrupt 15 + - description: External pin interrupt 0 + - description: External pin interrupt 1 + - description: External pin interrupt 2 + - description: External pin interrupt 3 + - description: External pin interrupt 4 + - description: External pin interrupt 5 + - description: External pin interrupt 6 + - description: External pin interrupt 7 + - description: External pin interrupt 8 + - description: External pin interrupt 9 + - description: External pin interrupt 10 + - description: External pin interrupt 11 + - description: External pin interrupt 12 + - description: External pin interrupt 13 + - description: External pin interrupt 14 + - description: External pin interrupt 15 + - description: System error interrupt + - description: Cortex-A55 error event 0 + - description: Cortex-A55 error event 1 + - description: Cortex-R52 CPU 0 error event 0 + - description: Cortex-R52 CPU 0 error event 1 + - description: Cortex-R52 CPU 1 error event 0 + - description: Cortex-R52 CPU 1 error event 1 + - description: Peripherals error event 0 + - description: Peripherals error event 1 + - description: DSMIF error event 0 + - description: DSMIF error event 1 + - description: ENCIF error event 0 + - description: ENCIF error event 1 + + interrupt-names: + items: + - const: intcpu0 + - const: intcpu1 + - const: intcpu2 + - const: intcpu3 + - const: intcpu4 + - const: intcpu5 + - const: intcpu6 + - const: intcpu7 + - const: intcpu8 + - const: intcpu9 + - const: intcpu10 + - const: intcpu11 + - const: intcpu12 + - const: intcpu13 + - const: intcpu14 + - const: intcpu15 + - const: irq0 + - const: irq1 + - const: irq2 + - const: irq3 + - const: irq4 + - const: irq5 + - const: irq6 + - const: irq7 + - const: irq8 + - const: irq9 + - const: irq10 + - const: irq11 + - const: irq12 + - const: irq13 + - const: irq14 + - const: irq15 + - const: sei + - const: ca55-err0 + - const: ca55-err1 + - const: cr520-err0 + - const: cr520-err1 + - const: cr521-err0 + - const: cr521-err1 + - const: peri-err0 + - const: peri-err1 + - const: dsmif-err0 + - const: dsmif-err1 + - const: encif-err0 + - const: encif-err1 + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - '#interrupt-cells' + - '#address-cells' + - interrupt-controller + - interrupts + - interrupt-names + - clocks + - power-domains + +unevaluatedProperties: false + +examples: + - | + #include + #include + + icu: interrupt-controller@802a0000 { + compatible =3D "renesas,r9a09g077-icu"; + reg =3D <0x802a0000 0x10000>, + <0x812a0000 0x50>; + #interrupt-cells =3D <2>; + #address-cells =3D <0>; + interrupt-controller; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "intcpu0", "intcpu1", "intcpu2", + "intcpu3", "intcpu4", "intcpu5", + "intcpu6", "intcpu7", "intcpu8", + "intcpu9", "intcpu10", "intcpu11", + "intcpu12", "intcpu13", "intcpu14", + "intcpu15", + "irq0", "irq1", "irq2", "irq3", + "irq4", "irq5", "irq6", "irq7", + "irq8", "irq9", "irq10", "irq11", + "irq12", "irq13", "irq14", "irq15", + "sei", + "ca55-err0", "ca55-err1", + "cr520-err0", "cr520-err1", + "cr521-err0", "cr521-err1", + "peri-err0", "peri-err1", + "dsmif-err0", "dsmif-err1", + "encif-err0", "encif-err1"; + clocks =3D <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; + power-domains =3D <&cpg>; + }; --=20 2.52.0 From nobody Mon Dec 1 21:31:53 2025 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3B2B925A33A; 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dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: TpYG/aJjQtagv7bmnD+QWg== X-CSE-MsgGUID: s5Mi2zJZSGmtvn+efgAc6w== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 01 Dec 2025 20:30:29 +0900 Received: from demon-pc.localdomain (unknown [10.226.93.83]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 0E12541F1B93; Mon, 1 Dec 2025 20:30:25 +0900 (JST) From: Cosmin Tanislav To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Cosmin Tanislav Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH v2 2/4] irqchip: add RZ/{T2H,N2H} Interrupt Controller (ICU) driver Date: Mon, 1 Dec 2025 13:29:31 +0200 Message-ID: <20251201112933.488801-3-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251201112933.488801-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20251201112933.488801-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Renesas RZ/T2H (R9A09G077) and Renesas RZ/N2H (R9A09G087) SoCs have an Interrupt Controller (ICU) that supports interrupts from external pins IRQ0 to IRQ15, and SEI, and software-triggered interrupts INTCPU0 to INTCPU15. INTCPU0 to INTCPU13, IRQ0 to IRQ13 are non-safety interrupts, while INTCPU14, INTCPU15, IRQ14, IRQ15 and SEI are safety interrupts, and are exposed via a separate register space. Signed-off-by: Cosmin Tanislav --- V2: * use 100 columns where necessary * move SEI comment above if * inline declarations of the same type * use scoped_guard() in rzt2h_icu_irq_set_type() to avoid keeping the guard across the irq_chip_set_type_parent() call * align struct irq_chip members initialization drivers/irqchip/Kconfig | 8 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-renesas-rzt2h.c | 283 ++++++++++++++++++++++ drivers/soc/renesas/Kconfig | 1 + include/linux/irqchip/irq-renesas-rzt2h.h | 23 ++ 5 files changed, 316 insertions(+) create mode 100644 drivers/irqchip/irq-renesas-rzt2h.c create mode 100644 include/linux/irqchip/irq-renesas-rzt2h.h diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index f334f49c9791..118d0c16e633 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -297,6 +297,14 @@ config RENESAS_RZG2L_IRQC Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Control= ler for external devices. =20 +config RENESAS_RZT2H_ICU + bool "Renesas RZ/{T2H,N2H} ICU support" if COMPILE_TEST + select GENERIC_IRQ_CHIP + select IRQ_DOMAIN_HIERARCHY + help + Enable support for the Renesas RZ/{T2H,N2H} Interrupt Controller + (ICU). + config RENESAS_RZV2H_ICU bool "Renesas RZ/V2H(P) ICU support" if COMPILE_TEST select GENERIC_IRQ_CHIP diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 6a229443efe0..26aa3b6ec99f 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -54,6 +54,7 @@ obj-$(CONFIG_RENESAS_INTC_IRQPIN) +=3D irq-renesas-intc-i= rqpin.o obj-$(CONFIG_RENESAS_IRQC) +=3D irq-renesas-irqc.o obj-$(CONFIG_RENESAS_RZA1_IRQC) +=3D irq-renesas-rza1.o obj-$(CONFIG_RENESAS_RZG2L_IRQC) +=3D irq-renesas-rzg2l.o +obj-$(CONFIG_RENESAS_RZT2H_ICU) +=3D irq-renesas-rzt2h.o obj-$(CONFIG_RENESAS_RZV2H_ICU) +=3D irq-renesas-rzv2h.o obj-$(CONFIG_VERSATILE_FPGA_IRQ) +=3D irq-versatile-fpga.o obj-$(CONFIG_ARCH_NSPIRE) +=3D irq-zevio.o diff --git a/drivers/irqchip/irq-renesas-rzt2h.c b/drivers/irqchip/irq-rene= sas-rzt2h.c new file mode 100644 index 000000000000..1b2fb1782982 --- /dev/null +++ b/drivers/irqchip/irq-renesas-rzt2h.c @@ -0,0 +1,283 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RZT2H_ICU_INTCPU_NS_START 0 +#define RZT2H_ICU_INTCPU_NS_COUNT 14 + +#define RZT2H_ICU_INTCPU_S_START (RZT2H_ICU_INTCPU_NS_START + \ + RZT2H_ICU_INTCPU_NS_COUNT) +#define RZT2H_ICU_INTCPU_S_COUNT 2 + +#define RZT2H_ICU_IRQ_NS_START (RZT2H_ICU_INTCPU_S_START + \ + RZT2H_ICU_INTCPU_S_COUNT) +#define RZT2H_ICU_IRQ_NS_COUNT 14 + +#define RZT2H_ICU_IRQ_S_START (RZT2H_ICU_IRQ_NS_START + \ + RZT2H_ICU_IRQ_NS_COUNT) +#define RZT2H_ICU_IRQ_S_COUNT 2 + +#define RZT2H_ICU_SEI_START (RZT2H_ICU_IRQ_S_START + \ + RZT2H_ICU_IRQ_S_COUNT) +#define RZT2H_ICU_SEI_COUNT 1 + +#define RZT2H_ICU_NUM_IRQ (RZT2H_ICU_INTCPU_NS_COUNT + \ + RZT2H_ICU_INTCPU_S_COUNT + \ + RZT2H_ICU_IRQ_NS_COUNT + \ + RZT2H_ICU_IRQ_S_COUNT + \ + RZT2H_ICU_SEI_COUNT) + +#define RZT2H_ICU_IRQ_IN_RANGE(n, type) \ + ((n) >=3D RZT2H_ICU_##type##_START && \ + (n) < RZT2H_ICU_##type##_START + RZT2H_ICU_##type##_COUNT) + +#define RZT2H_ICU_PORTNF_MD 0xc +#define RZT2H_ICU_PORTNF_MDi_MASK(i) (GENMASK(1, 0) << ((i) * 2)) +#define RZT2H_ICU_PORTNF_MDi_PREP(i, val) (FIELD_PREP(GENMASK(1, 0), val) = << ((i) * 2)) + +#define RZT2H_ICU_MD_LOW_LEVEL 0b00 +#define RZT2H_ICU_MD_FALLING_EDGE 0b01 +#define RZT2H_ICU_MD_RISING_EDGE 0b10 +#define RZT2H_ICU_MD_BOTH_EDGES 0b11 + +#define RZT2H_ICU_DMACn_RSSELi(n, i) (0x7d0 + 0x18 * (n) + 0x4 * (i)) +#define RZT2H_ICU_DMAC_REQ_SELx_MASK(x) (GENMASK(9, 0) << ((x) * 10)) +#define RZT2H_ICU_DMAC_REQ_SELx_PREP(x, val) (FIELD_PREP(GENMASK(9, 0), va= l) << ((x) * 10)) + +struct rzt2h_icu_priv { + void __iomem *base_ns; + void __iomem *base_s; + struct irq_fwspec fwspec[RZT2H_ICU_NUM_IRQ]; + raw_spinlock_t lock; +}; + +void rzt2h_icu_register_dma_req(struct platform_device *icu_dev, u8 dmac_i= ndex, u8 dmac_channel, + u16 req_no) +{ + struct rzt2h_icu_priv *priv =3D platform_get_drvdata(icu_dev); + u8 y, upper; + u32 val; + + y =3D dmac_channel / 3; + upper =3D dmac_channel % 3; + + guard(raw_spinlock_irqsave)(&priv->lock); + + val =3D readl(priv->base_ns + RZT2H_ICU_DMACn_RSSELi(dmac_index, y)); + val &=3D ~RZT2H_ICU_DMAC_REQ_SELx_MASK(upper); + val |=3D RZT2H_ICU_DMAC_REQ_SELx_PREP(upper, req_no); + writel(val, priv->base_ns + RZT2H_ICU_DMACn_RSSELi(dmac_index, y)); +} +EXPORT_SYMBOL_GPL(rzt2h_icu_register_dma_req); + +static inline struct rzt2h_icu_priv *irq_data_to_priv(struct irq_data *dat= a) +{ + return data->domain->host_data; +} + +static inline int rzt2h_icu_irq_to_offset(struct irq_data *d, void __iomem= **base, + unsigned int *offset) +{ + struct rzt2h_icu_priv *priv =3D irq_data_to_priv(d); + unsigned int hwirq =3D irqd_to_hwirq(d); + + /* + * Safety IRQs and SEI use a separate register space from the non-safety = IRQs. + * SEI interrupt number follows immediately after the safety IRQs. + */ + if (RZT2H_ICU_IRQ_IN_RANGE(hwirq, IRQ_NS)) { + *offset =3D hwirq - RZT2H_ICU_IRQ_NS_START; + *base =3D priv->base_ns; + } else if (RZT2H_ICU_IRQ_IN_RANGE(hwirq, IRQ_S) || + RZT2H_ICU_IRQ_IN_RANGE(hwirq, SEI)) { + *offset =3D hwirq - RZT2H_ICU_IRQ_S_START; + *base =3D priv->base_s; + } else { + return -EINVAL; + } + + return 0; +} + +static int rzt2h_icu_irq_set_type(struct irq_data *d, unsigned int type) +{ + struct rzt2h_icu_priv *priv =3D irq_data_to_priv(d); + unsigned int offset, parent_type; + void __iomem *base; + u32 val, md; + int ret; + + ret =3D rzt2h_icu_irq_to_offset(d, &base, &offset); + if (ret) + return ret; + + switch (type & IRQ_TYPE_SENSE_MASK) { + case IRQ_TYPE_LEVEL_LOW: + md =3D RZT2H_ICU_MD_LOW_LEVEL; + parent_type =3D IRQ_TYPE_LEVEL_HIGH; + break; + case IRQ_TYPE_EDGE_FALLING: + md =3D RZT2H_ICU_MD_FALLING_EDGE; + parent_type =3D IRQ_TYPE_EDGE_RISING; + break; + case IRQ_TYPE_EDGE_RISING: + md =3D RZT2H_ICU_MD_RISING_EDGE; + parent_type =3D IRQ_TYPE_EDGE_RISING; + break; + case IRQ_TYPE_EDGE_BOTH: + md =3D RZT2H_ICU_MD_BOTH_EDGES; + parent_type =3D IRQ_TYPE_EDGE_RISING; + break; + default: + return -EINVAL; + } + + scoped_guard(raw_spinlock, &priv->lock) { + val =3D readl_relaxed(base + RZT2H_ICU_PORTNF_MD); + val &=3D ~RZT2H_ICU_PORTNF_MDi_MASK(offset); + val |=3D RZT2H_ICU_PORTNF_MDi_PREP(offset, md); + writel_relaxed(val, base + RZT2H_ICU_PORTNF_MD); + } + + return irq_chip_set_type_parent(d, parent_type); +} + +static int rzt2h_icu_set_type(struct irq_data *d, unsigned int type) +{ + unsigned int hw_irq =3D irqd_to_hwirq(d); + + /* IRQn and SEI are selectable, others are edge-only. */ + if (RZT2H_ICU_IRQ_IN_RANGE(hw_irq, IRQ_NS) || + RZT2H_ICU_IRQ_IN_RANGE(hw_irq, IRQ_S) || + RZT2H_ICU_IRQ_IN_RANGE(hw_irq, SEI)) + return rzt2h_icu_irq_set_type(d, type); + + if ((type & IRQ_TYPE_SENSE_MASK) !=3D IRQ_TYPE_EDGE_RISING) + return -EINVAL; + + return irq_chip_set_type_parent(d, IRQ_TYPE_EDGE_RISING); +} + +static const struct irq_chip rzt2h_icu_chip =3D { + .name =3D "rzt2h-icu", + .irq_mask =3D irq_chip_mask_parent, + .irq_unmask =3D irq_chip_unmask_parent, + .irq_eoi =3D irq_chip_eoi_parent, + .irq_set_type =3D rzt2h_icu_set_type, + .irq_set_wake =3D irq_chip_set_wake_parent, + .irq_set_affinity =3D irq_chip_set_affinity_parent, + .irq_retrigger =3D irq_chip_retrigger_hierarchy, + .irq_get_irqchip_state =3D irq_chip_get_parent_state, + .irq_set_irqchip_state =3D irq_chip_set_parent_state, + .flags =3D IRQCHIP_MASK_ON_SUSPEND | + IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE, +}; + +static int rzt2h_icu_alloc(struct irq_domain *domain, unsigned int virq, u= nsigned int nr_irqs, + void *arg) +{ + struct rzt2h_icu_priv *priv =3D domain->host_data; + irq_hw_number_t hwirq; + unsigned int type; + int ret; + + ret =3D irq_domain_translate_twocell(domain, arg, &hwirq, &type); + if (ret) + return ret; + + ret =3D irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &rzt2h_icu_chi= p, NULL); + if (ret) + return ret; + + return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &priv->fwspec[= hwirq]); +} + +static const struct irq_domain_ops rzt2h_icu_domain_ops =3D { + .alloc =3D rzt2h_icu_alloc, + .free =3D irq_domain_free_irqs_common, + .translate =3D irq_domain_translate_twocell, +}; + +static int rzt2h_icu_parse_interrupts(struct rzt2h_icu_priv *priv, struct = device_node *np) +{ + struct of_phandle_args map; + unsigned int i; + int ret; + + for (i =3D 0; i < RZT2H_ICU_NUM_IRQ; i++) { + ret =3D of_irq_parse_one(np, i, &map); + if (ret) + return ret; + + of_phandle_args_to_fwspec(np, map.args, map.args_count, &priv->fwspec[i]= ); + } + + return 0; +} + +static int rzt2h_icu_init(struct platform_device *pdev, struct device_node= *parent) +{ + struct irq_domain *irq_domain, *parent_domain; + struct device_node *node =3D pdev->dev.of_node; + struct device *dev =3D &pdev->dev; + struct rzt2h_icu_priv *priv; + int ret; + + parent_domain =3D irq_find_host(parent); + if (!parent_domain) + return dev_err_probe(dev, -ENODEV, "cannot find parent domain\n"); + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + platform_set_drvdata(pdev, priv); + + priv->base_ns =3D devm_of_iomap(dev, dev->of_node, 0, NULL); + if (IS_ERR(priv->base_ns)) + return PTR_ERR(priv->base_ns); + + priv->base_s =3D devm_of_iomap(dev, dev->of_node, 1, NULL); + if (IS_ERR(priv->base_s)) + return PTR_ERR(priv->base_s); + + ret =3D rzt2h_icu_parse_interrupts(priv, node); + if (ret) + return dev_err_probe(dev, ret, "cannot parse interrupts: %d\n", ret); + + ret =3D devm_pm_runtime_enable(dev); + if (ret) + return dev_err_probe(dev, ret, "devm_pm_runtime_enable failed: %d\n", re= t); + + ret =3D pm_runtime_resume_and_get(dev); + if (ret) + return dev_err_probe(dev, ret, "pm_runtime_resume_and_get failed: %d\n",= ret); + + raw_spin_lock_init(&priv->lock); + + irq_domain =3D irq_domain_create_hierarchy(parent_domain, 0, RZT2H_ICU_NU= M_IRQ, + dev_fwnode(dev), &rzt2h_icu_domain_ops, priv); + if (!irq_domain) { + pm_runtime_put(dev); + return -ENOMEM; + } + + return 0; +} + +IRQCHIP_PLATFORM_DRIVER_BEGIN(rzt2h_icu) +IRQCHIP_MATCH("renesas,r9a09g077-icu", rzt2h_icu_init) +IRQCHIP_PLATFORM_DRIVER_END(rzt2h_icu) +MODULE_AUTHOR("Cosmin Tanislav "); +MODULE_DESCRIPTION("Renesas RZ/T2H ICU Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 340a1ff7e92b..198baf890b14 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -423,6 +423,7 @@ config ARCH_R9A09G057 config ARCH_R9A09G077 bool "ARM64 Platform support for R9A09G077 (RZ/T2H)" default y if ARCH_RENESAS + select RENESAS_RZT2H_ICU help This enables support for the Renesas RZ/T2H SoC variants. =20 diff --git a/include/linux/irqchip/irq-renesas-rzt2h.h b/include/linux/irqc= hip/irq-renesas-rzt2h.h new file mode 100644 index 000000000000..853fd5ee0b22 --- /dev/null +++ b/include/linux/irqchip/irq-renesas-rzt2h.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Renesas RZ/T2H Interrupt Control Unit (ICU) + * + * Copyright (C) 2025 Renesas Electronics Corporation. + */ + +#ifndef __LINUX_IRQ_RENESAS_RZT2H +#define __LINUX_IRQ_RENESAS_RZT2H + +#include + +#define RZT2H_ICU_DMAC_REQ_NO_DEFAULT 0x3ff + +#ifdef CONFIG_RENESAS_RZT2H_ICU +void rzt2h_icu_register_dma_req(struct platform_device *icu_dev, u8 dmac_i= ndex, u8 dmac_channel, + u16 req_no); +#else +static inline void rzt2h_icu_register_dma_req(struct platform_device *icu_= dev, u8 dmac_index, + u8 dmac_channel, u16 req_no) { } +#endif + +#endif /* __LINUX_IRQ_RENESAS_RZT2H */ --=20 2.52.0 From nobody Mon Dec 1 21:31:53 2025 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id AE9C826158B; Mon, 1 Dec 2025 11:30:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588635; cv=none; b=i7ePTzRHjdM4abnL35G3HfAiuUH5DIsW8VPCpEwnpqzVMY3+L3jdn2VQ5sBaiItAy4+Sq3ZSgrPmQzvRXoieg1Twk3PxGmto/sHfFpA7tFXNMCObhXAr4kFkCl/kJzP0TxBd0nrsstcD56vNzMxPCBRHg1amPAgDqWN9g8GVouE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588635; c=relaxed/simple; bh=BYr/gDvVEgFo/tdZiwLHAusQdunhJXHXgkkC0vsEYCM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uXe6ax6mKkFxUutkcVCXyPbToV7QmSAOIo8Gc0CgwWAAzhYol2/KnEl3yfCKfzsxha8jE3bNdx8acbWTAOmevDP6OGgJZwn8pvjwKnpf0I5CF3HV29sihu77Ud8kwWs7pgIZsUlGaT6Smb/zE9MJjjjD1lgzBe4i1kXv9a6XZBw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: gCLAaIslSDeSPpXraHOLjA== X-CSE-MsgGUID: GyCMw0pYS36Qyi/gB3XVcw== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 01 Dec 2025 20:30:33 +0900 Received: from demon-pc.localdomain (unknown [10.226.93.83]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 4982741F1B93; Mon, 1 Dec 2025 20:30:30 +0900 (JST) From: Cosmin Tanislav To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Cosmin Tanislav Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH v2 3/4] arm64: dts: renesas: r9a09g077: add ICU support Date: Mon, 1 Dec 2025 13:29:32 +0200 Message-ID: <20251201112933.488801-4-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251201112933.488801-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20251201112933.488801-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Renesas RZ/T2H (R9A09G077) SoC has an Interrupt Controller (ICU) block that routes external interrupts to the GIC's SPIs, with the ability of level-translation, and can also produce software and aggregate error interrupts. Add support for it. Signed-off-by: Cosmin Tanislav --- V2: * no changes arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 73 ++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g077.dtsi index f80c6d603eea..0af41287e6a8 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -862,6 +862,79 @@ cpg: clock-controller@80280000 { #power-domain-cells =3D <0>; }; =20 + icu: interrupt-controller@802a0000 { + compatible =3D "renesas,r9a09g077-icu"; + reg =3D <0 0x802a0000 0 0x10000>, + <0 0x812a0000 0 0x50>; + #interrupt-cells =3D <2>; + #address-cells =3D <0>; + interrupt-controller; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "intcpu0", "intcpu1", "intcpu2", + "intcpu3", "intcpu4", "intcpu5", + "intcpu6", "intcpu7", "intcpu8", + "intcpu9", "intcpu10", "intcpu11", + "intcpu12", "intcpu13", "intcpu14", + "intcpu15", + "irq0", "irq1", "irq2", "irq3", + "irq4", "irq5", "irq6", "irq7", + "irq8", "irq9", "irq10", "irq11", + "irq12", "irq13", "irq14", "irq15", + "sei", + "ca55-err0", "ca55-err1", + "cr520-err0", "cr520-err1", + "cr521-err0", "cr521-err1", + "peri-err0", "peri-err1", + "dsmif-err0", "dsmif-err1", + "encif-err0", "encif-err1"; + clocks =3D <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; + power-domains =3D <&cpg>; + }; + pinctrl: pinctrl@802c0000 { compatible =3D "renesas,r9a09g077-pinctrl"; reg =3D <0 0x802c0000 0 0x10000>, --=20 2.52.0 From nobody Mon Dec 1 21:31:53 2025 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BEC3D25A2B4; Mon, 1 Dec 2025 11:30:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588640; cv=none; b=SNhG5aQAMFwCy+axkpbL54DUHnrYNvvFHGyvGUMas9VYGGKp1P0DQWqbhqLhgH7R8cXNVct9ZPQnJwuZqnc6xV1Hj17QnljbQxPpIhSmnmMXVVSj0IfePMykYlWuIr8YKMln7MY7hJ11DU4KK4vTtWedTSlg5exgPqLNAl7PfcA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588640; c=relaxed/simple; bh=X/Mx2w+IbAQkSLaka70txr2uyrIrdWgpWbgD08a2cCU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=OQ6epMG/ZPG3xk6g8Xh6xQ0L3sq9cqMsQ5EJpAuGYosKvhpBs29aVpa1jPHYbG2CRl3M85TSQ/ew+JI5LrqwQs/fDArwF8gJ/IAdHjtmO6SkTAdImsnompsfHMMNp3fry9hcYqcyaTsKSXPiGTqnQjo3DXMNTgWDSw5SwlxORG4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: j0LTLnaRTfikQ7Q9lvO5vw== X-CSE-MsgGUID: uPPw9+fITcGiSOmGVUVqyA== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 01 Dec 2025 20:30:37 +0900 Received: from demon-pc.localdomain (unknown [10.226.93.83]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 87E7341F1B9F; Mon, 1 Dec 2025 20:30:34 +0900 (JST) From: Cosmin Tanislav To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Cosmin Tanislav Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH v2 4/4] arm64: dts: renesas: r9a09g087: add ICU support Date: Mon, 1 Dec 2025 13:29:33 +0200 Message-ID: <20251201112933.488801-5-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251201112933.488801-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20251201112933.488801-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Renesas RZ/N2H (R9A09G087) SoC has an Interrupt Controller (ICU) block that routes external interrupts to the GIC's SPIs, with the ability of level-translation, and can also produce software and aggregate error interrupts. Add support for it. Signed-off-by: Cosmin Tanislav --- V2: * no changes arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 73 ++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g087.dtsi index f9f49bd3e8b0..6b5693e5c1f9 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -865,6 +865,79 @@ cpg: clock-controller@80280000 { #power-domain-cells =3D <0>; }; =20 + icu: interrupt-controller@802a0000 { + compatible =3D "renesas,r9a09g087-icu", "renesas,r9a09g077-icu"; + reg =3D <0 0x802a0000 0 0x10000>, + <0 0x812a0000 0 0x50>; + #interrupt-cells =3D <2>; + #address-cells =3D <0>; + interrupt-controller; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "intcpu0", "intcpu1", "intcpu2", + "intcpu3", "intcpu4", "intcpu5", + "intcpu6", "intcpu7", "intcpu8", + "intcpu9", "intcpu10", "intcpu11", + "intcpu12", "intcpu13", "intcpu14", + "intcpu15", + "irq0", "irq1", "irq2", "irq3", + "irq4", "irq5", "irq6", "irq7", + "irq8", "irq9", "irq10", "irq11", + "irq12", "irq13", "irq14", "irq15", + "sei", + "ca55-err0", "ca55-err1", + "cr520-err0", "cr520-err1", + "cr521-err0", "cr521-err1", + "peri-err0", "peri-err1", + "dsmif-err0", "dsmif-err1", + "encif-err0", "encif-err1"; + clocks =3D <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; + power-domains =3D <&cpg>; + }; + pinctrl: pinctrl@802c0000 { compatible =3D "renesas,r9a09g087-pinctrl"; reg =3D <0 0x802c0000 0 0x10000>, --=20 2.52.0