From nobody Mon Dec 1 21:33:21 2025 Received: from mail-m155101.qiye.163.com (mail-m155101.qiye.163.com [101.71.155.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B9DE2E4279; Mon, 1 Dec 2025 10:01:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=101.71.155.101 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764583284; cv=none; b=hlz3ZMRiWuYM+2AUJ26zYJr6XSzT+V6+bakEu9ckZkYP81+guJuULAMljWjoWbXCVmwSv8OTWJ6/hzXl7QhPbsq8bWmZkjksJ1ecIUeJdHC8LS4s9FxwKfOM9ltuM/noUlSIx/YhlthmuBkd1OSEhybPgGYAWHs5YQ94UsUz5Mw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764583284; c=relaxed/simple; bh=3ithkSbCBMU6iwVOGCExIuy5tg+GbzuIHt/59Me8q/M=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=CAsOdy+uXcqa8DRsVlSJIzvYuegQeuueeMqmcCagGHoXPYS6Oil3YsNxNO8qOSUjGhpMI1ihokdp9A8a24Q0jWxD/uqv6Kzaht1vdcALc7EWdehNioToEpLPlj9Wi7ej4GX4o2goaBRm11Gj7ExYIGufhz1fngg4aq/3Yu9A04g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=jmu.edu.cn; spf=pass smtp.mailfrom=jmu.edu.cn; arc=none smtp.client-ip=101.71.155.101 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=jmu.edu.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=jmu.edu.cn Received: from localhost.localdomain (unknown [119.122.215.79]) by smtp.qiye.163.com (Hmail) with ESMTP id 2b846f23a; Mon, 1 Dec 2025 18:01:12 +0800 (GMT+08:00) From: Chukun Pan To: Heiko Stuebner Cc: Rob Herring , Chukun Pan , Conor Dooley , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 1/4] dt-bindings: arm: rockchip: Add HINLINK H28K Date: Mon, 1 Dec 2025 18:00:05 +0800 Message-Id: <20251201100008.206524-2-amadeus@jmu.edu.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20251201100008.206524-1-amadeus@jmu.edu.cn> References: <20251201100008.206524-1-amadeus@jmu.edu.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0a9ad95bf13203a2kunm919d19c1367a07 X-HM-MType: 10 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVkaSU9OVkwfQx0YQ0gaQkMYHlYeHw5VEwETFhoSFy QUDg9ZV1kYEgtZQVlKSkJVSklJVUlKTlVMQllXWRYaDxIVHRRZQVlPS0hVSktISk5MTlVKS0tVSk JLS1kG Content-Type: text/plain; charset="utf-8" The HINLINK H28K is a dual-gigabit SBC based on the RK3528 SoC. Add devicetree binding documentation for it. Signed-off-by: Chukun Pan --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index d496421dbd87..8d6e2b28e51a 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -718,6 +718,11 @@ properties: - const: hardkernel,odroid-m2 - const: rockchip,rk3588s =20 + - description: HINLINK H28K + items: + - const: hinlink,h28k + - const: rockchip,rk3528 + - description: HINLINK H66K / H68K items: - enum: --=20 2.25.1 From nobody Mon Dec 1 21:33:21 2025 Received: from mail-m49198.qiye.163.com (mail-m49198.qiye.163.com [45.254.49.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 201022FCC17; Mon, 1 Dec 2025 10:06:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.254.49.198 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764583590; cv=none; b=chri/KNGOJrfUEp2vKCz/cCiEflPWZQ9+aVa8uLyPSfS/C73etWHyLwe0goF0G7YPyhNGx31lOhIbj+E8y3mHLndHIPB5yL4i1qxh2nXrOHUihqoIXpfETCSzdrrFfYv26jD5+ZfFx+/TgvVM9VVSfbvEoDPNLYFGRXD61UsIS0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764583590; c=relaxed/simple; bh=HOJKT3e2KNXjQR6nBmmivoYJ0BOD+0ELru24MOTBXtw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=thV2PMKLZSmuIb0cSuCoc7AmbNrgDo3WUI/rFSzPxzWnG45Xvr4cFU2R/8POG95u4lgmCx5yRvQ9K0yGjKsf6vk6X3i8bInOpF2YDQHWM0uBnEZxLPaRVbqzmZTQU+2vOeRJCd10SYMnwtu0UZYvTPMxJlB486PR5muLQlahMyk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=jmu.edu.cn; spf=pass smtp.mailfrom=jmu.edu.cn; arc=none smtp.client-ip=45.254.49.198 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=jmu.edu.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=jmu.edu.cn Received: from localhost.localdomain (unknown [119.122.215.79]) by smtp.qiye.163.com (Hmail) with ESMTP id 2b846f242; Mon, 1 Dec 2025 18:01:16 +0800 (GMT+08:00) From: Chukun Pan To: Heiko Stuebner Cc: Rob Herring , Chukun Pan , Conor Dooley , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 2/4] arm64: dts: rockchip: Add HINLINK H28K Date: Mon, 1 Dec 2025 18:00:06 +0800 Message-Id: <20251201100008.206524-3-amadeus@jmu.edu.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20251201100008.206524-1-amadeus@jmu.edu.cn> References: <20251201100008.206524-1-amadeus@jmu.edu.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0a9ad95bff3803a2kunm919d19c1367a29 X-HM-MType: 10 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVkaSUxKVklOQkxIS0hIQkMfHVYeHw5VEwETFhoSFy QUDg9ZV1kYEgtZQVlKSkJVSklJVUlKTlVMQllXWRYaDxIVHRRZQVlPS0hVSktISk5MTlVKS0tVSk JLS1kG Content-Type: text/plain; charset="utf-8" The HINLINK H28K is a development board with the Rockchip RK3528 SoC. It has the following features: - 1x USB 2.0 - 8/32GB eMMC - 1/2/4GB LPDDR4 - MicroSD card slot - 1x 1GbE RTL8111H Ethernet - 1x 1GbE RTL8211F Ethernet Signed-off-by: Chukun Pan --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3528-hinlink-h28k.dts | 301 ++++++++++++++++++ 2 files changed, 302 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3528-hinlink-h28k.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index dbdda9783e93..8ccf72c2e31e 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -90,6 +90,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3399-sapphire.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3399-sapphire-excavator.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3399pro-rock-pi-n10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3528-armsom-sige1.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3528-hinlink-h28k.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3528-nanopi-zero2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3528-radxa-e20c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3528-rock-2a.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3528-hinlink-h28k.dts b/arch/ar= m64/boot/dts/rockchip/rk3528-hinlink-h28k.dts new file mode 100644 index 000000000000..4685db24a560 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3528-hinlink-h28k.dts @@ -0,0 +1,301 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include "rk3528.dtsi" + +/ { + model =3D "HINLINK H28K"; + compatible =3D "hinlink,h28k", "rockchip,rk3528"; + + aliases { + ethernet0 =3D &gmac1; + mmc0 =3D &sdhci; + mmc1 =3D &sdmmc; + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:1500000n8"; + }; + + keys { + compatible =3D "adc-keys"; + io-channels =3D <&saradc 0>; + io-channel-names =3D "buttons"; + keyup-threshold-microvolt =3D <1800000>; + poll-interval =3D <100>; + + button-boot { + label =3D "BOOT"; + linux,code =3D ; + press-threshold-microvolt =3D <0>; + }; + }; + + leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&lan_led>, <&wan_led>, <&work_led>; + + led-0 { + color =3D ; + function =3D LED_FUNCTION_LAN; + gpios =3D <&gpio4 RK_PC1 GPIO_ACTIVE_LOW>; + linux,default-trigger =3D "netdev"; + }; + + led-1 { + color =3D ; + function =3D LED_FUNCTION_WAN; + gpios =3D <&gpio4 RK_PC0 GPIO_ACTIVE_LOW>; + linux,default-trigger =3D "netdev"; + }; + + led-2 { + color =3D ; + function =3D LED_FUNCTION_STATUS; + gpios =3D <&gpio4 RK_PB7 GPIO_ACTIVE_LOW>; + linux,default-trigger =3D "default-on"; + }; + }; + + vdd_0v9: regulator-0v9-vdd { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + vin-supply =3D <&vcc5v0_sys>; + }; + + vcc_ddr: regulator-1v1-vcc-ddr { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + vin-supply =3D <&vcc5v0_sys>; + }; + + vcc_1v8: regulator-1v8-vcc { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&vcc_3v3>; + }; + + vcc_3v3: regulator-3v3-vcc { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc5v0_sys>; + }; + + vcc3v3_sd: regulator-3v3-vcc-sd { + compatible =3D "regulator-fixed"; + gpios =3D <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdmmc_pwren_l>; + regulator-name =3D "vcc3v3_sd"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc_3v3>; + }; + + vcc5v0_sys: regulator-5v0-vcc-sys { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + }; + + vccio_sd: regulator-vccio-sd { + compatible =3D "regulator-gpio"; + gpios =3D <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdmmc_vol_ctrl_h>; + regulator-name =3D "vccio_sd"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + states =3D <1800000 0x0>, <3300000 0x1>; + vin-supply =3D <&vcc5v0_sys>; + }; + + vdd_arm: regulator-vdd-arm { + compatible =3D "pwm-regulator"; + pwms =3D <&pwm1 0 5000 PWM_POLARITY_INVERTED>; + pwm-supply =3D <&vcc5v0_sys>; + regulator-name =3D "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <746000>; + regulator-max-microvolt =3D <1201000>; + regulator-settling-time-up-us =3D <250>; + }; + + vdd_logic: regulator-vdd-logic { + compatible =3D "pwm-regulator"; + pwms =3D <&pwm2 0 5000 PWM_POLARITY_INVERTED>; + pwm-supply =3D <&vcc5v0_sys>; + regulator-name =3D "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <705000>; + regulator-max-microvolt =3D <1006000>; + regulator-settling-time-up-us =3D <250>; + }; +}; + +&combphy { + status =3D "okay"; +}; + +&cpu0 { + cpu-supply =3D <&vdd_arm>; +}; + +&cpu1 { + cpu-supply =3D <&vdd_arm>; +}; + +&cpu2 { + cpu-supply =3D <&vdd_arm>; +}; + +&cpu3 { + cpu-supply =3D <&vdd_arm>; +}; + +&gmac1 { + clock_in_out =3D "output"; + phy-handle =3D <&rgmii_phy>; + phy-mode =3D "rgmii-id"; + phy-supply =3D <&vcc_3v3>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rgmii_miim>, + <&rgmii_tx_bus2>, + <&rgmii_rx_bus2>, + <&rgmii_rgmii_clk>, + <&rgmii_rgmii_bus>; + status =3D "okay"; +}; + +&gpu { + mali-supply =3D <&vdd_logic>; + status =3D "okay"; +}; + +&mdio1 { + rgmii_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0x1>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gmac1_rstn_l>; + reset-assert-us =3D <20000>; + reset-deassert-us =3D <100000>; + reset-gpios =3D <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; + }; +}; + +&pcie { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rtl8111hs_isolateb_l>; + reset-gpios =3D <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc_3v3>; + status =3D "okay"; +}; + +&pinctrl { + gmac { + gmac1_rstn_l: gmac1-rstn-l { + rockchip,pins =3D <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + lan_led: lan-led { + rockchip,pins =3D <4 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wan_led: wan-led { + rockchip,pins =3D <4 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + work_led: work-led { + rockchip,pins =3D <4 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + rtl8111hs_isolateb_l: rtl8111hs-isolateb-l { + rockchip,pins =3D <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + sdmmc_pwren_l: sdmmc-pwren-l { + rockchip,pins =3D <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + sdmmc_vol_ctrl_h: sdmmc-vol-ctrl-h { + rockchip,pins =3D <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm1m0_pins>; + status =3D "okay"; +}; + +&pwm2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm2m0_pins>; + status =3D "okay"; +}; + +&saradc { + vref-supply =3D <&vcc_1v8>; + status =3D "okay"; +}; + +&sdhci { + bus-width =3D <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + non-removable; + vmmc-supply =3D <&vcc_3v3>; + vqmmc-supply =3D <&vcc_1v8>; + status =3D "okay"; +}; + +&sdmmc { + bus-width =3D <4>; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply =3D <&vcc3v3_sd>; + vqmmc-supply =3D <&vccio_sd>; + status =3D "okay"; +}; + +&uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0m0_xfer>; + status =3D "okay"; +}; --=20 2.25.1 From nobody Mon Dec 1 21:33:21 2025 Received: from mail-m155101.qiye.163.com (mail-m155101.qiye.163.com [101.71.155.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 836B921CC4F; Mon, 1 Dec 2025 10:01:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=101.71.155.101 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764583285; cv=none; b=dWayyEPC9mAJe888mHhBoEC/NlqbCKysFBuVZPYKYt0BigOD70dP/g+Lm/78DjNctcyEafOqHvSPhTymaIM3fbSH0HAyHoCYANZiDRn/Qh1rPtcezpPoqSBibvebh8hfBJ1ij/LuPphEVuHPf5VjLwdu0h/zhBIKLkb5cqbJFx8= ARC-Message-Signature: i=1; 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charset="utf-8" The MangoPi M28K is a dual-gigabit SBC developed by Widora based on the RK3528 SoC. Add devicetree binding documentation for it. Signed-off-by: Chukun Pan --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index 8d6e2b28e51a..8fef370b637c 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -1269,6 +1269,11 @@ properties: - const: turing,rk1 - const: rockchip,rk3588 =20 + - description: MangoPi M28K + items: + - const: widora,mangopi-m28k + - const: rockchip,rk3528 + - description: WolfVision PF5 mainboard items: - const: wolfvision,rk3568-pf5 --=20 2.25.1 From nobody Mon Dec 1 21:33:21 2025 Received: from mail-m155101.qiye.163.com (mail-m155101.qiye.163.com [101.71.155.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C4C13019BB; Mon, 1 Dec 2025 10:01:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=101.71.155.101 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764583287; cv=none; b=mC90RDg15cOgqtWrMIN4QP4BDlEWUwCi7gTOQkizFf767axRastwnunCvGRZPZJPCRQ49vBcV1KU5IlgN73tPqn2PsHwmRtUtHHUODpSIR0BmL6wEOYKd6UFXUZvPmttvVxP5M0OTUFvutnR5/1EFH3ajLmVbJ1snySI8gZP0iU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764583287; c=relaxed/simple; bh=RQugmeTQ+g9grEPv8qTFE7DuWndMxheUfkA2RGWJJOc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ZQci/Qtv6W4rptxYPfe42k5xv5wd2gl96EQA9BE8rEJHoKVF7hSjhwe+8cfQS0hvx+QrKcX+t4OxeS6IMYEWn6kDTyvBdDMgZ3hoULzGprV8Un3tdhpogX1a6jcFmgPjKkRR59rApiUVuJanJv+MblvAIkHBqNR2x9+bRhrlIXI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=jmu.edu.cn; spf=pass smtp.mailfrom=jmu.edu.cn; arc=none smtp.client-ip=101.71.155.101 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=jmu.edu.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=jmu.edu.cn Received: from localhost.localdomain (unknown [119.122.215.79]) by smtp.qiye.163.com (Hmail) with ESMTP id 2b846f24b; Mon, 1 Dec 2025 18:01:21 +0800 (GMT+08:00) From: Chukun Pan To: Heiko Stuebner Cc: Rob Herring , Chukun Pan , Conor Dooley , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 4/4] arm64: dts: rockchip: Add MangoPi M28K Date: Mon, 1 Dec 2025 18:00:08 +0800 Message-Id: <20251201100008.206524-5-amadeus@jmu.edu.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20251201100008.206524-1-amadeus@jmu.edu.cn> References: <20251201100008.206524-1-amadeus@jmu.edu.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0a9ad95c11a103a2kunm919d19c1367a43 X-HM-MType: 10 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVlCHkxOVhhKSR0aQ0keGUhKGVYeHw5VEwETFhoSFy QUDg9ZV1kYEgtZQVlKSkJVSklJVUlKTlVMQllXWRYaDxIVHRRZQVlPS0hVSktJQkNDTFVKS0tVS1 kG Content-Type: text/plain; charset="utf-8" The MangoPi M28K is a development board with the Rockchip RK3528 SoC. It has the following features: - 2x USB 2.0 - 1x mini-HDMI - 1/2/4GB LPDDR4 - AIC8800 WiFi/BT - MicroSD card slot - Optional 16/32GB eMMC - 1x 1GbE RTL8111H Ethernet - 1x 1GbE RTL8211F Ethernet Signed-off-by: Chukun Pan --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3528-mangopi-m28k.dts | 381 ++++++++++++++++++ 2 files changed, 382 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3528-mangopi-m28k.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index 8ccf72c2e31e..d666ef62f5f4 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -91,6 +91,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3399-sapphire-excavato= r.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3399pro-rock-pi-n10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3528-armsom-sige1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3528-hinlink-h28k.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3528-mangopi-m28k.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3528-nanopi-zero2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3528-radxa-e20c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3528-rock-2a.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3528-mangopi-m28k.dts b/arch/ar= m64/boot/dts/rockchip/rk3528-mangopi-m28k.dts new file mode 100644 index 000000000000..e99a83553910 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3528-mangopi-m28k.dts @@ -0,0 +1,381 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include "rk3528.dtsi" + +/ { + model =3D "MangoPi M28K"; + compatible =3D "widora,mangopi-m28k", "rockchip,rk3528"; + + aliases { + ethernet0 =3D &gmac1; + i2c6 =3D &i2c6; + mmc0 =3D &sdhci; + mmc1 =3D &sdmmc; + mmc2 =3D &sdio0; + serial0 =3D &uart0; + serial2 =3D &uart2; + serial3 =3D &uart3; + }; + + chosen { + stdout-path =3D "serial0:1500000n8"; + }; + + ir-receiver { + compatible =3D "gpio-ir-receiver"; + gpios =3D <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm3_m0_ir_rx>; + }; + + keys-0 { + compatible =3D "adc-keys"; + io-channels =3D <&saradc 0>; + io-channel-names =3D "buttons"; + keyup-threshold-microvolt =3D <1800000>; + poll-interval =3D <100>; + + button-boot { + label =3D "BOOT"; + linux,code =3D ; + press-threshold-microvolt =3D <0>; + }; + }; + + keys-1 { + compatible =3D "adc-keys"; + io-channels =3D <&saradc 1>; + io-channel-names =3D "buttons"; + keyup-threshold-microvolt =3D <1800000>; + poll-interval =3D <100>; + + button-recover { + label =3D "RECOVER"; + linux,code =3D ; + press-threshold-microvolt =3D <0>; + }; + }; + + leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&lan_led>, <&wan_led>, <&work_led>; + + led-0 { + color =3D ; + function =3D LED_FUNCTION_LAN; + gpios =3D <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>; + linux,default-trigger =3D "netdev"; + }; + + led-1 { + color =3D ; + function =3D LED_FUNCTION_WAN; + gpios =3D <&gpio4 RK_PC0 GPIO_ACTIVE_LOW>; + linux,default-trigger =3D "netdev"; + }; + + led-2 { + color =3D ; + function =3D LED_FUNCTION_STATUS; + gpios =3D <&gpio4 RK_PB7 GPIO_ACTIVE_LOW>; + linux,default-trigger =3D "default-on"; + }; + }; + + vdd_0v9: regulator-0v9-vdd { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + vin-supply =3D <&vcc_sys>; + }; + + vcc_ddr: regulator-1v1-vcc-ddr { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + vin-supply =3D <&vcc_sys>; + }; + + vcc_1v8: regulator-1v8-vcc { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&vcc_3v3>; + }; + + vcc_3v3: regulator-3v3-vcc { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc_sys>; + }; + + vcc3v3_sd: regulator-3v3-vcc-sd { + compatible =3D "regulator-fixed"; + gpios =3D <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdmmc_pwren_l>; + regulator-name =3D "vcc3v3_sd"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc_3v3>; + }; + + vcc_sys: regulator-5v0-vcc-sys { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + }; + + vccio_sd: regulator-vccio-sd { + compatible =3D "regulator-gpio"; + gpios =3D <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdmmc_vol_ctrl_h>; + regulator-name =3D "vccio_sd"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + states =3D <1800000 0x0>, <3300000 0x1>; + vin-supply =3D <&vcc_sys>; + }; + + vdd_arm: regulator-vdd-arm { + compatible =3D "pwm-regulator"; + pwms =3D <&pwm1 0 5000 PWM_POLARITY_INVERTED>; + pwm-supply =3D <&vcc_sys>; + regulator-name =3D "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <746000>; + regulator-max-microvolt =3D <1201000>; + regulator-settling-time-up-us =3D <250>; + }; + + vdd_logic: regulator-vdd-logic { + compatible =3D "pwm-regulator"; + pwms =3D <&pwm2 0 5000 PWM_POLARITY_INVERTED>; + pwm-supply =3D <&vcc_sys>; + regulator-name =3D "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <705000>; + regulator-max-microvolt =3D <1006000>; + regulator-settling-time-up-us =3D <250>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wifi_reg_on_h>; + post-power-on-delay-ms =3D <100>; + power-off-delay-us =3D <5000000>; + reset-gpios =3D <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>; + }; +}; + +&combphy { + status =3D "okay"; +}; + +&cpu0 { + cpu-supply =3D <&vdd_arm>; +}; + +&cpu1 { + cpu-supply =3D <&vdd_arm>; +}; + +&cpu2 { + cpu-supply =3D <&vdd_arm>; +}; + +&cpu3 { + cpu-supply =3D <&vdd_arm>; +}; + +&gmac1 { + clock_in_out =3D "output"; + phy-handle =3D <&rgmii_phy>; + phy-mode =3D "rgmii-id"; + phy-supply =3D <&vcc_3v3>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rgmii_miim>, + <&rgmii_tx_bus2>, + <&rgmii_rx_bus2>, + <&rgmii_rgmii_clk>, + <&rgmii_rgmii_bus>; + status =3D "okay"; +}; + +&gpu { + mali-supply =3D <&vdd_logic>; + status =3D "okay"; +}; + +&i2c6 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c6m0_xfer>; + status =3D "okay"; +}; + +&mdio1 { + rgmii_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0x1>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gmac1_rstn_l>; + reset-assert-us =3D <20000>; + reset-deassert-us =3D <100000>; + reset-gpios =3D <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; + }; +}; + +&pcie { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rtl8111hs_isolateb_l>; + reset-gpios =3D <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc_3v3>; + status =3D "okay"; +}; + +&pinctrl { + gmac { + gmac1_rstn_l: gmac1-rstn-l { + rockchip,pins =3D <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + ir { + pwm3_m0_ir_rx: pwm3-m0-ir-rx { + rockchip,pins =3D <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + lan_led: lan-led { + rockchip,pins =3D <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wan_led: wan-led { + rockchip,pins =3D <4 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + work_led: work-led { + rockchip,pins =3D <4 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + rtl8111hs_isolateb_l: rtl8111hs-isolateb-l { + rockchip,pins =3D <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + sdmmc_pwren_l: sdmmc-pwren-l { + rockchip,pins =3D <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + sdmmc_vol_ctrl_h: sdmmc-vol-ctrl-h { + rockchip,pins =3D <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_reg_on_h: wifi-reg-on-h { + rockchip,pins =3D <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_wake_host_h: wifi-wake-host-h { + rockchip,pins =3D <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pwm1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm1m0_pins>; + status =3D "okay"; +}; + +&pwm2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm2m0_pins>; + status =3D "okay"; +}; + +&saradc { + vref-supply =3D <&vcc_1v8>; + status =3D "okay"; +}; + +&sdhci { + bus-width =3D <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + non-removable; + vmmc-supply =3D <&vcc_3v3>; + vqmmc-supply =3D <&vcc_1v8>; + status =3D "okay"; +}; + +&sdio0 { + bus-width =3D <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq =3D <&sdio_pwrseq>; + non-removable; + sd-uhs-sdr104; + status =3D "okay"; +}; + +&sdmmc { + bus-width =3D <4>; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply =3D <&vcc3v3_sd>; + vqmmc-supply =3D <&vccio_sd>; + status =3D "okay"; +}; + +&uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0m0_xfer>; + status =3D "okay"; +}; + +&uart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart2m1_ctsn>, <&uart2m1_rtsn>, <&uart2m1_xfer>; + uart-has-rtscts; + status =3D "okay"; +}; + +&uart3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart3m0_xfer>; + status =3D "disabled"; +}; --=20 2.25.1