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([2001:861:3201:3d10:4ab6:6efe:9b65:a6af]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42e1ca1a4bbsm24186087f8f.21.2025.12.01.00.41.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Dec 2025 00:41:44 -0800 (PST) From: Gary Bisson To: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Gary Bisson , robh@kernel.org, krzk+dt@kernel.org Subject: [PATCH 1/5] dt-bindings: vendor-prefixes: Add Ezurio LLC Date: Mon, 1 Dec 2025 09:41:36 +0100 Message-ID: <20251201084140.376058-2-bisson.gary@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251201084140.376058-1-bisson.gary@gmail.com> References: <20251201084140.376058-1-bisson.gary@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Ezurio is the new name of Laird Connectivity after it acquired Boundary Devices. Signed-off-by: Gary Bisson Acked-by: Krzysztof Kozlowski --- Cc: robh@kernel.org Cc: krzk+dt@kernel.org --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index f1d1882009ba..e76e6c5be726 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -547,6 +547,8 @@ patternProperties: description: Exegin Technologies Limited "^ezchip,.*": description: EZchip Semiconductor + "^ezurio,.*": + description: Ezurio LLC "^facebook,.*": description: Facebook "^fairchild,.*": --=20 2.43.0 From nobody Mon Dec 1 21:31:21 2025 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B6B8F2E03EC for ; Mon, 1 Dec 2025 08:41:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764578509; cv=none; b=uBAYuTPQkcEhZunCsKKF3yx/Gl9BOkk1P6dKyS5pdvZpuXVz+o60pdAgUZOnp6LvoID+i1niDMLYhl7A1xwniikzUzp8C6EZ5EJnMSp+qkcGC+hF7ybfCJ4xD3t/TTM/LkF2TeuNyJlS4C4lf1etQzNELf2S+AKX1zVzCde/mTY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764578509; c=relaxed/simple; bh=Z64vc+PH5218xi1icQZOA43jLOwOpUFrKJWdxhWwMZI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UnklVom7nblFG5n/HApB2qVSYWdxTbc3ruI//a0QK1KbbXaYAUpudWh2afJDSjeZo2Gu3kCRHe2mT7YLdptcW4o7vwDVTZfgO/4DGCVfNYCHI9a82mriiHjNJ25oF8jOp5xiDnjyXP5iyEdNLptGaHLy37UDBDxAM3vCFA+v+94= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=OTnM/j3d; arc=none smtp.client-ip=209.85.128.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="OTnM/j3d" Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-477b198f4bcso26608775e9.3 for ; Mon, 01 Dec 2025 00:41:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1764578506; x=1765183306; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6/TsDHFpJoTghU0e6gzw66+wowdVuqKszPma+r/MdGc=; b=OTnM/j3dPeXai7b3Ad5V+azIbBzakN2mOQx++FvXRpLTMNkxdEnNZK8Z6wIDEl/pVu sSrD5IJPRbIj0uAuFf2qISiF/2m967Dq+p88l8nCCbHuWxhQALbXote0fPYrr3swXJeA 5hk9AgS7gW1UR0YD40CZD40eOL9wPFfEeDevjviU0/bwrmU20qvPQ1040+gAYeJkdUVA +7EMbiQQ4PEx76tC6UvNaHC4rPf4QgDLGsdkXjSqD/fT1IwVIyoCDleYqClOIR+ocAJ6 U9cEW9Ix1VugVgTgwDN6qj3njxDLkESppBtYpIj+SZ2As6EP94rPE45HKrrpEM7T9EsS ML8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764578506; x=1765183306; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=6/TsDHFpJoTghU0e6gzw66+wowdVuqKszPma+r/MdGc=; b=pRkCNYjasTBCcSNBHLYMp2V4YS6ro2XQpEpJYo7qer87UCfgmVlCoAiJBzeqmsKCs2 H8VTuscp4NS2NR3/lS/J3YiePCcSTj91KhITqlrTtxb0Y1Z4PC1ipRccWqXTo7yS/dB9 qKqQ233u6bNL9j8Vgz8Xs/sCmqdPKMiZJdmu1yBn2R91F1V5kIwLMe1aMEWw1ioIiMmO 7BIrNpHkUJy/0rXCPSKXYU9+97K9DFkKCa1pF3onUZwZhJv4BObRWkO7MrmHlb6T1mxK YfvrzDRuf8RuEWXHa7P1s5Xf4GeqL/nV1sjsdh6HMu3oRpNWCoh1p4rNwDl/pxD8C7Zj vN6w== X-Gm-Message-State: AOJu0YxfWLJOzuErD+kJhHk8TTI/SKysOJCKfbk3TuE/Z9UubhpQFbcc ztfdFe8QG1VHq7mi0h4dTHDU+ggXgvwc0YjBaJjlXY16ubMFd8xnoLKi X-Gm-Gg: ASbGncu6CoS/vb+SCVSVJGtYS6F/+36vnJzOZoj6VK9oZsViTTayF60r3hYXaDVpqEd KHNPuJM1fKdthp9HTdt8gsgw8e1dqP3pi7h7XHvGlHMN+3Oj9/W3piLErLkmdGfqpgNZ3pAOVk4 KXSFLi6PXWFlDG0bmMeNy+dNUmAQ3OofTF7ZhfTzHi75SlPttRm925bUgkSKnUJAAqO80ocbNIg tST64U1mhdJQBSE9X2Ndsu/pmJr0OJHKaCKKiXD0hxTqhhPWHV7G+Fd7ITuiRsuh0MOHDXmDYTm 0tQpSWc6xZNdZ+l29i+3Dfw8L0+SRvTpoS/OVPtEDsouqZwYgqbmVb80QvPAxn9kS0wDgsK7Qc6 IU2XB23re478JNgj/GmOX6T+zTSW53UGWtoC01zAIGNr1gcXOmkOHlKZbxO3oW56/Rj4zCmzjth DIwESYpqTcrSg88Bw4E/GOSyJq4nr1Bw== X-Google-Smtp-Source: AGHT+IEYuCTv935vGmlcGX3etHdHZbqBXh/TzCfPUEc0jsmHA4A4/uxPZ70+glSBPUk5gb6AjXKx3Q== X-Received: by 2002:a05:600c:3541:b0:477:9650:3184 with SMTP id 5b1f17b1804b1-477c0165bc3mr380794285e9.2.1764578505868; Mon, 01 Dec 2025 00:41:45 -0800 (PST) Received: from owl5.. ([2001:861:3201:3d10:4ab6:6efe:9b65:a6af]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42e1ca1a4bbsm24186087f8f.21.2025.12.01.00.41.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Dec 2025 00:41:45 -0800 (PST) From: Gary Bisson To: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Gary Bisson , robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com Subject: [PATCH 2/5] dt-bindings: arm: mediatek: Add ezurio,mt8370-tungsten-smarc Date: Mon, 1 Dec 2025 09:41:37 +0100 Message-ID: <20251201084140.376058-3-bisson.gary@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251201084140.376058-1-bisson.gary@gmail.com> References: <20251201084140.376058-1-bisson.gary@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree bindings support for the Ezurio Tungsten 510 (MT8370) SMARC SOM [1] + Universal SMARC carrier board [2]. [1] https://www.ezurio.com/product/tungsten510-smarc [2] https://www.ezurio.com/system-on-module/accessories/universal-smarc-carrier Signed-off-by: Gary Bisson Acked-by: Krzysztof Kozlowski --- Cc: robh@kernel.org Cc: krzk+dt@kernel.org Cc: conor+dt@kernel.org Cc: matthias.bgg@gmail.com --- Documentation/devicetree/bindings/arm/mediatek.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Document= ation/devicetree/bindings/arm/mediatek.yaml index f04277873694..301f9a1e041c 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -431,6 +431,7 @@ properties: - const: mediatek,mt8365 - items: - enum: + - ezurio,mt8370-tungsten-smarc - grinn,genio-510-sbc - mediatek,mt8370-evk - const: mediatek,mt8370 --=20 2.43.0 From nobody Mon Dec 1 21:31:21 2025 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4BD282F9DA1 for ; Mon, 1 Dec 2025 08:41:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764578511; cv=none; b=mlTYMvSOaKnJ5SVGiabCE+TA2oC1+77ZwyBlTSYLdSyxWNwiXnXrYMoreFXG04KUtsTYLA/eTX4fJYNK9P2JnaG9cpQeoOqL/p6jub2wIZnymzXBSO5q2Y4yv+2Uj+nj5Ej0s/kMtaW85M9NGbtKkWhTjvPPYdQtbYmlVsOJ7Fk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764578511; c=relaxed/simple; bh=cP9ldUvBoRJV7n0qPcQbeaaUhdHAmZeDOafv6SmhAp4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CScY20Vbo5LiS+dPRcFh/wAhLLTL1sKVQ0YQIdOAJi2PxSIojaoNox2oKGDIZgCYq98hELcPeD4oej54PHjakzdNsGF3ifWjzb5JRZd858eoUYGZ9qLUMJlFDV+vUe0tYPx0Giri44+fHf9QAmKy7yeHOM/RkZKD6IlTMTq9r1M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=lf+SxDLD; arc=none smtp.client-ip=209.85.128.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="lf+SxDLD" Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-4775895d69cso16133495e9.0 for ; Mon, 01 Dec 2025 00:41:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1764578507; x=1765183307; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pFWvZEEhiAwGjjJdNwTTNPizb/BR3jr6ZQBEE1XeAik=; b=lf+SxDLDKvNBmHgtrJrYQb/HrRL10Q13BfmCHg/Az9wr5TYXvI6B7QjhRuf+4j1BKc f0fkcJnW1yiulk+ZKJGyYG/d3McialkIHIlOx++80vTb2uglxlSxz+EDlCZYX9nwlHKU nLlYFvinzV+/2MIahEb7Wp3IfbHkjJGwRYti6H+t8mXX9YgA3hDOgZSGqfj3OL08gTzB yEffn28ewnu7PBqRgNDRRtNEy7KzDO/PE7O8rFrjgdc6pqHoyKE7HuyUNXgr6LnjjSGV Jow2srNZqCeGJMz7Z9Qju0hWxLtnMK6yplHNCh/B7cP0RnCQAgAOZCsVgOK5q6369bfS Lu+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764578507; x=1765183307; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=pFWvZEEhiAwGjjJdNwTTNPizb/BR3jr6ZQBEE1XeAik=; b=nOMzqKS2VUvg8IrRzZJyQ/YzjhYwUB8rllwrRDfArqREOtiK3yK0TiulToCnz4g0KQ VEdq/Y9qnC7gA2rgKENCa1+z7NTVzmuLIKZTFszMUutFiSUB0+9AyYAKcFPaIyWdk+KW nz00eE/dUsRl9KIIpwanCuCacD5QFHTuSPo8ArY8ZQg/dvlfoxAoCTvOqCU3eHkOwnol VaemJcjCzeUvxyjmyib8NlU/IY+c9+hWuNZhzh2PvbiZ54VM6HuoxkrFhoh45FR0jNC8 MAWXCLUdLLVX0lFgWJ7Q8nhQ4MbofYb2fTTZfdPp2nVdvODACeqfyfxij6I/z68cwnwN 5QUA== X-Gm-Message-State: AOJu0Yx9i1+NlTEVO36nDSn7Nt206SBLBE/JPrqvjp+ZKug1FtAB4fw5 EryHJw0vUr7jogPo2AsVR4NEW0lHbG84BjLGRJPx2XrufNMYcMXPFxqig68XYg== X-Gm-Gg: ASbGnctOd2zuXA8zwuB5FXSS9b1EO3wiY/aCVzfNBiGQK2k1MndJgwLrAjiDuE8HjSF JuszpxvvZHMxtRCXwZ0alm4m1XZbG1PwhqXgRTtgAm5s8PiMoIOo3Ixh2ezvp0g1GIhKe9vxjwO wQq9MlACgbloXTwbg8pXoEtyiJunNh6roTj+q6Am8OD2/kGdVrrsTsYXf1/x/q5zI1MTigVWyqY tnhwWdJyT5HNAO+lOoBCE8cWUs0yL0fYfndSwjtugFLQlbeW2Zjv3XGzKZxRLSHBYlSvXS6cA8w /VQSiSK+p+8worZyL6UpTJuYcaWTqoTIdfW+d/cE3hcR1TPvJUEVq7VHFvYd8O7gfSUOGyLNU+7 dkQ3/PN17IlgEBjThEqLvqqh5yPVDyyly/wXoOiGT/DH69Cwg2dprT7Y/QVtLNLddSvqTLa6cI1 uBJl0WMDs99gvZSiTGLXs= X-Google-Smtp-Source: AGHT+IGhs6p/Px4HSRx+ii7ASQl1YviEAStwSJLBm22f5Y1vrBH6D+UflFBC3i3z+pJ6RqSaeOB46Q== X-Received: by 2002:a5d:588c:0:b0:429:f14a:9807 with SMTP id ffacd0b85a97d-42e0f34fadbmr26557716f8f.40.1764578506601; Mon, 01 Dec 2025 00:41:46 -0800 (PST) Received: from owl5.. ([2001:861:3201:3d10:4ab6:6efe:9b65:a6af]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42e1ca1a4bbsm24186087f8f.21.2025.12.01.00.41.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Dec 2025 00:41:46 -0800 (PST) From: Gary Bisson To: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Gary Bisson , robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com Subject: [PATCH 3/5] dt-bindings: arm: mediatek: Add ezurio,mt8390-tungsten-smarc Date: Mon, 1 Dec 2025 09:41:38 +0100 Message-ID: <20251201084140.376058-4-bisson.gary@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251201084140.376058-1-bisson.gary@gmail.com> References: <20251201084140.376058-1-bisson.gary@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree bindings support for the Ezurio Tungsten 700 (MT8390) SMARC SOM [1] + Universal SMARC carrier board [2]. [1] https://www.ezurio.com/product/tungsten700-smarc [2] https://www.ezurio.com/system-on-module/accessories/universal-smarc-carrier Signed-off-by: Gary Bisson --- Cc: robh@kernel.org Cc: krzk+dt@kernel.org Cc: conor+dt@kernel.org Cc: matthias.bgg@gmail.com --- Documentation/devicetree/bindings/arm/mediatek.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Document= ation/devicetree/bindings/arm/mediatek.yaml index 301f9a1e041c..cffb0f6ac690 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -438,6 +438,7 @@ properties: - const: mediatek,mt8188 - items: - enum: + - ezurio,mt8390-tungsten-smarc - grinn,genio-700-sbc - mediatek,mt8390-evk - const: mediatek,mt8390 --=20 2.43.0 From nobody Mon Dec 1 21:31:21 2025 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3F14F2F999A for ; Mon, 1 Dec 2025 08:41:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764578513; cv=none; b=CfL5oEbElAcgrltWpC45HA4uYdLrpBpq4XhND80okzvLWJ2hIKNIktsVaDRQ58lGVzFvjfAqGdUqA4rOkOqFOK2UlhzoPCT4SOg7+ptCHTifMWXyZQmhjyLwNw5qFduWfnYuM0qP/7wW9WGLbO995h9MxHCyNu3fV46QW75ubtc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764578513; c=relaxed/simple; bh=BU8RMWZP6druS9SeborlmoQfdLD5VcE+pMV9rZMiZCk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=g/ewvDKMeFBwxPuhkAw46EdyLLVyPFu60FExDrADcAWszEfZhTQgUK/+5KY+SNWHjgPP/z3ARh3LYMQGDE/CwprKPxtU9P9dOZqg9/trAKwPHfmoqoTyj20FIL4LDzenFhfgiJ73+CQcPFyK110V6tm5bZWyixtR74J6wU+hF5c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=W131qhFO; arc=none smtp.client-ip=209.85.128.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="W131qhFO" Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-477ba2c1ca2so45653215e9.2 for ; Mon, 01 Dec 2025 00:41:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1764578508; x=1765183308; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=N5s47OIEkwIjHqO4fwrPx1cEklUoDpseCxiKLKDsAjg=; b=W131qhFOUfVYqImuBaI5HzXC8O1N7+OmpNfZg805X67xMv6ULOHanGpspei/W/SqZt C0hTHJmSFqtt9LwwsuPZ54J6DCeaaH8oHYMxQ/HZHYanrVWba9pusg+qh5LqlvaL8aNM QfJm72tX+5KWqmXDBC9T8GxIUMNevD/XL3qiuZ1iT0uLjYh6ocJBNlTxaI5E8oLgvLVA 1fcB7B4VTmT4trauLFW9KUIRu/QCOPQcEq2PgUVpCzja2VDL+FSSN6MoKFrHiE0NMNEK iDBeHgcfl2xzE3NonNAsvuuoWiT1rjodtvP8KuHj//dTdR6xm82//7CivsHRG0o1K0Lp jm3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764578508; x=1765183308; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=N5s47OIEkwIjHqO4fwrPx1cEklUoDpseCxiKLKDsAjg=; b=HNkJZLVmI/+2BY6aqM5taYpK/ZoESa2Jac93CuD/pWTsjL5prju+lhHKYIwN+jN0U2 wPaqCkDX4O/pL0HZoX/yPfmDcSXTjJGk7aCpDOxzCY5Fn+oN2xftmmTzkKlgHX8kaSN4 8rf+29KD5Vwju6U4bj3fz1pGug8cIMs6hG/Va4xL/ZjelLC8VNQxpDLFxP1rk4M3icA0 Z2hKkssP0cZ4fb4cu9dAstHG3wz6gtilNQ4MGN94gs7+0epGIcjdnqLjlb8oj6ygTaUT TLye7i7Nm26bp/2dAUFQlTAy3ItiGLelBVlQVuP8SYZVQLpD2JXemZOJCGJuWcY3C7UP RHTg== X-Gm-Message-State: AOJu0Yzs4HID4MAXOAmGXtovrNGQZjKIfZSf7imd2KcFsoRTu3574gA1 IC7bNpwxIKHhrGygBkFTkNRfGNZl+yWl4VS1oZvW34wWSKdW7vNc4N1Z X-Gm-Gg: ASbGnctXDC3iTLIMBRA+mT2kxqkPvxVhau9qy55eUWvpFee+3LyprfqO93EeHSu5+R1 lxNLdbalQCoTokODbbXqMHTNAkLEJKbS2ImgaWMPrhsXKbp4E4rI9j3VUKW6XZ9Dg61tu+JsWOD SwrfByS4STreBGGz0MTveesRgZYrZqJBVrdbN6DPDasCWGwSl3uW/w7GXk+PV/86F3MoeY+OhZe eI2Q8YguV/AQLDtqBb2RM8zAce0vneV7hkSlbxSQSB64q797Yw69PfIfOVrFHDB7Peb4JmhewkK UHSWx2uXCSPhUips4yWkOH4dpoYm3MHWiUhcncOlz75lDUChQ09TwjCoA+3yEPY+dPXL4xlrTX8 GOq0G6AZG1C9RYz6AjhVZRyBhMa7XJq3eqaLReF+S652JK8EIsoEU/irPnahaksZrVfFcGDSV6g Rwty/C3QzqWRFoXs6AaVg= X-Google-Smtp-Source: AGHT+IE+lP2nrbIoK5cubaAt9OPbceIgSWDuxjTkuQYkOWFToii5d5QFqy00gyVEAuoYFvbEnf7L8w== X-Received: by 2002:a05:600c:45d0:b0:476:84e9:b571 with SMTP id 5b1f17b1804b1-47904aed576mr234968505e9.14.1764578507350; Mon, 01 Dec 2025 00:41:47 -0800 (PST) Received: from owl5.. ([2001:861:3201:3d10:4ab6:6efe:9b65:a6af]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42e1ca1a4bbsm24186087f8f.21.2025.12.01.00.41.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Dec 2025 00:41:46 -0800 (PST) From: Gary Bisson To: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Gary Bisson , angelogioacchino.delregno@collabora.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com Subject: [PATCH 4/5] arm64: dts: mediatek: add device tree for Tungsten 510 board Date: Mon, 1 Dec 2025 09:41:39 +0100 Message-ID: <20251201084140.376058-5-bisson.gary@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251201084140.376058-1-bisson.gary@gmail.com> References: <20251201084140.376058-1-bisson.gary@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree to support Ezurio Tungsten 510 (MT8370) SMARC SOM [1] + Universal SMARC carrier board [2]. It includes support for the MIPI-DSI BD070LIC3 display which uses the Tianma TM070JDHG30 panel + TI SN65DSI84 MIPI-DSI to LVDS bridge [3]. [1] https://www.ezurio.com/product/tungsten510-smarc [2] https://www.ezurio.com/system-on-module/accessories/universal-smarc-carrier [3] https://www.ezurio.com/product/bd070lic3-7-touchscreen-display Signed-off-by: Gary Bisson --- Cc: angelogioacchino.delregno@collabora.com Cc: robh@kernel.org Cc: krzk+dt@kernel.org Cc: conor+dt@kernel.org Cc: matthias.bgg@gmail.com --- arch/arm64/boot/dts/mediatek/Makefile | 1 + .../dts/mediatek/mt8370-tungsten-smarc.dts | 14 + .../dts/mediatek/mt83x0-tungsten-smarc.dtsi | 1481 +++++++++++++++++ 3 files changed, 1496 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8370-tungsten-smarc.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt83x0-tungsten-smarc.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/me= diatek/Makefile index a4df4c21399e..30d169a31b10 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -99,6 +99,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8195-demo.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8195-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8365-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8370-genio-510-evk.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8370-tungsten-smarc.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8395-genio-1200-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8390-genio-700-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8395-kontron-3-5-sbc-i1200.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8370-tungsten-smarc.dts b/arch/= arm64/boot/dts/mediatek/mt8370-tungsten-smarc.dts new file mode 100644 index 000000000000..d713ef77df3a --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8370-tungsten-smarc.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Ezurio LLC + * Author: Gary Bisson + */ +/dts-v1/; +#include "mt8370.dtsi" +#include "mt83x0-tungsten-smarc.dtsi" + +/ { + model =3D "Ezurio Tungsten510 SMARC (MT8370)"; + compatible =3D "ezurio,mt8370-tungsten-smarc", "mediatek,mt8370", + "mediatek,mt8188"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt83x0-tungsten-smarc.dtsi b/arch= /arm64/boot/dts/mediatek/mt83x0-tungsten-smarc.dtsi new file mode 100644 index 000000000000..acdafd4936fe --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt83x0-tungsten-smarc.dtsi @@ -0,0 +1,1481 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Ezurio LLC + * Author: Gary Bisson + */ + +#include "mt6359.dtsi" +#include +#include +#include +#include +#include +#include + +/ { + aliases { + dsi0 =3D &disp_dsi0; + ethernet0 =3D ð + i2c0 =3D &i2c0; + i2c1 =3D &i2c1; + i2c2 =3D &i2c2; + i2c3 =3D &i2c3; + i2c4 =3D &i2c4; + i2c5 =3D &i2c5; + i2c6 =3D &i2c6; + mmc0 =3D &mmc0; + mmc1 =3D &mmc1; + mmc2 =3D &mmc2; + rtc0 =3D &rv3028; + rtc1 =3D &mt6359rtc; + serial0 =3D &uart0; + }; + + backlight_lcd0: backlight-lcd0 { + compatible =3D "pwm-backlight"; + brightness-levels =3D <0 1023>; + default-brightness-level =3D <768>; + num-interpolated-steps =3D <1023>; + enable-gpios =3D <&pio 30 GPIO_ACTIVE_HIGH>; + pwms =3D <&disp_pwm0 0 30000>; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + firmware { + optee { + compatible =3D "linaro,optee-tz"; + method =3D "smc"; + }; + }; + + memory@40000000 { + device_type =3D "memory"; + reg =3D <0 0x40000000 0x1 0x00000000>; + }; + + panel-dsi0 { + compatible =3D "tianma,tm070jdhg30"; + backlight =3D <&backlight_lcd0>; + + port { + dsi0_panel_in: endpoint { + remote-endpoint =3D <&sn65dsi84_bridge_out>; + }; + }; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + /* + * 12 MiB reserved for OP-TEE (BL32) + * +-----------------------+ 0x43e0_0000 + * | SHMEM 2MiB | + * +-----------------------+ 0x43c0_0000 + * | | TA_RAM 8MiB | + * + TZDRAM +--------------+ 0x4340_0000 + * | | TEE_RAM 2MiB | + * +-----------------------+ 0x4320_0000 + */ + optee_reserved: optee@43200000 { + no-map; + reg =3D <0 0x43200000 0 0x00c00000>; + }; + + scp_mem: memory@50000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x50000000 0 0x2900000>; + no-map; + }; + + /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_reserved: memory@54600000 { + no-map; + reg =3D <0 0x54600000 0x0 0x200000>; + }; + + apu_mem: memory@55000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x55000000 0 0x1400000>; /* 20 MB */ + }; + + vpu_mem: memory@57000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x57000000 0 0x1400000>; /* 20 MB */ + }; + + adsp_mem: memory@60000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x60000000 0 0xf00000>; + no-map; + }; + + afe_dma_mem: memory@60f00000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x60f00000 0 0x100000>; + no-map; + }; + + adsp_dma_mem: memory@61000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x61000000 0 0x100000>; + no-map; + }; + }; + + regulator-efuse { + compatible =3D "regulator-output"; + vout-supply =3D <&mt6359_vefuse_ldo_reg>; + }; + + sdcard_en_3v3: regulator-sdcard-en { + compatible =3D "regulator-fixed"; + regulator-always-on; + regulator-name =3D "sdcard_en_3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpio =3D <&pio 111 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb_p0_vbus: regulator-usb-p0-vbus { + compatible =3D "regulator-fixed"; + regulator-name =3D "vbus_p0"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&pio 84 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb_p1_vbus: regulator-usb-p1-vbus { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usb1_hub_pins>; + regulator-name =3D "vbus_p1"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + gpio =3D <&pio 147 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb_p2_vbus: regulator-usb-p2-vbus { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usb2_eth_pins>; + regulator-name =3D "vbus_p2"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + gpio =3D <&pio 80 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wifi_pwrseq_pins>; + post-power-on-delay-ms =3D <200>; + reset-gpios =3D <&pio 89 GPIO_ACTIVE_LOW>; + }; +}; + +&adsp { + memory-region =3D <&adsp_dma_mem>, <&adsp_mem>; + status =3D "okay"; +}; + +&afe { + memory-region =3D <&afe_dma_mem>; + status =3D "okay"; +}; + +&cpu0 { + cpu-supply =3D <&mt6359_vcore_buck_reg>; +}; + +&cpu1 { + cpu-supply =3D <&mt6359_vcore_buck_reg>; +}; + +&cpu2 { + cpu-supply =3D <&mt6359_vcore_buck_reg>; +}; + +&cpu3 { + cpu-supply =3D <&mt6359_vcore_buck_reg>; +}; + +&cpu6 { + cpu-supply =3D <&mt6315_6_vbuck1>; +}; + +&cpu7 { + cpu-supply =3D <&mt6315_6_vbuck1>; +}; + +&disp_pwm0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&disp_pwm0_pins>; + status =3D "okay"; +}; + +&disp_dsi0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dsi0_in: endpoint { + remote-endpoint =3D <&dither0_out>; + }; + }; + + port@1 { + reg =3D <1>; + dsi0_out: endpoint { + remote-endpoint =3D <&sn65dsi84_bridge_in>; + }; + }; + }; +}; + +&dither0_in { + remote-endpoint =3D <&postmask0_out>; +}; + +&dither0_out { + remote-endpoint =3D <&dsi0_in>; +}; + +ð { + phy-mode =3D"rgmii-id"; + phy-handle =3D <ðernet_phy0>; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <ð_default_pins>; + pinctrl-1 =3D <ð_sleep_pins>; + mediatek,mac-wol; + snps,reset-gpio =3D <&pio 27 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us =3D <0 11000 1000>; + status =3D "okay"; +}; + +ð_mdio { + ethernet_phy0: ethernet-phy@7 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0x7>; + interrupts-extended =3D <&pio 148 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&gamma0_out { + remote-endpoint =3D <&postmask0_in>; +}; + +&gpu { + mali-supply =3D <&mt6359_vproc2_buck_reg>; + status =3D "okay"; +}; + +&i2c0 { + pinctrl-names =3D "default", "gpio"; + pinctrl-0 =3D <&i2c0_pins>; + pinctrl-1 =3D <&i2c0_gpio_pins>; + scl-gpios =3D <&pio 55 GPIO_OPEN_DRAIN>; + sda-gpios =3D <&pio 56 GPIO_OPEN_DRAIN>; + clock-frequency =3D <100000>; + status =3D "okay"; + + i2c-mux-gp@73 { + compatible =3D "nxp,pca9546"; + reg =3D <0x73>; + reset-gpios =3D <&pio 6 GPIO_ACTIVE_LOW>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + i2c_mux_gp_0: i2cmux-gp@0 { + clock-frequency =3D <100000>; + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c_mux_gp_1: i2cmux-gp@1 { + clock-frequency =3D <100000>; + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c_mux_gp_2: i2cmux-gp@2 { + clock-frequency =3D <100000>; + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c_mux_gp_3: i2cmux-gp@3 { + clock-frequency =3D <100000>; + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +&i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c1_pins>; + clock-frequency =3D <400000>; + status =3D "okay"; +}; + +&i2c2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c2_pins>; + clock-frequency =3D <400000>; + status =3D "okay"; + + i2c-mux-lcd@73 { + compatible =3D "nxp,pca9546"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c_mux_smarc_lcd_pins>; + reg =3D <0x73>; + reset-gpios =3D <&pio 5 GPIO_ACTIVE_LOW>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + i2c_mux_lcd_0: i2cmux-lcd@0 { + clock-frequency =3D <100000>; + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c_mux_lcd_1: i2cmux-lcd@1 { + clock-frequency =3D <100000>; + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c_mux_lcd_2: i2cmux-lcd@2 { + clock-frequency =3D <100000>; + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c_mux_lcd_3: i2cmux-lcd@3 { + clock-frequency =3D <100000>; + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +&i2c3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c3_pins>; + clock-frequency =3D <400000>; + status =3D "okay"; +}; + +&i2c4 { + pinctrl-names =3D "default", "default"; + pinctrl-0 =3D <&i2c4_pins>; + clock-frequency =3D <400000>; + status =3D "okay"; +}; + +&i2c_mux_gp_0 { + rv3028: rtc@52 { + compatible =3D "microcrystal,rv3028"; + reg =3D <0x52>; + interrupts-extended =3D <&pio 42 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rv3028_pins>; + #clock-cells =3D <0>; + wakeup-source; + }; +}; + +&i2c_mux_gp_1 { + typec@60 { + compatible =3D "ti,hd3ss3220"; + interrupts-extended =3D <&pio 45 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hd3ss3220_pins>; + reg =3D <0x60>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + hd3ss3220_in_ep: endpoint { + remote-endpoint =3D <&ss_ep>; + }; + }; + + port@1 { + reg =3D <1>; + hd3ss3220_out_ep: endpoint { + remote-endpoint =3D <&usb_role_switch>; + }; + }; + }; + }; +}; + +&i2c_mux_gp_2 { + codec@1a { + #sound-dai-cells =3D <0>; + clocks =3D <&topckgen CLK_TOP_I2SO1>; + compatible =3D "wlf,wm8962"; + gpio-cfg =3D < + 0x0000 /* n/c */ + 0x0000 /* gpio2: */ + 0x0000 /* gpio3: */ + 0x0000 /* n/c */ + 0x8081 /* gpio5:HP detect */ + 0x8095 /* gpio6:Mic detect */ + >; + reg =3D <0x1a>; + }; +}; + +&i2c_mux_lcd_2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + bridge@2c { + compatible =3D "ti,sn65dsi84"; + reg =3D <0x2c>; + enable-gpios =3D <&pio 25 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&dsi0_sn65dsi84_pins>; + status =3D "okay"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + sn65dsi84_bridge_in: endpoint { + remote-endpoint =3D <&dsi0_out>; + data-lanes =3D <1 2 3 4>; + }; + }; + + port@2 { + reg =3D <2>; + + sn65dsi84_bridge_out: endpoint { + remote-endpoint =3D <&dsi0_panel_in>; + }; + }; + }; + }; + + touchscren@5d { + compatible =3D "goodix,gt911"; + reg =3D <0x5d>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ts_dsi0_goodix_pins>; + interrupts-extended =3D <&pio 146 IRQ_TYPE_LEVEL_HIGH>; + irq-gpios =3D <&pio 146 GPIO_ACTIVE_HIGH>; + reset-gpios =3D <&pio 7 GPIO_ACTIVE_HIGH>; + }; +}; + +&mfg0 { + domain-supply =3D <&mt6359_vproc2_buck_reg>; +}; + +&mfg1 { + domain-supply =3D <&mt6359_vsram_others_ldo_reg>; +}; + +&mmc0 { + status =3D "okay"; + pinctrl-names =3D "default", "state_uhs"; + pinctrl-0 =3D <&mmc0_default_pins>; + pinctrl-1 =3D <&mmc0_uhs_pins>; + bus-width =3D <8>; + max-frequency =3D <200000000>; + cap-mmc-highspeed; + cap-mmc-hw-reset; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + supports-cqe; + cap-mmc-hw-reset; + no-sdio; + no-sd; + hs400-ds-delay =3D <0x1481b>; + vmmc-supply =3D <&mt6359_vemc_1_ldo_reg>; + vqmmc-supply =3D <&mt6359_vufs_ldo_reg>; + non-removable; +}; + +&mmc1 { + status =3D "okay"; + pinctrl-names =3D "default", "state_uhs"; + pinctrl-0 =3D <&mmc1_default_pins>; + pinctrl-1 =3D <&mmc1_uhs_pins>; + bus-width =3D <4>; + max-frequency =3D <200000000>; + cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-sdr104; + cd-gpios =3D <&pio 2 GPIO_ACTIVE_LOW>; + vqmmc-supply =3D <&mt6359_vsim1_ldo_reg>; + vmmc-supply =3D <&sdcard_en_3v3>; +}; + +&mmc2 { + status =3D "okay"; + pinctrl-names =3D "default", "state_uhs", "state_eint"; + pinctrl-0 =3D <&mmc2_default_pins>; + pinctrl-1 =3D <&mmc2_uhs_pins>; + pinctrl-2 =3D <&mmc2_eint_pins>; + eint-gpios =3D <&pio 172 0>; + bus-width =3D <4>; + max-frequency =3D <200000000>; + cap-sd-highspeed; + sd-uhs-sdr104; + keep-power-in-suspend; + enable-sdio-wakeup; + cap-sdio-async-int; + cap-sdio-irq; + no-mmc; + no-sd; + non-removable; + vmmc-supply =3D <&mt6359_vcn33_2_bt_ldo_reg>; + vqmmc-supply =3D <&mt6359_vcn18_ldo_reg>; + mmc-pwrseq =3D <&wifi_pwrseq>; +}; + +&mipi_tx_config0 { + status =3D "okay"; +}; + +&mt6359codec { + mediatek,mic-type-0 =3D <1>; + mediatek,mic-type-1 =3D <3>; + mediatek,mic-type-2 =3D <0>; + mediatek,dmic-mode =3D <0>; +}; + +&mt6359_vbbck_ldo_reg { + regulator-always-on; +}; + +&mt6359_vcn18_ldo_reg { + regulator-name =3D "vcn18_pmu"; + regulator-always-on; + regulator-boot-on; +}; + +&mt6359_vcn33_1_bt_ldo_reg { + regulator-name =3D "vcn33_1_pmu"; + regulator-always-on; +}; + +&mt6359_vcn33_2_bt_ldo_reg { + regulator-name =3D "vcn33_2_pmu"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + regulator-boot-on; +}; + +&mt6359_vcore_buck_reg { + regulator-name =3D "dvdd_proc_l"; + regulator-always-on; +}; + +&mt6359_vemc_1_ldo_reg { + regulator-always-on; +}; + +&mt6359_vgpu11_buck_reg { + regulator-name =3D "dvdd_core"; + regulator-always-on; +}; + +&mt6359_vmodem_buck_reg { + regulator-always-on; +}; + +&mt6359_vpa_buck_reg { + regulator-name =3D "vpa_pmu"; + regulator-always-on; +}; + +&mt6359_vproc2_buck_reg { + /* The name "vgpu" is required by mtk-regulator-coupler */ + regulator-name =3D "vgpu"; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <800000>; + regulator-coupled-with =3D <&mt6359_vsram_others_ldo_reg>; + regulator-coupled-max-spread =3D <225000>; + regulator-always-on; +}; + +&mt6359_vs2_buck_reg { + regulator-min-microvolt =3D <1600000>; + regulator-boot-on; +}; + +&mt6359_vpu_buck_reg { + regulator-name =3D "dvdd_adsp"; + regulator-always-on; +}; + +&mt6359_vrf12_ldo_reg { + regulator-name =3D "va12_abb2_pmu"; + regulator-always-on; +}; + +&mt6359_vsram_md_ldo_reg { + regulator-always-on; +}; + +&mt6359_vsram_others_ldo_reg { + /* The name "vsram_gpu" is required by mtk-regulator-coupler */ + regulator-name =3D "vsram_gpu"; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <800000>; + regulator-coupled-with =3D <&mt6359_vproc2_buck_reg>; + regulator-coupled-max-spread =3D <225000>; + regulator-always-on; +}; + +&mt6359_vsim1_ldo_reg { + regulator-name =3D "vsim1_pmu"; + regulator-max-microvolt =3D <1800000>; + regulator-enable-ramp-delay =3D <480>; +}; + +&mt6359_vufs_ldo_reg { + regulator-name =3D "vufs18_pmu"; + regulator-always-on; +}; + +&ovl0_in { + remote-endpoint =3D <&vdosys0_ep_main>; +}; + +&pcie { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie_default_pins>; + status =3D "okay"; +}; + +&pciephy { + status =3D "okay"; +}; + +&pmic { + interrupt-parent =3D <&pio>; + interrupts =3D <222 IRQ_TYPE_LEVEL_HIGH>; + + mt6359keys: keys { + compatible =3D "mediatek,mt6359-keys"; + mediatek,long-press-mode =3D <1>; + power-off-time-sec =3D <0>; + + power-key { + linux,keycodes =3D <116>; + wakeup-source; + }; + }; +}; + +&postmask0_in { + remote-endpoint =3D <&gamma0_out>; +}; + +&postmask0_out { + remote-endpoint =3D <&dither0_in>; +}; + +&scp_cluster { + status =3D "okay"; +}; + +&scp_c0 { + firmware-name =3D "mediatek/mt8188/scp.img"; + memory-region =3D <&scp_mem>; + status =3D "okay"; +}; + +&spi0 { + pinctrl-0 =3D <&spi0_pins>; + pinctrl-names =3D "default"; + mediatek,pad-select =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; +}; + +&spi1 { + pinctrl-0 =3D <&spi1_pins>; + pinctrl-names =3D "default"; + mediatek,pad-select =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; +}; + +&spmi { + #address-cells =3D <1>; + #size-cells =3D <2>; + + mt6315_6: mt6315@6 { + compatible =3D "mediatek,mt6315-regulator"; + reg =3D <0x6 0 0xb>; + + regulators { + mt6315_6_vbuck1: vbuck1 { + regulator-compatible =3D "vbuck1"; + regulator-name =3D "vbuck1"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1193750>; + regulator-enable-ramp-delay =3D <256>; + regulator-allowed-modes =3D <0 1 2>; + regulator-always-on; + mtk,combined-regulator =3D <2>; + }; + + mt6315_6_vbuck3: vbuck3 { + regulator-compatible =3D "vbuck3"; + regulator-name =3D "vbuck3"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1193750>; + regulator-enable-ramp-delay =3D <256>; + regulator-allowed-modes =3D <0 1 2>; + regulator-always-on; + }; + + mt6315_6_vbuck4: vbuck4 { + regulator-compatible =3D "vbuck4"; + regulator-name =3D "vbuck4"; + regulator-min-microvolt =3D <1193750>; + regulator-max-microvolt =3D <1193750>; + regulator-enable-ramp-delay =3D <256>; + regulator-allowed-modes =3D <0 1 2>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1193750>; + }; + }; + }; + }; +}; + +&uart0 { + pinctrl-0 =3D <&uart0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&uart1 { + pinctrl-0 =3D <&uart1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&uart2 { + pinctrl-0 =3D <&uart2_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&ssusb0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usbotg_pins>; + maximum-speed =3D "high-speed"; + usb-role-switch; + dr_mode =3D "otg"; + vusb33-supply =3D <&mt6359_vusb_ldo_reg>; + wakeup-source; + status =3D "okay"; + + connector { + compatible =3D "usb-c-connector"; + label =3D "USB-C"; + data-role =3D "dual"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + hs_ep: endpoint { + remote-endpoint =3D <&usb_hs_ep>; + }; + }; + + port@1 { + reg =3D <1>; + ss_ep: endpoint { + remote-endpoint =3D <&hd3ss3220_in_ep>; + }; + }; + }; + }; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + usb_hs_ep: endpoint { + remote-endpoint =3D <&hs_ep>; + }; + }; + + port@1 { + reg =3D <1>; + usb_role_switch: endpoint { + remote-endpoint =3D <&hd3ss3220_out_ep>; + }; + }; + }; +}; + +&u2port0 { + status =3D "okay"; +}; + +&u3phy0 { + status =3D "okay"; +}; + +&xhci0 { + vbus-supply =3D <&usb_p0_vbus>; + vusb33-supply =3D <&mt6359_vusb_ldo_reg>; + status =3D "okay"; +}; + +&ssusb1 { + pinctrl-0 =3D <&usb1_pins>; + pinctrl-names =3D "default"; + vusb33-supply =3D <&mt6359_vusb_ldo_reg>; + dr_mode =3D "host"; + wakeup-source; + status =3D "okay"; +}; + +&u2port1 { + status =3D "okay"; +}; + +&u3port1 { + status =3D "okay"; +}; + +&u3phy1 { + status =3D "okay"; +}; + +&xhci1 { + vbus-supply =3D <&usb_p1_vbus>; + vusb33-supply =3D <&mt6359_vusb_ldo_reg>; + status =3D "okay"; +}; + +&ssusb2 { + maximum-speed =3D "high-speed"; + dr_mode =3D "host"; + vusb33-supply =3D <&mt6359_vusb_ldo_reg>; + status =3D "okay"; + wakeup-source; +}; + +&u2port2 { + status =3D "okay"; +}; + +&u3phy2 { + status =3D "okay"; +}; + +&xhci2 { + vbus-supply =3D <&usb_p2_vbus>; + vusb33-supply =3D <&mt6359_vusb_ldo_reg>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + + ethernet@1 { + compatible =3D "usb424,7850"; + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethernet-phy@1 { + reg =3D <1>; + microchip,led-modes =3D < + LAN78XX_LINK_1000_ACTIVITY + LAN78XX_LINK_10_ACTIVITY + LAN78XX_LINK_10_100_ACTIVITY + LAN78XX_LINK_ACTIVITY + >; + }; + }; + }; +}; + +&vdosys0 { + port { + #address-cells =3D <1>; + #size-cells =3D <0>; + + vdosys0_ep_main: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&ovl0_in>; + }; + }; +}; + +&watchdog { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&watchdog_pins>; +}; + +&pio { + audio_pins: audio-pins { + pins-aud-pmic { + pinmux =3D < + PINMUX_GPIO101__FUNC_O_AUD_CLK_MOSI + PINMUX_GPIO102__FUNC_O_AUD_SYNC_MOSI + PINMUX_GPIO103__FUNC_O_AUD_DAT_MOSI0 + PINMUX_GPIO104__FUNC_O_AUD_DAT_MOSI1 + PINMUX_GPIO105__FUNC_I0_AUD_DAT_MISO0 + PINMUX_GPIO106__FUNC_I0_AUD_DAT_MISO1 + >; + }; + + pins-pcm-wifi { + pinmux =3D < + PINMUX_GPIO121__FUNC_B0_PCM_CLK + PINMUX_GPIO122__FUNC_B0_PCM_SYNC + PINMUX_GPIO123__FUNC_O_PCM_DO + PINMUX_GPIO124__FUNC_I0_PCM_DI + >; + }; + + pins-i2s { + pinmux =3D < + PINMUX_GPIO119__FUNC_O_I2SO1_MCK + PINMUX_GPIO112__FUNC_O_I2SO1_WS + PINMUX_GPIO120__FUNC_O_I2SO1_BCK + PINMUX_GPIO113__FUNC_O_I2SO1_D0 + PINMUX_GPIO110__FUNC_I0_I2SIN_D0 + >; + }; + }; + + disp_pwm0_pins: disp-pwm0-pins { + pins { + pinmux =3D ; + bias-pull-down; + }; + }; + + dsi0_sn65dsi84_pins: dsi0-sn65dsi84-pins { + pins-irq { + pinmux =3D ; + bias-pull-down; + input-enable; + }; + + pins-enable { + pinmux =3D ; + bias-pull-down; + }; + }; + + eth_default_pins: eth-default-pins { + pins-txd { + pinmux =3D , + , + , + ; + drive-strength =3D ; + }; + pins-cc { + pinmux =3D , + , + ; + drive-strength =3D ; + }; + pins-rxd { + pinmux =3D , + , + , + , + ; + drive-strength =3D ; + bias-pull-up =3D ; + }; + pins-mdio { + pinmux =3D , + ; + drive-strength =3D ; + input-enable; + }; + pins-power { + pinmux =3D ; /* GP_EQOS_RESET */ + output-high; + }; + pins-intr { + pinmux =3D ; /* GPIRQ_EQOS_PHY */ + bias-pull-up =3D ; + input-enable; + }; + }; + + eth_sleep_pins: eth-sleep-pins { + pins-txd { + pinmux =3D , + , + , + ; + }; + pins-cc { + pinmux =3D , + , + , + ; + }; + pins-rxd { + pinmux =3D , + , + , + ; + }; + pins-mdio { + pinmux =3D , + ; + input-disable; + bias-disable; + }; + }; + + gpio_keys_pins: gpio-keys-pins { + pins-keys { + pinmux =3D , + , + ; + bias-pull-up; + }; + }; + + hd3ss3220_pins: hd3ss3320-pins { + pins-irq { + pinmux =3D ; + bias-pull-up =3D ; + input-enable; + }; + }; + + hdmi_vreg_pins: hdmi-vreg-pins { + pins-pwr { + pinmux =3D ; + bias-disable; + }; + }; + + hdmi_pins: hdmi-pins { + pins-hotplug { + pinmux =3D ; + bias-pull-down; + }; + + pins-cec { + pinmux =3D ; + bias-disable; + }; + + pins-ddc { + pinmux =3D , + ; + drive-strength =3D <10>; + }; + }; + + i2c0_pins: i2c0-pins { + pins-bus { + pinmux =3D , + ; + bias-pull-up =3D ; + drive-strength-microamp =3D <1000>; + }; + }; + + i2c0_gpio_pins: i2c0-gpio-pins { + pins-gpio { + pinmux =3D ; + bias-pull-up =3D ; + drive-strength-microamp =3D <1000>; + }; + }; + + i2c1_pins: i2c1-pins { + pins-bus { + pinmux =3D , + ; + bias-pull-up =3D ; + drive-strength-microamp =3D <1000>; + }; + }; + + i2c2_pins: i2c2-pins { + pins-bus { + pinmux =3D , + ; + bias-pull-up =3D ; + drive-strength-microamp =3D <1000>; + }; + }; + + i2c3_pins: i2c3-pins { + pins-bus { + pinmux =3D , + ; + bias-pull-up =3D ; + drive-strength-microamp =3D <1000>; + }; + }; + + i2c4_pins: i2c4-pins { + pins-bus { + pinmux =3D , + ; + bias-pull-up =3D ; + drive-strength-microamp =3D <1000>; + }; + }; + + i2c_mux_smarc_lcd_pins: i2c-mux-smarc-lcd-pins { + pins-reset { + pinmux =3D ; + bias-pull-down; + }; + }; + + mmc0_default_pins: mmc0-default-pins { + pins-cmd-dat { + pinmux =3D , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength =3D ; + bias-pull-up =3D ; + }; + + pins-clk { + pinmux =3D ; + drive-strength =3D ; + bias-pull-down =3D ; + }; + + pins-rst { + pinmux =3D ; + drive-strength =3D ; + bias-pull-up =3D ; + }; + }; + + mmc0_uhs_pins: mmc0-uhs-pins { + pins-cmd-dat { + pinmux =3D , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength =3D ; + bias-pull-up =3D ; + }; + + pins-clk { + pinmux =3D ; + drive-strength =3D ; + bias-pull-down =3D ; + }; + + pins-ds { + pinmux =3D ; + drive-strength =3D ; + bias-pull-down =3D ; + }; + + pins-rst { + pinmux =3D ; + drive-strength =3D ; + bias-pull-up =3D ; + }; + }; + + mmc1_default_pins: mmc1-default-pins { + pins-cmd-dat { + pinmux =3D , + , + , + , + ; + input-enable; + drive-strength =3D ; + bias-pull-up =3D ; + }; + + pins-pwr { + pinmux =3D ; + bias-pull-down; + }; + + pins-pullup { + pinmux =3D ; + bias-pull-up; + }; + + pins-clk { + pinmux =3D ; + drive-strength =3D ; + bias-pull-down =3D ; + }; + + pins-insert { + pinmux =3D ; + bias-pull-up; + }; + }; + + mmc1_uhs_pins: mmc1-uhs-pins { + pins-cmd-dat { + pinmux =3D , + , + , + , + ; + input-enable; + drive-strength =3D ; + bias-pull-up =3D ; + }; + + pins-clk { + pinmux =3D ; + drive-strength =3D ; + bias-pull-down =3D ; + }; + }; + + mmc2_default_pins: mmc2-default-pins { + pins-clk { + pinmux =3D ; + drive-strength =3D ; + bias-pull-down =3D ; + }; + + pins-cmd-dat { + pinmux =3D , + , + , + , + ; + input-enable; + drive-strength =3D ; + bias-pull-up =3D ; + }; + }; + + mmc2_uhs_pins: mmc2-uhs-pins { + pins-clk { + pinmux =3D ; + drive-strength =3D ; + bias-pull-down =3D ; + }; + + pins-cmd-dat { + pinmux =3D , + , + , + , + ; + input-enable; + drive-strength =3D ; + bias-pull-up =3D ; + }; + }; + + mmc2_eint_pins: mmc2-eint-pins { + pins-dat1 { + pinmux =3D ; + input-enable; + bias-pull-up =3D ; + }; + }; + + rv3028_pins: rv3028-pins { + pins-irq { + pinmux =3D ; + bias-pull-up =3D ; + input-enable; + }; + }; + + spi0_pins: spi0-pins { + pins-spi { + pinmux =3D , + , + , + ; + bias-disable; + }; + }; + + spi1_pins: spi1-pins { + pins-spi { + pinmux =3D , + , + , + ; + bias-disable; + }; + }; + + pcie_default_pins: pcie-default-pins { + pins { + pinmux =3D , + , + ; + bias-pull-up; + }; + }; + + ts_dsi0_goodix_pins: ts-dsi0-goodix-pins { + pins-irq { + pinmux =3D ; + bias-pull-up =3D ; + input-enable; + }; + + pins-reset { + pinmux =3D ; + bias-pull-down; + }; + }; + + uart0_pins: uart0-pins { + pins { + pinmux =3D , + ; + bias-pull-up; + }; + }; + + uart1_pins: uart1-pins { + pins { + pinmux =3D , + ; + bias-pull-up; + }; + }; + + uart2_pins: uart2-pins { + pins { + pinmux =3D , + ; + bias-pull-up; + }; + }; + + usbotg_pins: usbotg-pins { + pins-iddig { + pinmux =3D ; + input-enable; + bias-pull-up; + }; + + pins-valid { + pinmux =3D ; + input-enable; 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([2001:861:3201:3d10:4ab6:6efe:9b65:a6af]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42e1ca1a4bbsm24186087f8f.21.2025.12.01.00.41.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Dec 2025 00:41:47 -0800 (PST) From: Gary Bisson To: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Gary Bisson , angelogioacchino.delregno@collabora.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com Subject: [PATCH 5/5] arm64: dts: mediatek: add device tree for Tungsten 700 board Date: Mon, 1 Dec 2025 09:41:40 +0100 Message-ID: <20251201084140.376058-6-bisson.gary@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251201084140.376058-1-bisson.gary@gmail.com> References: <20251201084140.376058-1-bisson.gary@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree to support Ezurio Tungsten 700 (MT8390) SMARC SOM [1] + Universal SMARC carrier board [2]. It includes support for the MIPI-DSI BD070LIC3 display which uses the Tianma TM070JDHG30 panel + TI SN65DSI84 MIPI-DSI to LVDS bridge [3]. [1] https://www.ezurio.com/product/tungsten700-smarc [2] https://www.ezurio.com/system-on-module/accessories/universal-smarc-carrier [3] https://www.ezurio.com/product/bd070lic3-7-touchscreen-display Signed-off-by: Gary Bisson --- Cc: angelogioacchino.delregno@collabora.com Cc: robh@kernel.org Cc: krzk+dt@kernel.org Cc: conor+dt@kernel.org Cc: matthias.bgg@gmail.com --- arch/arm64/boot/dts/mediatek/Makefile | 1 + .../dts/mediatek/mt8390-tungsten-smarc.dts | 22 +++++++++++++++++++ 2 files changed, 23 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dts diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/me= diatek/Makefile index 30d169a31b10..85f338344dd3 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -102,6 +102,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8370-genio-510-evk.d= tb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8370-tungsten-smarc.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8395-genio-1200-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8390-genio-700-evk.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8390-tungsten-smarc.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8395-kontron-3-5-sbc-i1200.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8395-radxa-nio-12l.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8395-radxa-nio-12l-8-hd-panel.dtbo diff --git a/arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dts b/arch/= arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dts new file mode 100644 index 000000000000..f1cf2821107f --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Ezurio LLC + * Author: Gary Bisson + */ +/dts-v1/; +#include "mt8188.dtsi" +#include "mt83x0-tungsten-smarc.dtsi" + +/ { + model =3D "Ezurio Tungsten700 SMARC (MT8390)"; + compatible =3D "ezurio,mt8390-tungsten-smarc", "mediatek,mt8390", + "mediatek,mt8188"; +}; + +&cpu4 { + cpu-supply =3D <&mt6359_vcore_buck_reg>; +}; + +&cpu5 { + cpu-supply =3D <&mt6359_vcore_buck_reg>; +}; --=20 2.43.0