From nobody Mon Dec 1 22:36:53 2025 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 383B91A0BD6 for ; Mon, 1 Dec 2025 01:15:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764551760; cv=none; b=ghkV1aZa/ZWERt+bINdxiYZbKYFVFkF1Xc04pEidzh+8LGa5o/QD7rvy1MaSQ+HbNrC2yq59Bc/djQhT1Hw/FdEyLoho1GFJr+V5ym5ueEm5PMjAxHrjX1FUmDos7DNaI7DayiCgnQhoNspIjfDFrnYzZZ3LhWNgKBKYQJPx/qM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764551760; c=relaxed/simple; bh=IRggN3lmtuL1+sRl7lfs+N472nG3VqsOqQtqcI6fI1I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=S2jlEWgkcS+CcMcdVqeuBITDlAAs1+bdhZUaUidXi8B4YrNU/i85ZfkigEX0GkRKguNa6TD8pmnSjQlVwsp0TKdrjydIoL4y9RH47D6FfDui4OZBWuZXrKZbrJmdqBDCdk1UDmV01W9N5bsV7N4ZGsc5SXLdN+wjhonoHj4ZUlQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=YB7dHId5; arc=none smtp.client-ip=209.85.128.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="YB7dHId5" Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-477632b0621so21286025e9.2 for ; Sun, 30 Nov 2025 17:15:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1764551755; x=1765156555; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=caWS6hPO4Twt32QiX0Ivthekj2EdbIJLrCvPNIpwXHU=; b=YB7dHId5c2L/m4gcabJCjaOz7qt33PZi07+6m7ucpj/pXE/4wmREMpA+Yu/j9sAnRP kFq37apsSwpxKziId/WKqNk0Gk9e6V25lpCmgN8kYIot6SbRPGFT1eCC60FVzNGuC/w5 8WPi9Y5U2/CAh2cIoUh7GnA+Piz+JbRmM+o2EjuJx6PwLjQiOYkvLOROZnsniu5yww4+ Ykgo7wyjkB5895TPD9wFemZaIT1VFgwmuQ2hPIDDnmpkMav89tkLde2UQ7EguXZYtsg0 azt5m4ei1IfttLhfcB+QDWE366FZOo42PVUbFaGFal3D5av+zhfYghA0TTi7xWWxDBy+ HCvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764551755; x=1765156555; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=caWS6hPO4Twt32QiX0Ivthekj2EdbIJLrCvPNIpwXHU=; b=HPrirUsRIaiZJVOfDlDm4iLDHBXZVenWo03aJBcOw/eodL8kXF3lkjXqbhC9avGV4u GYsurhptFMJDyv4erFGj80BASl80osCujS5BVfN9vkwnJ7rpp3NN4qo+qW/wQ5PGQlUU K7To2jHGPlSl8Uod2hFbGR40G4kgLQ/DgSNpvN4HSAXry8ne45o82VdVsXCcLJsqSNUK QfA00mo7qsML9RCpXXTdPIIExHzwU1wOx4tlJ5ERtcKEq9lQxg+14f9eB1n+cVNxbx77 3GsrK1ceEqhsgatrcXB6BF5iveWpfNKKWbaUQ4C5z8BKj211U4aQx4wNNykRzLBftB1O z9cQ== X-Forwarded-Encrypted: i=1; AJvYcCX4TPz8AXumm6hrZCcxH/yLOZKMlNO8g7NI+VzCOnda7KtvI18DcQpksbo4B992fHcTgTRoyei2Gf3HNv8=@vger.kernel.org X-Gm-Message-State: AOJu0YxfAGRf0pOWpDXZm/Tcls2H1SDpbPq241Ke3uBGCDHWVvi2Rki1 P33oMI16f7QEq0M+mnBXVNSlu7P8nO5vR3xkTRlUNhvGS0xIVn/HFtko X-Gm-Gg: ASbGnctDS0xr+5tbRSM9P5+dqVbYxrL7dGYzlH8on5n6vLvM593Ty4yYbJzPYbXt6H9 gp6RHUqPr892numiUk0AknCyyhdig0jB7CmzJijimuRbmNXNkIyh3rK5JZUlP3j/vPD/xC00ulV xsrPNFA4I/kFHLDCDmJUiv/f7v8et5NR3ZMdNIa4Un6nkAX2HqIGhzvKyWxFVph+ocxOyVsFa3B W2g5Sz/8bE7S/FD7Z6tC1vfT2+fdjMQ+gvFcxuOhax4ERrJHpTcbb6NKJmJROhgKAhB3xbQN0Wa EEgsDBX3wOr2Jryb0KQLiLDaJb24vZCSdjkykMXyqUxmbvUaWloqLDNKJ/v7SF91vXXfchlfyID b/Q/MFt/isgd9Chcw48e6LHLDEfi2JDijTf7Rw+Eno24xuebCXNmW+BTwL/IvsR6yPSrDbERuPd U5yaT5A9gT7KYhb7poTgJppQzF3HQYHD/8JNMxGiXGbwF49Ys1fCvSvQ== X-Google-Smtp-Source: AGHT+IHEW3Rds/1KMTMF2j8T5zYO4ugi7BR6V2zJhUiHqId4d56QcNhq/Vr3IbhqYQtytyHF6ksGVg== X-Received: by 2002:a05:600c:4ec7:b0:477:9b4a:a82 with SMTP id 5b1f17b1804b1-477c1138445mr357584795e9.35.1764551755281; Sun, 30 Nov 2025 17:15:55 -0800 (PST) Received: from alarm (92.40.200.0.threembb.co.uk. [92.40.200.0]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-479110b6da9sm216152305e9.0.2025.11.30.17.15.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Nov 2025 17:15:54 -0800 (PST) From: Dale Whinham To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: =?UTF-8?q?J=C3=A9r=C3=B4me=20de=20Bretagne?= , Dale Whinham , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/8] arm64: dts: qcom: Add support for Surface Pro 11 Date: Mon, 1 Dec 2025 01:14:45 +0000 Message-ID: <20251201011457.17422-5-daleyo@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251201011457.17422-1-daleyo@gmail.com> References: <20251201011457.17422-1-daleyo@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Add device trees for the Qualcomm X1E and X1P-based Microsoft Surface Pro 11 machines (codenamed 'Denali'). This device is very similar to the Surface Laptop 7 ('Romulus'). Use a similar strategy to x1-asus-zenbook-a14.dtsi so that we can create x1e and x1p-specific flavors of the device tree without too much code duplication. Hardware support is similar to other X1E machines. The most notable features missing are: - Touchscreen and pen - Cameras (and status LEDs) Tested-by: J=C3=A9r=C3=B4me de Bretagne Signed-off-by: Dale Whinham --- arch/arm64/boot/dts/qcom/Makefile | 4 + .../boot/dts/qcom/x1-microsoft-denali.dtsi | 1338 +++++++++++++++++ .../qcom/x1e80100-microsoft-denali-oled.dts | 20 + .../dts/qcom/x1p64100-microsoft-denali.dts | 16 + 4 files changed, 1378 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi create mode 100644 arch/arm64/boot/dts/qcom/x1e80100-microsoft-denali-oled= .dts create mode 100644 arch/arm64/boot/dts/qcom/x1p64100-microsoft-denali.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 296688f7cb26..fe2054ee093e 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -336,6 +336,8 @@ x1e80100-hp-omnibook-x14-el2-dtbs :=3D x1e80100-hp-omni= book-x14.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) +=3D x1e80100-hp-omnibook-x14.dtb x1e80100-hp-omni= book-x14-el2.dtb x1e80100-lenovo-yoga-slim7x-el2-dtbs :=3D x1e80100-lenovo-yoga-slim7x.dtb = x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) +=3D x1e80100-lenovo-yoga-slim7x.dtb x1e80100-leno= vo-yoga-slim7x-el2.dtb +x1e80100-microsoft-denali-oled-el2-dtbs :=3D x1e80100-microsoft-denali-ole= d.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) +=3D x1e80100-microsoft-denali-oled.dtb x1e80100-m= icrosoft-denali-oled-el2.dtb x1e80100-microsoft-romulus13-el2-dtbs :=3D x1e80100-microsoft-romulus13.dt= b x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) +=3D x1e80100-microsoft-romulus13.dtb x1e80100-mic= rosoft-romulus13-el2.dtb x1e80100-microsoft-romulus15-el2-dtbs :=3D x1e80100-microsoft-romulus15.dt= b x1-el2.dtbo @@ -350,3 +352,5 @@ x1p42100-hp-omnibook-x14-el2-dtbs :=3D x1p42100-hp-omni= book-x14.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) +=3D x1p42100-hp-omnibook-x14.dtb x1p42100-hp-omni= book-x14-el2.dtb x1p42100-lenovo-thinkbook-16-el2-dtbs :=3D x1p42100-lenovo-thinkbook-16.dt= b x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) +=3D x1p42100-lenovo-thinkbook-16.dtb x1p42100-len= ovo-thinkbook-16-el2.dtb +x1p64100-microsoft-denali-el2-dtbs :=3D x1p64100-microsoft-denali.dtb x1-e= l2.dtbo +dtb-$(CONFIG_ARCH_QCOM) +=3D x1p64100-microsoft-denali.dtb x1p64100-micros= oft-denali-el2.dtb diff --git a/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi b/arch/arm64= /boot/dts/qcom/x1-microsoft-denali.dtsi new file mode 100644 index 000000000000..64eabe2b96cf --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi @@ -0,0 +1,1338 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2025 Dale Whinham + */ + +#include +#include +#include +#include + +#include "x1e80100-pmics.dtsi" + +/ { + aliases { + serial0 =3D &uart2; + serial1 =3D &uart14; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + + pinctrl-0 =3D <&hall_int_n_default>; + pinctrl-names =3D "default"; + + switch-lid { + gpios =3D <&tlmm 2 GPIO_ACTIVE_LOW>; + linux,input-type =3D ; + linux,code =3D ; + wakeup-source; + wakeup-event-action =3D ; + }; + }; + + pmic-glink { + compatible =3D "qcom,x1e80100-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells =3D <1>; + #size-cells =3D <0>; + orientation-gpios =3D <&tlmm 121 GPIO_ACTIVE_HIGH>, + <&tlmm 123 GPIO_ACTIVE_HIGH>; + + /* Left-side rear port */ + connector@0 { + compatible =3D "usb-c-connector"; + reg =3D <0>; + power-role =3D "dual"; + data-role =3D "dual"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + pmic_glink_ss0_hs_in: endpoint { + remote-endpoint =3D <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg =3D <1>; + + pmic_glink_ss0_ss_in: endpoint { + remote-endpoint =3D <&retimer_ss0_ss_out>; + }; + }; + + port@2 { + reg =3D <2>; + + pmic_glink_ss0_con_sbu_in: endpoint { + remote-endpoint =3D <&retimer_ss0_con_sbu_out>; + }; + }; + }; + }; + + /* Left-side front port */ + connector@1 { + compatible =3D "usb-c-connector"; + reg =3D <1>; + power-role =3D "dual"; + data-role =3D "dual"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + pmic_glink_ss1_hs_in: endpoint { + remote-endpoint =3D <&usb_1_ss1_dwc3_hs>; + }; + }; + + port@1 { + reg =3D <1>; + + pmic_glink_ss1_ss_in: endpoint { + remote-endpoint =3D <&retimer_ss1_ss_out>; + }; + }; + + port@2 { + reg =3D <2>; + + pmic_glink_ss1_con_sbu_in: endpoint { + remote-endpoint =3D <&retimer_ss1_con_sbu_out>; + }; + }; + }; + }; + }; + + reserved-memory { + linux,cma { + compatible =3D "shared-dma-pool"; + size =3D <0x0 0x8000000>; + reusable; + linux,cma-default; + }; + }; + + vreg_edp_3p3: regulator-edp-3p3 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_EDP_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&edp_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_1p15: regulator-rtmr0-1p15 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR0_1P15"; + + regulator-min-microvolt =3D <1150000>; + regulator-max-microvolt =3D <1150000>; + + gpio =3D <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&rtmr0_1p15_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_1p8: regulator-rtmr0-1p8 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR0_1P8"; + + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + gpio =3D <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&rtmr0_1p8_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_3p3: regulator-rtmr0-3p3 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR0_3P3"; + + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&rtmr0_3p3_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p15: regulator-rtmr1-1p15 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR1_1P15"; + + regulator-min-microvolt =3D <1150000>; + regulator-max-microvolt =3D <1150000>; + + gpio =3D <&tlmm 188 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&rtmr1_1p15_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p8: regulator-rtmr1-1p8 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR1_1P8"; + + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + gpio =3D <&tlmm 175 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&rtmr1_1p8_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_3p3: regulator-rtmr1-3p3 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR1_3P3"; + + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&tlmm 186 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&rtmr1_3p3_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_nvme: regulator-nvme { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_NVME_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&tlmm 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&nvme_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vph_pwr: regulator-vph-pwr { + compatible =3D "regulator-fixed"; + + regulator-name =3D "vph_pwr"; + regulator-min-microvolt =3D <3700000>; + regulator-max-microvolt =3D <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_WCN_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&wcn_sw_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + /* + * TODO: These two regulators are actually part of the removable M.2 + * card and not the CRD mainboard. Need to describe this differently. + * Functionally it works correctly, because all we need to do is to + * turn on the actual 3.3V supply above. + */ + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_WCN_0P95"; + regulator-min-microvolt =3D <950000>; + regulator-max-microvolt =3D <950000>; + + vin-supply =3D <&vreg_wcn_3p3>; + }; + + vreg_wcn_1p9: regulator-wcn-1p9 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_WCN_1P9"; + regulator-min-microvolt =3D <1900000>; + regulator-max-microvolt =3D <1900000>; + + vin-supply =3D <&vreg_wcn_3p3>; + }; + + sound { + compatible =3D "qcom,x1e80100-sndcard"; + model =3D "X1E80100-Microsoft-Surface-Pro-11"; + audio-routing =3D "SpkrLeft IN", "WSA WSA_SPK1 OUT", + "SpkrRight IN", "WSA WSA_SPK2 OUT", + "VA DMIC0", "vdd-micb", + "VA DMIC1", "vdd-micb"; + + wsa-dai-link { + link-name =3D "WSA Playback"; + + cpu { + sound-dai =3D <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai =3D <&left_spkr>, <&right_spkr>, <&swr0 0>, <&lpass_wsamacro= 0>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + + va-dai-link { + link-name =3D "VA Capture"; + + cpu { + sound-dai =3D <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + codec { + sound-dai =3D <&lpass_vamacro 0>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + }; + + wcn7850-pmu { + compatible =3D "qcom,wcn7850-pmu"; + + vdd-supply =3D <&vreg_wcn_0p95>; + vddio-supply =3D <&vreg_l15b_1p8>; + vddaon-supply =3D <&vreg_wcn_0p95>; + vdddig-supply =3D <&vreg_wcn_0p95>; + vddrfa1p2-supply =3D <&vreg_wcn_1p9>; + vddrfa1p8-supply =3D <&vreg_wcn_1p9>; + + wlan-enable-gpios =3D <&tlmm 117 GPIO_ACTIVE_HIGH>; + bt-enable-gpios =3D <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-0 =3D <&wcn_wlan_bt_en>; + pinctrl-names =3D "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name =3D "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name =3D "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name =3D "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name =3D "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name =3D "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name =3D "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name =3D "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name =3D "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name =3D "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name =3D "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id =3D "b"; + + vdd-bob1-supply =3D <&vph_pwr>; + vdd-bob2-supply =3D <&vph_pwr>; + vdd-l1-l4-l10-supply =3D <&vreg_s4c_1p8>; + vdd-l2-l13-l14-supply =3D <&vreg_bob1>; + vdd-l5-l16-supply =3D <&vreg_bob1>; + vdd-l6-l7-supply =3D <&vreg_bob2>; + vdd-l8-l9-supply =3D <&vreg_bob1>; + vdd-l12-supply =3D <&vreg_s5j_1p2>; + vdd-l15-supply =3D <&vreg_s4c_1p8>; + vdd-l17-supply =3D <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name =3D "vreg_bob1"; + regulator-min-microvolt =3D <3008000>; + regulator-max-microvolt =3D <3960000>; + regulator-initial-mode =3D ; + }; + + vreg_bob2: bob2 { + regulator-name =3D "vreg_bob2"; + regulator-min-microvolt =3D <2504000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name =3D "vreg_l1b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name =3D "vreg_l2b_3p0"; + regulator-min-microvolt =3D <3072000>; + regulator-max-microvolt =3D <3072000>; + regulator-initial-mode =3D ; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name =3D "vreg_l4b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name =3D "vreg_l6b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2960000>; + regulator-initial-mode =3D ; + }; + + vreg_l8b_3p0: ldo8 { + regulator-name =3D "vreg_l8b_3p0"; + regulator-min-microvolt =3D <3072000>; + regulator-max-microvolt =3D <3072000>; + regulator-initial-mode =3D ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name =3D "vreg_l9b_2p9"; + regulator-min-microvolt =3D <2960000>; + regulator-max-microvolt =3D <2960000>; + regulator-initial-mode =3D ; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name =3D "vreg_l10b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l12b_1p2: ldo12 { + regulator-name =3D "vreg_l12b_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name =3D "vreg_l13b_3p0"; + regulator-min-microvolt =3D <3072000>; + regulator-max-microvolt =3D <3072000>; + regulator-initial-mode =3D ; + }; + + vreg_l14b_3p0: ldo14 { + regulator-name =3D "vreg_l14b_3p0"; + regulator-min-microvolt =3D <3072000>; + regulator-max-microvolt =3D <3072000>; + regulator-initial-mode =3D ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name =3D "vreg_l15b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name =3D "vreg_l17b_2p5"; + regulator-min-microvolt =3D <2504000>; + regulator-max-microvolt =3D <2504000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-1 { + compatible =3D "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id =3D "c"; + + vdd-l1-supply =3D <&vreg_s5j_1p2>; + vdd-l2-supply =3D <&vreg_s1f_0p7>; + vdd-l3-supply =3D <&vreg_s1f_0p7>; + vdd-s4-supply =3D <&vph_pwr>; + + vreg_s4c_1p8: smps4 { + regulator-name =3D "vreg_s4c_1p8"; + regulator-min-microvolt =3D <1856000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + }; + + vreg_l1c_1p2: ldo1 { + regulator-name =3D "vreg_l1c_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_l2c_0p8: ldo2 { + regulator-name =3D "vreg_l2c_0p8"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <880000>; + regulator-initial-mode =3D ; + }; + + vreg_l3c_0p8: ldo3 { + regulator-name =3D "vreg_l3c_0p8"; + regulator-min-microvolt =3D <912000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-2 { + compatible =3D "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id =3D "d"; + + vdd-l1-supply =3D <&vreg_s1f_0p7>; + vdd-l2-supply =3D <&vreg_s1f_0p7>; + vdd-l3-supply =3D <&vreg_s4c_1p8>; + vdd-s1-supply =3D <&vph_pwr>; + + vreg_l1d_0p8: ldo1 { + regulator-name =3D "vreg_l1d_0p8"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <880000>; + regulator-initial-mode =3D ; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name =3D "vreg_l2d_0p9"; + regulator-min-microvolt =3D <912000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + }; + + vreg_l3d_1p8: ldo3 { + regulator-name =3D "vreg_l3d_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-3 { + compatible =3D "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id =3D "e"; + + vdd-l2-supply =3D <&vreg_s1f_0p7>; + vdd-l3-supply =3D <&vreg_s5j_1p2>; + + vreg_l2e_0p8: ldo2 { + regulator-name =3D "vreg_l2e_0p8"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <880000>; + regulator-initial-mode =3D ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name =3D "vreg_l3e_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-4 { + compatible =3D "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id =3D "f"; + + vdd-l1-supply =3D <&vreg_s5j_1p2>; + vdd-l2-supply =3D <&vreg_s5j_1p2>; + vdd-l3-supply =3D <&vreg_s5j_1p2>; + vdd-s1-supply =3D <&vph_pwr>; + + vreg_s1f_0p7: smps1 { + regulator-name =3D "vreg_s1f_0p7"; + regulator-min-microvolt =3D <700000>; + regulator-max-microvolt =3D <1100000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-6 { + compatible =3D "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id =3D "i"; + + vdd-l1-supply =3D <&vreg_s4c_1p8>; + vdd-l2-supply =3D <&vreg_s5j_1p2>; + vdd-l3-supply =3D <&vreg_s1f_0p7>; + vdd-s1-supply =3D <&vph_pwr>; + vdd-s2-supply =3D <&vph_pwr>; + + vreg_s1i_0p9: smps1 { + regulator-name =3D "vreg_s1i_0p9"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + }; + + vreg_s2i_1p0: smps2 { + regulator-name =3D "vreg_s2i_1p0"; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1100000>; + regulator-initial-mode =3D ; + }; + + vreg_l1i_1p8: ldo1 { + regulator-name =3D "vreg_l1i_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name =3D "vreg_l2i_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_l3i_0p8: ldo3 { + regulator-name =3D "vreg_l3i_0p8"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <880000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-7 { + compatible =3D "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id =3D "j"; + + vdd-l1-supply =3D <&vreg_s1f_0p7>; + vdd-l2-supply =3D <&vreg_s5j_1p2>; + vdd-l3-supply =3D <&vreg_s1f_0p7>; + vdd-s5-supply =3D <&vph_pwr>; + + vreg_s5j_1p2: smps5 { + regulator-name =3D "vreg_s5j_1p2"; + regulator-min-microvolt =3D <1256000>; + regulator-max-microvolt =3D <1304000>; + regulator-initial-mode =3D ; + }; + + vreg_l1j_0p8: ldo1 { + regulator-name =3D "vreg_l1j_0p8"; + regulator-min-microvolt =3D <912000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + }; + + vreg_l2j_1p2: ldo2 { + regulator-name =3D "vreg_l2j_1p2"; + regulator-min-microvolt =3D <1256000>; + regulator-max-microvolt =3D <1256000>; + regulator-initial-mode =3D ; + }; + + vreg_l3j_0p8: ldo3 { + regulator-name =3D "vreg_l3j_0p8"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <880000>; + regulator-initial-mode =3D ; + }; + }; +}; + +&gpu { + status =3D "okay"; + + zap-shader { + memory-region =3D <&gpu_microcode_mem>; + firmware-name =3D "qcom/x1e80100/microsoft/qcdxkmsuc8380.mbn"; + }; +}; + +&i2c0 { + clock-frequency =3D <400000>; + + status =3D "disabled"; +}; + +&i2c3 { + clock-frequency =3D <400000>; + + status =3D "okay"; + + /* Left-side rear port */ + typec-mux@8 { + compatible =3D "parade,ps8830"; + reg =3D <0x8>; + + reset-gpios =3D <&pm8550_gpios 10 GPIO_ACTIVE_LOW>; + + clocks =3D <&rpmhcc RPMH_RF_CLK3>; + + vdd-supply =3D <&vreg_rtmr0_1p15>; + vdd33-supply =3D <&vreg_rtmr0_3p3>; + vdd33-cap-supply =3D <&vreg_rtmr0_3p3>; + vddar-supply =3D <&vreg_rtmr0_1p15>; + vddat-supply =3D <&vreg_rtmr0_1p15>; + vddio-supply =3D <&vreg_rtmr0_1p8>; + + pinctrl-0 =3D <&rtmr0_default>; + pinctrl-names =3D "default"; + + retimer-switch; + orientation-switch; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + retimer_ss0_ss_out: endpoint { + remote-endpoint =3D <&pmic_glink_ss0_ss_in>; + }; + }; + + port@1 { + reg =3D <1>; + + retimer_ss0_ss_in: endpoint { + remote-endpoint =3D <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg =3D <2>; + + retimer_ss0_con_sbu_out: endpoint { + remote-endpoint =3D <&pmic_glink_ss0_con_sbu_in>; + }; + }; + }; + }; +}; + +&i2c4 { + clock-frequency =3D <400000>; + + status =3D "disabled"; +}; + +&i2c5 { + clock-frequency =3D <400000>; + + status =3D "disabled"; +}; + +&i2c7 { + clock-frequency =3D <400000>; + + status =3D "okay"; + + /* Left-side front port */ + typec-mux@8 { + compatible =3D "parade,ps8830"; + reg =3D <0x8>; + + reset-gpios =3D <&tlmm 176 GPIO_ACTIVE_LOW>; + + clocks =3D <&rpmhcc RPMH_RF_CLK4>; + + vdd-supply =3D <&vreg_rtmr1_1p15>; + vdd33-supply =3D <&vreg_rtmr1_3p3>; + vdd33-cap-supply =3D <&vreg_rtmr1_3p3>; + vddar-supply =3D <&vreg_rtmr1_1p15>; + vddat-supply =3D <&vreg_rtmr1_1p15>; + vddio-supply =3D <&vreg_rtmr1_1p8>; + + retimer-switch; + orientation-switch; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + retimer_ss1_ss_out: endpoint { + remote-endpoint =3D <&pmic_glink_ss1_ss_in>; + }; + }; + + port@1 { + reg =3D <1>; + + retimer_ss1_ss_in: endpoint { + remote-endpoint =3D <&usb_1_ss1_qmpphy_out>; + }; + }; + + port@2 { + reg =3D <2>; + + retimer_ss1_con_sbu_out: endpoint { + remote-endpoint =3D <&pmic_glink_ss1_con_sbu_in>; + }; + }; + }; + }; +}; + +&lpass_tlmm { + spkr_01_sd_n_active: spkr-01-sd-n-active-state { + pins =3D "gpio12"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + output-low; + }; + + spkr_23_sd_n_active: spkr-23-sd-n-active-state { + pins =3D "gpio13"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + output-low; + }; +}; + +&lpass_vamacro { + pinctrl-0 =3D <&dmic01_default>, <&dmic23_default>; + pinctrl-names =3D "default"; + + vdd-micb-supply =3D <&vreg_l1b_1p8>; + qcom,dmic-sample-rate =3D <4800000>; +}; + +&mdss { + status =3D "okay"; +}; + +&mdss_dp0 { + status =3D "okay"; +}; + +&mdss_dp0_out { + link-frequencies =3D /bits/ 64 <1620000000 2700000000 5400000000 81000000= 00>; +}; + +&mdss_dp1 { + status =3D "okay"; +}; + +&mdss_dp1_out { + link-frequencies =3D /bits/ 64 <1620000000 2700000000 5400000000 81000000= 00>; +}; + +&mdss_dp3 { + compatible =3D "qcom,x1e80100-dp"; + /delete-property/ #sound-dai-cells; + + status =3D "okay"; + + aux-bus { + panel: panel { + compatible =3D "edp-panel"; + enable-gpios =3D <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>; + power-supply =3D <&vreg_edp_3p3>; + + pinctrl-0 =3D <&edp_bl_en>; + pinctrl-names =3D "default"; + + port { + edp_panel_in: endpoint { + remote-endpoint =3D <&mdss_dp3_out>; + }; + }; + }; + }; + + ports { + port@1 { + reg =3D <1>; + + mdss_dp3_out: endpoint { + data-lanes =3D <0 1 2 3>; + link-frequencies =3D /bits/ 64 <1620000000 2700000000 5400000000 81000= 00000>; + + remote-endpoint =3D <&edp_panel_in>; + }; + }; + }; +}; + +&mdss_dp3_phy { + vdda-phy-supply =3D <&vreg_l3j_0p8>; + vdda-pll-supply =3D <&vreg_l2j_1p2>; + + status =3D "okay"; +}; + +&pcie4 { + status =3D "okay"; +}; + +&pcie4_phy { + vdda-phy-supply =3D <&vreg_l3i_0p8>; + vdda-pll-supply =3D <&vreg_l3e_1p2>; + + status =3D "okay"; +}; + +&pcie4_port0 { + wifi@0 { + compatible =3D "pci17cb,1107"; + reg =3D <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply =3D <&vreg_pmu_aon_0p59>; + vddwlcx-supply =3D <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply =3D <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply =3D <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply =3D <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply =3D <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply =3D <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply =3D <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply =3D <&vreg_pmu_pcie_1p8>; + }; +}; + +&pcie6a { + perst-gpios =3D <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 154 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply =3D <&vreg_nvme>; + + pinctrl-0 =3D <&pcie6a_default>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie6a_phy { + vdda-phy-supply =3D <&vreg_l1d_0p8>; + vdda-pll-supply =3D <&vreg_l2j_1p2>; + + status =3D "okay"; +}; + +&pm8550_gpios { + rtmr0_default: rtmr0-reset-n-active-state { + pins =3D "gpio10"; + function =3D "normal"; + power-source =3D <1>; /* 1.8V */ + }; + + rtmr0_3p3_reg_en: rtmr0-3p3-reg-en-state { + pins =3D "gpio11"; + function =3D "normal"; + power-source =3D <1>; /* 1.8V */ + }; +}; + +&pm8550ve_9_gpios { + rtmr0_1p8_reg_en: rtmr0-1p8-reg-en-state { + pins =3D "gpio8"; + function =3D "normal"; + power-source =3D <1>; /* 1.8V */ + }; +}; + +&pmc8380_3_gpios { + edp_bl_en: edp-bl-en-state { + pins =3D "gpio4"; + function =3D "normal"; + power-source =3D <1>; /* 1.8V */ + input-disable; + output-enable; + }; +}; + +&pmc8380_5_gpios { + rtmr0_1p15_reg_en: rtmr0-1p15-reg-en-state { + pins =3D "gpio8"; + function =3D "normal"; + power-source =3D <1>; /* 1.8V */ + }; +}; + +&qupv3_0 { + status =3D "okay"; +}; + +&qupv3_1 { + status =3D "okay"; +}; + +&qupv3_2 { + status =3D "okay"; +}; + +&remoteproc_adsp { + firmware-name =3D "qcom/x1e80100/microsoft/Denali/qcadsp8380.mbn", + "qcom/x1e80100/microsoft/Denali/adsp_dtb.mbn"; + + status =3D "okay"; +}; + +&remoteproc_cdsp { + firmware-name =3D "qcom/x1e80100/microsoft/Denali/qccdsp8380.mbn", + "qcom/x1e80100/microsoft/Denali/cdsp_dtb.mbn"; + + status =3D "okay"; +}; + +&smb2360_0 { + status =3D "okay"; +}; + +&smb2360_0_eusb2_repeater { + vdd18-supply =3D <&vreg_l3d_1p8>; + vdd3-supply =3D <&vreg_l2b_3p0>; +}; + +&smb2360_1 { + status =3D "okay"; +}; + +&smb2360_1_eusb2_repeater { + vdd18-supply =3D <&vreg_l3d_1p8>; + vdd3-supply =3D <&vreg_l14b_3p0>; +}; + +&smb2360_2 { + status =3D "okay"; +}; + +&smb2360_2_eusb2_repeater { + vdd18-supply =3D <&vreg_l3d_1p8>; + vdd3-supply =3D <&vreg_l8b_3p0>; +}; + +&swr0 { + status =3D "okay"; + + pinctrl-0 =3D <&wsa_swr_active>, <&spkr_01_sd_n_active>; + pinctrl-names =3D "default"; + + /* WSA8845, Left Speaker */ + left_spkr: speaker@0,0 { + compatible =3D "sdw20217020400"; + reg =3D <0 0>; + reset-gpios =3D <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "SpkrLeft"; + vdd-1p8-supply =3D <&vreg_l15b_1p8>; + vdd-io-supply =3D <&vreg_l12b_1p2>; + qcom,port-mapping =3D <1 2 3 7 10 13>; + }; + + /* WSA8845, Right Speaker */ + right_spkr: speaker@0,1 { + compatible =3D "sdw20217020400"; + reg =3D <0 1>; + reset-gpios =3D <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "SpkrRight"; + vdd-1p8-supply =3D <&vreg_l15b_1p8>; + vdd-io-supply =3D <&vreg_l12b_1p2>; + qcom,port-mapping =3D <4 5 6 7 11 13>; + }; +}; + +&tlmm { + gpio-reserved-ranges =3D <44 4>, /* SPI (TPM) */ + <238 1>; /* UFS Reset */ + + hall_int_n_default: hall-int-n-state { + pins =3D "gpio2"; + function =3D "gpio"; + bias-disable; + }; + + nvme_reg_en: nvme-reg-en-state { + pins =3D "gpio18"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + edp_reg_en: edp-reg-en-state { + pins =3D "gpio70"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + }; + + ssam_state: ssam-state-state { + pins =3D "gpio91"; + function =3D "gpio"; + bias-disable; + }; + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins =3D "gpio147"; + function =3D "pcie4_clk"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-n-pins { + pins =3D "gpio146"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + wake-n-pins { + pins =3D "gpio148"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + pcie6a_default: pcie6a-default-state { + perst-n-pins { + pins =3D "gpio152"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + clkreq-n-pins { + pins =3D "gpio153"; + function =3D "pcie6a_clk"; + drive-strength =3D <2>; + bias-pull-up; + }; + + wake-n-pins { + pins =3D "gpio154"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + rtmr1_1p8_reg_en: rtmr1-1p8-reg-en-state { + pins =3D "gpio175"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + rtmr1_3p3_reg_en: rtmr1-3p3-reg-en-state { + pins =3D "gpio186"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + rtmr1_1p15_reg_en: rtmr1-1p15-reg-en-state { + pins =3D "gpio188"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + cam_indicator_en: cam-indicator-en-state { + pins =3D "gpio225"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + wcn_sw_en: wcn-sw-en-state { + pins =3D "gpio214"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + wcn_wlan_bt_en: wcn-wlan-bt-en-state { + pins =3D "gpio116", "gpio117"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; +}; + +&uart2 { + status =3D "okay"; + + embedded-controller { + compatible =3D "microsoft,surface-sam"; + + interrupts-extended =3D <&tlmm 91 IRQ_TYPE_EDGE_RISING>; + + current-speed =3D <4000000>; + + pinctrl-0 =3D <&ssam_state>; + pinctrl-names =3D "default"; + }; +}; + +&uart14 { + status =3D "okay"; + + bluetooth { + compatible =3D "qcom,wcn7850-bt"; + max-speed =3D <3200000>; + + vddaon-supply =3D <&vreg_pmu_aon_0p59>; + vddwlcx-supply =3D <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply =3D <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply =3D <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply =3D <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply =3D <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply =3D <&vreg_pmu_rfa_1p8>; + }; +}; + +&usb_1_ss0_hsphy { + vdd-supply =3D <&vreg_l3j_0p8>; + vdda12-supply =3D <&vreg_l2j_1p2>; + + phys =3D <&smb2360_0_eusb2_repeater>; + + status =3D "okay"; +}; + +&usb_1_ss0_qmpphy { + vdda-phy-supply =3D <&vreg_l2j_1p2>; + vdda-pll-supply =3D <&vreg_l1j_0p8>; + + status =3D "okay"; +}; + +&usb_1_ss0 { + status =3D "okay"; +}; + +&usb_1_ss0_dwc3 { + dr_mode =3D "host"; +}; + +&usb_1_ss0_dwc3_hs { + remote-endpoint =3D <&pmic_glink_ss0_hs_in>; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint =3D <&retimer_ss0_ss_in>; +}; + +&usb_1_ss1_hsphy { + vdd-supply =3D <&vreg_l3j_0p8>; + vdda12-supply =3D <&vreg_l2j_1p2>; + + phys =3D <&smb2360_1_eusb2_repeater>; + + status =3D "okay"; +}; + +&usb_1_ss1_qmpphy { + vdda-phy-supply =3D <&vreg_l2j_1p2>; + vdda-pll-supply =3D <&vreg_l2d_0p9>; + + status =3D "okay"; +}; + +&usb_1_ss1 { + status =3D "okay"; +}; + +&usb_1_ss1_dwc3 { + dr_mode =3D "host"; +}; + +&usb_1_ss1_dwc3_hs { + remote-endpoint =3D <&pmic_glink_ss1_hs_in>; +}; + +&usb_1_ss1_qmpphy_out { + remote-endpoint =3D <&retimer_ss1_ss_in>; +}; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-denali-oled.dts b/= arch/arm64/boot/dts/qcom/x1e80100-microsoft-denali-oled.dts new file mode 100644 index 000000000000..f7159eef1d85 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-denali-oled.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2025 Dale Whinham + */ + +/dts-v1/; + +#include "x1e80100.dtsi" +#include "x1-microsoft-denali.dtsi" + +/ { + model =3D "Microsoft Surface Pro 11th Edition (OLED)"; + compatible =3D "microsoft,denali-oled", "microsoft,denali", + "qcom,x1e80100"; +}; + +&panel { + compatible =3D "samsung,atna30dw01", "samsung,atna33xc20"; +}; diff --git a/arch/arm64/boot/dts/qcom/x1p64100-microsoft-denali.dts b/arch/= arm64/boot/dts/qcom/x1p64100-microsoft-denali.dts new file mode 100644 index 000000000000..7c064ad49395 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1p64100-microsoft-denali.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2025 Dale Whinham + */ + +/dts-v1/; + +#include "x1e80100.dtsi" +#include "x1-microsoft-denali.dtsi" + +/ { + model =3D "Microsoft Surface Pro 11th Edition (LCD)"; + compatible =3D "microsoft,denali-lcd", "microsoft,denali", + "qcom,x1p64100", "qcom,x1e80100"; +}; --=20 2.52.0