From nobody Mon Dec 1 22:35:40 2025 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E04D633985 for ; Mon, 1 Dec 2025 01:15:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764551754; cv=none; b=d2ZOQBSNLSW0kjh32UtdZM2G0AbYsD8fFCZNLePNEqyZIfFeZqsGSFaGjK9sQfxDTuScng+mioFUeLeVniF/dIu8z46bwEO5JJmDATmQf7eRVte16w4amgsz6eJ6iKcTeqAl7mfqqQiL9ypVDxICGOahpHuXq+ByvwGBLSM2bvQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764551754; c=relaxed/simple; bh=8fxORl1I8YAECASFsj9/Ws4g18jKmbkYYWVQiXzVhnA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=IgnniFZf8dkqzqdPntXYZNFF71++xU+iw9M9fXPbMxKlysQb3nP0Y0+MYYXNGtDtH48ko8a0UGL+1lKN3gYDmNUJa6479EK389/DdC7J1TQj5xlW/EkuwzYtowPpVj6MZrCdaFwzeFlNDkkVuK5WCuJBSFAaP73axHoJSljZW/A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=DKRO9QXr; arc=none smtp.client-ip=209.85.128.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="DKRO9QXr" Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-4775ae77516so37229135e9.1 for ; Sun, 30 Nov 2025 17:15:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1764551751; x=1765156551; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XHyZ6FAtJU5qO1dJcRGwRE2nReT0pakALIINJQlT6dM=; b=DKRO9QXrpzp8z0JDS36Ax/pkIudX7mwe39x/bOlEZNerBn1nyOJi+pNNMIiJzPZt0I uTXDqvA/slPcpaNjl+3qOCwK2Y1aE+5lb4H1ZSSN0VIzfrHoqI4NDzrjrdF1qN54Mqy/ s6eT+9RO6SvD57fjZCnxGFYl3Ua7SwiiOr3hCBDZhqhNrzKBXzO5cGAShbTgPhhfszdK nITLpL/CrC1r6BQHm8CeIfCh0mpea81enTOzyMNaC0TsItwmF0GOAV315HO2EXvG8i8J wFLe7H2OdRYoB9gOGrIFjBkvLcLRKVUNUYBSTr7zVDm1gV7DZ2GcCoA77glPi0xmZ1Rw Sm1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764551751; x=1765156551; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=XHyZ6FAtJU5qO1dJcRGwRE2nReT0pakALIINJQlT6dM=; b=HMwLH67oD0TVyQgBzGI7p54dXzsMht2XiWD+mKz0F01QWdVYg76Iy4Ki8vM5fqC038 sXQpcijbyfg/X6HCvh+4GdqZP1WUksyO1wtz/zh4+cjEveUcov+qinq8UEjY7q+4gK+6 hlE/RF4pfKK53gWnldX8EHR96bTQJ9B+d5khbKUlkEDPzBd2KcvmZCRORFxAsmwn0yQf kEaGlEVrQ8/5O0OAxU53wxNqS5agFGj2SulkItjaR5rrukcH16qIQWany+A7k7/ODXqV pBiVYOo+1KUuDuHA9WiQ2w9YxGyH5+9b1MUdMrnm3Kr2RkKOGGzHPXoBlvGgzf3xWLQB mIuA== X-Forwarded-Encrypted: i=1; AJvYcCUMBe0SMBOkgFu5tmThm+TctnIx2i5fL1y+rMBwNCEPMnZcNlVIeG4zrvNayFdhgPBxeziORajbjbqA8Kc=@vger.kernel.org X-Gm-Message-State: AOJu0YyWtM/FUeR2keHgfwDDUPNaTAKrDuXBy0pBoHpM+1ASyNKJYvOX 68+y8AGVmCynpxYXED4tZaUNIT+81xzokZvTwSlDtfFZxzg0VlUrWXKK X-Gm-Gg: ASbGncv0sPau6mWirj7S56kXEzLYpzHb95yN3UNSxIx1GKGIKQG+u7i3tmgPUMEHs1h 8alrAudbCbNGWnCCBlhpqKOmM/11ZAlHhbN+yMUjPuL27WWycYI9mkk/ObAwVzsTMY2hDsJTZXN Ymko9RC0TMvVjwx5988jMuNI7iyq2gZTh2JKsxYUdfsRAl7sv/xOVVA0mM74iARZNGjwF3SNnCl hwy/lZ3QC4qfucIQqsOTqRNBW4T+KgOLBWly/SY+z7TkbMjSm2cpTprTkkf7A+6btT1XgIYn8pY KRtNsQtvxTTGeGCO9ZJeg5DQtJrQ7mfzGVJRZcyvY5PquOHfNiKljzJ9DQm5rlD7OQipce6ApAh JB9YzASQGhW9wPN9EFf+JXtj5qbQuYTH4qNG+0PW/LHRXHPoJ3gKfV8lNUrsVrPxHQT0C4T/gfQ 5WF9NK4R1qsRHZHYxJCu7+hHaoRl5bHaoewPHShxucad2e/pVGfdlCvg== X-Google-Smtp-Source: AGHT+IEpYYe3gL2BsaA1HL6btRIHeyw309tXCm0NAEh0Lw3rFgKYmMUnXtp740D13O3MvOY049xzmQ== X-Received: by 2002:a05:600c:3551:b0:471:131f:85b7 with SMTP id 5b1f17b1804b1-477c10e2bc2mr418877175e9.15.1764551750742; Sun, 30 Nov 2025 17:15:50 -0800 (PST) Received: from alarm (92.40.200.0.threembb.co.uk. [92.40.200.0]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-479110b6da9sm216152305e9.0.2025.11.30.17.15.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Nov 2025 17:15:50 -0800 (PST) From: Dale Whinham To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: =?UTF-8?q?J=C3=A9r=C3=B4me=20de=20Bretagne?= , Dale Whinham , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/8] dt-bindings: arm: qcom: Document Microsoft Surface Pro 11 Date: Mon, 1 Dec 2025 01:14:42 +0000 Message-ID: <20251201011457.17422-2-daleyo@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251201011457.17422-1-daleyo@gmail.com> References: <20251201011457.17422-1-daleyo@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: J=C3=A9r=C3=B4me de Bretagne Add the compatible for the Qualcomm X1-based Microsoft Surface Pro 11, using its Denali codename. Signed-off-by: J=C3=A9r=C3=B4me de Bretagne Signed-off-by: Dale Whinham --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index 18b5ed044f9f..e35e7764dd8b 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1069,6 +1069,7 @@ properties: - hp,elitebook-ultra-g1q - hp,omnibook-x14 - lenovo,yoga-slim7x + - microsoft,denali - microsoft,romulus13 - microsoft,romulus15 - qcom,x1e80100-crd --=20 2.52.0 From nobody Mon Dec 1 22:35:40 2025 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F6B583A14 for ; Mon, 1 Dec 2025 01:15:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764551756; cv=none; b=XYhuBoC2MAyyrZCwmcJJ1p0lwg8wc8S3RQpiYqSb/ahUQmCw0YQJj+b+kmimvqsFgcIgEcc3zFkUpIYv1VCbMRSgpxekHx26hKcK0Ni3/y6Soah+qgBBLvSGEC/OA2rfNBYVHN5EGNBpykJISvFnm0P+hwuo+PrkW94rlUxenRE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764551756; c=relaxed/simple; bh=ymdj8iWQgXeJ9doGMASDK65eKURG2Ow4j7RDRnLK5bo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=beyD11ofUOWtNybnaKGGqQqYc7/SdyCGtOonI0yhHpftqkOTMBWGGgSwtnpuo+wCXmRmknBa5h6MJ2YZvrA+NhkCLNaMBfewbMk4Mhs5SAt3pcWDrBKsJ1lE494KVLLMGujakYudkv8Z1OFO2bcLv3FOqUXnLG1Kl0KCfcEhRUQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=XIwNDYyk; arc=none smtp.client-ip=209.85.128.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="XIwNDYyk" Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-477a219dbcaso31604565e9.3 for ; Sun, 30 Nov 2025 17:15:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1764551752; x=1765156552; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VSFp1WyHU0nZAFVKsmUn78bPo/8zi/N2062JdvrUp5k=; b=XIwNDYykcwwSvWTrPLPB5DrBELUAac+4MvMXLdJnOsBmvlq9PJ/wkY3pWTLp6m4We2 GGJV6XXvPY9mfpPHsjCY6SMibbYEQ2R8lEYv0LaVtOVGI28a/Euc4pXyUWL3zmZVvBMX gv4pbXcz02oO0x013kwLyEQw67N8GB+ZwMvTQyUMRlQ4kXvrjj+PiihoSftCjUz8riTj 3deGJVciAdoKk4EdfnGjUuG+xb51XnqIMod62iQQq8CsljhsYbbzoWKDrubVpXhcoIRS pvgc4nkFC7vIy6zxPdVBj/Maaz33e5E3mwI/HzZaI7Hp6KY5+UW4h0WuaO/NfGQtB/Cr w+NQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764551752; x=1765156552; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=VSFp1WyHU0nZAFVKsmUn78bPo/8zi/N2062JdvrUp5k=; b=T9fEvpN9wdBzog/cdL4L+yL1aLSCIhJOykjz/K02ic+DOreLk/LwckgftQdOQ1bn0M 0xwT2uJaaloF5lJpSdF0iKm0hdQlcARMqC5FsoRhNIfmwX3X7L2LG710p55ZviAZcDde KsguAE2/DBtqSUpVcbxkCEyl3ZD8533dVVjzHTs2nhcdvQUCliYvhO46LmJBU7sTXzBT 4G9JGuuo60pEtU1Ho3QoMA16Oyvq7R5Rg/cMUsZ5EOuMpaZoQkRtQPGXx1YcxMFcpYm6 8J6hFEdR0CoIC8tUSpXLCsKgH2G3qMdE3Hqut7WsF/VxJj19sa5dSipdsMw59lOJ6Jr2 aI5A== X-Forwarded-Encrypted: i=1; AJvYcCVydy/pEQV4P7elYWsX9ausgt0WO9Kc0/S0fi9+Dj6fNPMm//AMs7tXWEmCJyM0fF4WpfeddK9cqrCnIHY=@vger.kernel.org X-Gm-Message-State: AOJu0YyM/US/asq82eMxHLKr4DrkJHwXdOlnsHYKTLHdc+ERVHikl1xg Imr+wVn6QaW+P3o1xxhXX37FbiYMEgI5jeJwD7vQDFCnBfciTAZCu8Ws X-Gm-Gg: ASbGnct/OAnfu3mkJnlmwHSdPWft5EDgZDSXXWjR8ueWk/ks/EP/T//7EJv0eXJhMOH dk9LuggR4WEo1byPPZhV9FkNA/R8E7YuN65uSFpzkEBidrG1yikig15vg44Y6OOfQ2XXb3ZSxVH G0qybfC2tFRDSzMeRqHy8zNaZ6MuPHtqVq1/5jTb2v9axl4KiVQhqAFeDXrUKYdkuFRNxxbFbey 919/zRnwB1PYcovZAKn3ql2MyspejZk6tKqooS5QOQBDrQzkhrmJRel8nElPgzX8349AZHY2tf2 2iPwrrxQXiePGds1TrzvAk2wwKriQ+9CypMrYbsZzWyxIfhZuF9Im+rBxTYncShjOhEzOYqYklO N3J5oK2Nho9TEVWjGLcOVYNLtHrAHkkR98Qd1UKyrfUwh8PBbe1722nd0DJ4Lz5PqTpNp3/Q39B UxVycXtG8ETf2kv7lP+xmKLSC91VuL0cNy6MQoNnKvDwkRtq/EHqupkA== X-Google-Smtp-Source: AGHT+IHt1vGUsA7Svez/JxKX7EhEA/6WSnSYAf54Ktb8Xzx5CAPEEKocZCZzK5dSnv6h/Fl+2Vf6Iw== X-Received: by 2002:a05:600c:358f:b0:479:1ac2:f9b8 with SMTP id 5b1f17b1804b1-4791ac2fa2emr78862555e9.21.1764551751787; Sun, 30 Nov 2025 17:15:51 -0800 (PST) Received: from alarm (92.40.200.0.threembb.co.uk. [92.40.200.0]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-479110b6da9sm216152305e9.0.2025.11.30.17.15.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Nov 2025 17:15:51 -0800 (PST) From: Dale Whinham To: Bjorn Andersson , Konrad Dybcio Cc: =?UTF-8?q?J=C3=A9r=C3=B4me=20de=20Bretagne?= , Dale Whinham , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/8] firmware: qcom: scm: allow QSEECOM on Surface Pro 11 Date: Mon, 1 Dec 2025 01:14:43 +0000 Message-ID: <20251201011457.17422-3-daleyo@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251201011457.17422-1-daleyo@gmail.com> References: <20251201011457.17422-1-daleyo@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Enables access to EFI variables on this machine. Tested-by: J=C3=A9r=C3=B4me de Bretagne Signed-off-by: Dale Whinham --- drivers/firmware/qcom/qcom_scm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_= scm.c index e777b7cb9b12..5d123c11d8ed 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -2007,6 +2007,7 @@ static const struct of_device_id qcom_scm_qseecom_all= owlist[] __maybe_unused =3D { { .compatible =3D "lenovo,yoga-slim7x" }, { .compatible =3D "microsoft,arcata", }, { .compatible =3D "microsoft,blackrock" }, + { .compatible =3D "microsoft,denali", }, { .compatible =3D "microsoft,romulus13", }, { .compatible =3D "microsoft,romulus15", }, { .compatible =3D "qcom,hamoa-iot-evk" }, --=20 2.52.0 From nobody Mon Dec 1 22:35:40 2025 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E01E214F9FB for ; Mon, 1 Dec 2025 01:15:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764551756; cv=none; b=kM01NLDj4bdFynNL+zZseRfbMvuD8Ce84IfgNZ6qeJs8L5Yc+wUqnyFgekDq1OVJsXQxB+lzsyTzkrX64GEIhOMcwMX/+FCeEGw2+2wRuXuAPHqXtJBurnWQoDE2tft567v2nVt/81wGUcaKLNd5SvzKrhwG6MPDyOQO5NgC8RM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764551756; c=relaxed/simple; bh=fpUkE9ULX/qiNIgm+freNtTLYgz8I2UojpJ1nQJV6z8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=QAqvTpMz9hhhzpCBVNsu5jeAjaWEHy+kt96VRV+OXtwsp/Km5eNIQ+qq/TO/3qzodTyG9rgcG51sPGasDU1WYQkqTI/U/po/TsUyJWzRIW6zkJWBD+etSRg27yJTcZI/nZWcYYzaQjPuNRBycbvjUz7cjAnIe5j4rtcREoqLgBg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=nsYtRkj4; arc=none smtp.client-ip=209.85.128.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="nsYtRkj4" Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-47755de027eso23543295e9.0 for ; Sun, 30 Nov 2025 17:15:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1764551753; x=1765156553; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cNWknMZFPXFAx6SymlKZ6NLCFxgnUo2lmZCpszapuiQ=; b=nsYtRkj4TBqTWJy0q3uR0ws1iSw7sakhmExtBLL3TM7FA71aVyab5XvOrHuc9znkuf uefovE1Kc2XEw2LWCRHA1G582TDh/eoAmWUzSERElyAD1EPZH6X4lulY9fjTUH72hmv+ SnLNwc4ZcarDXKfOzn5OCSvYrD5dwvkwSTdNTbk781TFf0oQ8PpQlnZcrzSxX2DbXBnT 3fGAinKN/SV6m++ZPPa1w9Sug8QWH3AE1Qtgh5aTo8wxWjCGs9Uf2Z1FEys/CJlIhAet vDo5w++p0eXqy7WtFAGafGfFzwsIH9fc3pBCZBDm5Ea09coxZbR2rSoK04b3zJPbSXog 3r+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764551753; x=1765156553; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=cNWknMZFPXFAx6SymlKZ6NLCFxgnUo2lmZCpszapuiQ=; b=SNoX16JyuG9Wnk5S60/yPtGHvZAHVL8evpB/e3H2yiMK1YBWEGrta3BkcwN07VK3ez JnY1HQqqERzxXR4OwihbyXYclCVF5GPURRHn/WPJ7D6gwy7veMpVG1363B/0uLdJTqSQ GeCQdsFTzdL/lohEVxSKc+jEKDuI0/qXCfo/h8/SMB2UIJB2JKo9Zpl+eUd/efpbKXbD 4KFJG8FxzpS796G0X7EwLLiYRkjJOaO43W6x0Lo+kaxGzhJwq0qARnHLOMd0zrhHvaNX T5KP4Fp+JI3m0kqNvI9W9xyR/y6nmOk9Pq0uEuZSOJQWLLudr87Q4mBVhW3hLkZuzYlA 4OIQ== X-Forwarded-Encrypted: i=1; AJvYcCUhUkWDD+8mAsgf0puAoQzgDeUK2r+3IOkgEiXDnPsjTAKNRIO+tMgvN0kn/dVRjgM7Ftx5z/pOIo2jv9s=@vger.kernel.org X-Gm-Message-State: AOJu0YzLupKaw7DG3c9h5Cjy57CzjRzvBQYMVVkG7ihN7CO+P6/8DFL5 BAQAxN9MlgDHY/9WP2sv2GwoIdoZ0he2xvvSW0mxiHfZkzO0QYq+V6tC X-Gm-Gg: ASbGncshEO4MNgHLcJaGyDQ0tYxZWabAwZUL32aHXSYVsqnZ32DeIzk8TQqDDniZ8IR mLSIoN+peNjHlZqcOqD/LW695frlsD80JBa1WNT+RcPqON46CAyiB5swyOyKwkdIkrC7oM4ZG+e hMoGDWL/Ipo+TN3AHdCOl/sS1PvOswdMkW+INvFNFxHK+j643SfaW/MrCwXPCj1lb3TuefpeXTJ /aZF4orydPYFFXVLqdI1/IuSzyCiQZLV60oeDxUM193d2YK4fYha2xs5DZBHUXEcSI413cIknTc DavATE8ya3QjbXRSQgOr5j8eqFEW9JU5Ki0o+yN2EIJuGJ1Xa8SZc0ovHsbp68LjUPnSGITjgDb 6+ULX7p2ZG/lAmi5KF9nLWN9HOjK2yqcsufD8FUA12I/CD7lTwOt3WHwoGKROMPRxZPtBy1OB6h kG/LzzDZHTIpzvOH2t2hZ7ceY9EGzhXIi9JJO4n2b2ResUy6g55/d7rg== X-Google-Smtp-Source: AGHT+IFdfAWMgKy7dIfy8+I+uS0Vi7nXIKnPE4HKi08R8Rbs2lfgQtD0jd9Zh7ZgArMkeFo1j1T/FA== X-Received: by 2002:a05:600c:3b9f:b0:477:8985:4036 with SMTP id 5b1f17b1804b1-47904acef58mr277229905e9.1.1764551752934; Sun, 30 Nov 2025 17:15:52 -0800 (PST) Received: from alarm (92.40.200.0.threembb.co.uk. [92.40.200.0]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-479110b6da9sm216152305e9.0.2025.11.30.17.15.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Nov 2025 17:15:52 -0800 (PST) From: Dale Whinham To: Maximilian Luz , Hans de Goede , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Cc: =?UTF-8?q?J=C3=A9r=C3=B4me=20de=20Bretagne?= , Dale Whinham , platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/8] platform/surface: aggregator_registry: Add Surface Pro 11 Date: Mon, 1 Dec 2025 01:14:44 +0000 Message-ID: <20251201011457.17422-4-daleyo@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251201011457.17422-1-daleyo@gmail.com> References: <20251201011457.17422-1-daleyo@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable This enables support for the X1E-based Surface Pro 11. Tested-by: J=C3=A9r=C3=B4me de Bretagne Signed-off-by: Dale Whinham --- .../surface/surface_aggregator_registry.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/platform/surface/surface_aggregator_registry.c b/drive= rs/platform/surface/surface_aggregator_registry.c index a594d5fcfcfd..e08d029e0856 100644 --- a/drivers/platform/surface/surface_aggregator_registry.c +++ b/drivers/platform/surface/surface_aggregator_registry.c @@ -406,6 +406,22 @@ static const struct software_node *ssam_node_group_sp9= _5g[] =3D { NULL, }; =20 +/* Devices for Surface Pro 11 (ARM/QCOM) */ +static const struct software_node *ssam_node_group_sp11[] =3D { + &ssam_node_root, + &ssam_node_hub_kip, + &ssam_node_bat_ac, + &ssam_node_bat_main, + &ssam_node_tmp_sensors, + &ssam_node_hid_kip_keyboard, + &ssam_node_hid_kip_penstash, + &ssam_node_hid_kip_touchpad, + &ssam_node_hid_kip_fwupd, + &ssam_node_hid_sam_sensors, + &ssam_node_kip_tablet_switch, + NULL, +}; + /* -- SSAM platform/meta-hub driver. -------------------------------------= --- */ =20 static const struct acpi_device_id ssam_platform_hub_acpi_match[] =3D { @@ -485,6 +501,8 @@ static const struct of_device_id ssam_platform_hub_of_m= atch[] __maybe_unused =3D { /* Surface Laptop 7 */ { .compatible =3D "microsoft,romulus13", (void *)ssam_node_group_sl7 }, { .compatible =3D "microsoft,romulus15", (void *)ssam_node_group_sl7 }, + /* Surface Pro 11 */ + { .compatible =3D "microsoft,denali", (void *)ssam_node_group_sp11 }, { }, }; =20 --=20 2.52.0 From nobody Mon Dec 1 22:35:40 2025 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 383B91A0BD6 for ; Mon, 1 Dec 2025 01:15:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764551760; cv=none; b=ghkV1aZa/ZWERt+bINdxiYZbKYFVFkF1Xc04pEidzh+8LGa5o/QD7rvy1MaSQ+HbNrC2yq59Bc/djQhT1Hw/FdEyLoho1GFJr+V5ym5ueEm5PMjAxHrjX1FUmDos7DNaI7DayiCgnQhoNspIjfDFrnYzZZ3LhWNgKBKYQJPx/qM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764551760; c=relaxed/simple; bh=IRggN3lmtuL1+sRl7lfs+N472nG3VqsOqQtqcI6fI1I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=S2jlEWgkcS+CcMcdVqeuBITDlAAs1+bdhZUaUidXi8B4YrNU/i85ZfkigEX0GkRKguNa6TD8pmnSjQlVwsp0TKdrjydIoL4y9RH47D6FfDui4OZBWuZXrKZbrJmdqBDCdk1UDmV01W9N5bsV7N4ZGsc5SXLdN+wjhonoHj4ZUlQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=YB7dHId5; arc=none smtp.client-ip=209.85.128.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="YB7dHId5" Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-477632b0621so21286025e9.2 for ; Sun, 30 Nov 2025 17:15:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1764551755; x=1765156555; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=caWS6hPO4Twt32QiX0Ivthekj2EdbIJLrCvPNIpwXHU=; b=YB7dHId5c2L/m4gcabJCjaOz7qt33PZi07+6m7ucpj/pXE/4wmREMpA+Yu/j9sAnRP kFq37apsSwpxKziId/WKqNk0Gk9e6V25lpCmgN8kYIot6SbRPGFT1eCC60FVzNGuC/w5 8WPi9Y5U2/CAh2cIoUh7GnA+Piz+JbRmM+o2EjuJx6PwLjQiOYkvLOROZnsniu5yww4+ Ykgo7wyjkB5895TPD9wFemZaIT1VFgwmuQ2hPIDDnmpkMav89tkLde2UQ7EguXZYtsg0 azt5m4ei1IfttLhfcB+QDWE366FZOo42PVUbFaGFal3D5av+zhfYghA0TTi7xWWxDBy+ HCvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764551755; x=1765156555; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=caWS6hPO4Twt32QiX0Ivthekj2EdbIJLrCvPNIpwXHU=; b=HPrirUsRIaiZJVOfDlDm4iLDHBXZVenWo03aJBcOw/eodL8kXF3lkjXqbhC9avGV4u GYsurhptFMJDyv4erFGj80BASl80osCujS5BVfN9vkwnJ7rpp3NN4qo+qW/wQ5PGQlUU K7To2jHGPlSl8Uod2hFbGR40G4kgLQ/DgSNpvN4HSAXry8ne45o82VdVsXCcLJsqSNUK QfA00mo7qsML9RCpXXTdPIIExHzwU1wOx4tlJ5ERtcKEq9lQxg+14f9eB1n+cVNxbx77 3GsrK1ceEqhsgatrcXB6BF5iveWpfNKKWbaUQ4C5z8BKj211U4aQx4wNNykRzLBftB1O z9cQ== X-Forwarded-Encrypted: i=1; AJvYcCX4TPz8AXumm6hrZCcxH/yLOZKMlNO8g7NI+VzCOnda7KtvI18DcQpksbo4B992fHcTgTRoyei2Gf3HNv8=@vger.kernel.org X-Gm-Message-State: AOJu0YxfAGRf0pOWpDXZm/Tcls2H1SDpbPq241Ke3uBGCDHWVvi2Rki1 P33oMI16f7QEq0M+mnBXVNSlu7P8nO5vR3xkTRlUNhvGS0xIVn/HFtko X-Gm-Gg: ASbGnctDS0xr+5tbRSM9P5+dqVbYxrL7dGYzlH8on5n6vLvM593Ty4yYbJzPYbXt6H9 gp6RHUqPr892numiUk0AknCyyhdig0jB7CmzJijimuRbmNXNkIyh3rK5JZUlP3j/vPD/xC00ulV xsrPNFA4I/kFHLDCDmJUiv/f7v8et5NR3ZMdNIa4Un6nkAX2HqIGhzvKyWxFVph+ocxOyVsFa3B W2g5Sz/8bE7S/FD7Z6tC1vfT2+fdjMQ+gvFcxuOhax4ERrJHpTcbb6NKJmJROhgKAhB3xbQN0Wa EEgsDBX3wOr2Jryb0KQLiLDaJb24vZCSdjkykMXyqUxmbvUaWloqLDNKJ/v7SF91vXXfchlfyID b/Q/MFt/isgd9Chcw48e6LHLDEfi2JDijTf7Rw+Eno24xuebCXNmW+BTwL/IvsR6yPSrDbERuPd U5yaT5A9gT7KYhb7poTgJppQzF3HQYHD/8JNMxGiXGbwF49Ys1fCvSvQ== X-Google-Smtp-Source: AGHT+IHEW3Rds/1KMTMF2j8T5zYO4ugi7BR6V2zJhUiHqId4d56QcNhq/Vr3IbhqYQtytyHF6ksGVg== X-Received: by 2002:a05:600c:4ec7:b0:477:9b4a:a82 with SMTP id 5b1f17b1804b1-477c1138445mr357584795e9.35.1764551755281; Sun, 30 Nov 2025 17:15:55 -0800 (PST) Received: from alarm (92.40.200.0.threembb.co.uk. [92.40.200.0]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-479110b6da9sm216152305e9.0.2025.11.30.17.15.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Nov 2025 17:15:54 -0800 (PST) From: Dale Whinham To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: =?UTF-8?q?J=C3=A9r=C3=B4me=20de=20Bretagne?= , Dale Whinham , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/8] arm64: dts: qcom: Add support for Surface Pro 11 Date: Mon, 1 Dec 2025 01:14:45 +0000 Message-ID: <20251201011457.17422-5-daleyo@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251201011457.17422-1-daleyo@gmail.com> References: <20251201011457.17422-1-daleyo@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Add device trees for the Qualcomm X1E and X1P-based Microsoft Surface Pro 11 machines (codenamed 'Denali'). This device is very similar to the Surface Laptop 7 ('Romulus'). Use a similar strategy to x1-asus-zenbook-a14.dtsi so that we can create x1e and x1p-specific flavors of the device tree without too much code duplication. Hardware support is similar to other X1E machines. The most notable features missing are: - Touchscreen and pen - Cameras (and status LEDs) Tested-by: J=C3=A9r=C3=B4me de Bretagne Signed-off-by: Dale Whinham --- arch/arm64/boot/dts/qcom/Makefile | 4 + .../boot/dts/qcom/x1-microsoft-denali.dtsi | 1338 +++++++++++++++++ .../qcom/x1e80100-microsoft-denali-oled.dts | 20 + .../dts/qcom/x1p64100-microsoft-denali.dts | 16 + 4 files changed, 1378 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi create mode 100644 arch/arm64/boot/dts/qcom/x1e80100-microsoft-denali-oled= .dts create mode 100644 arch/arm64/boot/dts/qcom/x1p64100-microsoft-denali.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 296688f7cb26..fe2054ee093e 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -336,6 +336,8 @@ x1e80100-hp-omnibook-x14-el2-dtbs :=3D x1e80100-hp-omni= book-x14.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) +=3D x1e80100-hp-omnibook-x14.dtb x1e80100-hp-omni= book-x14-el2.dtb x1e80100-lenovo-yoga-slim7x-el2-dtbs :=3D x1e80100-lenovo-yoga-slim7x.dtb = x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) +=3D x1e80100-lenovo-yoga-slim7x.dtb x1e80100-leno= vo-yoga-slim7x-el2.dtb +x1e80100-microsoft-denali-oled-el2-dtbs :=3D x1e80100-microsoft-denali-ole= d.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) +=3D x1e80100-microsoft-denali-oled.dtb x1e80100-m= icrosoft-denali-oled-el2.dtb x1e80100-microsoft-romulus13-el2-dtbs :=3D x1e80100-microsoft-romulus13.dt= b x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) +=3D x1e80100-microsoft-romulus13.dtb x1e80100-mic= rosoft-romulus13-el2.dtb x1e80100-microsoft-romulus15-el2-dtbs :=3D x1e80100-microsoft-romulus15.dt= b x1-el2.dtbo @@ -350,3 +352,5 @@ x1p42100-hp-omnibook-x14-el2-dtbs :=3D x1p42100-hp-omni= book-x14.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) +=3D x1p42100-hp-omnibook-x14.dtb x1p42100-hp-omni= book-x14-el2.dtb x1p42100-lenovo-thinkbook-16-el2-dtbs :=3D x1p42100-lenovo-thinkbook-16.dt= b x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) +=3D x1p42100-lenovo-thinkbook-16.dtb x1p42100-len= ovo-thinkbook-16-el2.dtb +x1p64100-microsoft-denali-el2-dtbs :=3D x1p64100-microsoft-denali.dtb x1-e= l2.dtbo +dtb-$(CONFIG_ARCH_QCOM) +=3D x1p64100-microsoft-denali.dtb x1p64100-micros= oft-denali-el2.dtb diff --git a/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi b/arch/arm64= /boot/dts/qcom/x1-microsoft-denali.dtsi new file mode 100644 index 000000000000..64eabe2b96cf --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi @@ -0,0 +1,1338 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2025 Dale Whinham + */ + +#include +#include +#include +#include + +#include "x1e80100-pmics.dtsi" + +/ { + aliases { + serial0 =3D &uart2; + serial1 =3D &uart14; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + + pinctrl-0 =3D <&hall_int_n_default>; + pinctrl-names =3D "default"; + + switch-lid { + gpios =3D <&tlmm 2 GPIO_ACTIVE_LOW>; + linux,input-type =3D ; + linux,code =3D ; + wakeup-source; + wakeup-event-action =3D ; + }; + }; + + pmic-glink { + compatible =3D "qcom,x1e80100-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells =3D <1>; + #size-cells =3D <0>; + orientation-gpios =3D <&tlmm 121 GPIO_ACTIVE_HIGH>, + <&tlmm 123 GPIO_ACTIVE_HIGH>; + + /* Left-side rear port */ + connector@0 { + compatible =3D "usb-c-connector"; + reg =3D <0>; + power-role =3D "dual"; + data-role =3D "dual"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + pmic_glink_ss0_hs_in: endpoint { + remote-endpoint =3D <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg =3D <1>; + + pmic_glink_ss0_ss_in: endpoint { + remote-endpoint =3D <&retimer_ss0_ss_out>; + }; + }; + + port@2 { + reg =3D <2>; + + pmic_glink_ss0_con_sbu_in: endpoint { + remote-endpoint =3D <&retimer_ss0_con_sbu_out>; + }; + }; + }; + }; + + /* Left-side front port */ + connector@1 { + compatible =3D "usb-c-connector"; + reg =3D <1>; + power-role =3D "dual"; + data-role =3D "dual"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + pmic_glink_ss1_hs_in: endpoint { + remote-endpoint =3D <&usb_1_ss1_dwc3_hs>; + }; + }; + + port@1 { + reg =3D <1>; + + pmic_glink_ss1_ss_in: endpoint { + remote-endpoint =3D <&retimer_ss1_ss_out>; + }; + }; + + port@2 { + reg =3D <2>; + + pmic_glink_ss1_con_sbu_in: endpoint { + remote-endpoint =3D <&retimer_ss1_con_sbu_out>; + }; + }; + }; + }; + }; + + reserved-memory { + linux,cma { + compatible =3D "shared-dma-pool"; + size =3D <0x0 0x8000000>; + reusable; + linux,cma-default; + }; + }; + + vreg_edp_3p3: regulator-edp-3p3 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_EDP_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&edp_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_1p15: regulator-rtmr0-1p15 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR0_1P15"; + + regulator-min-microvolt =3D <1150000>; + regulator-max-microvolt =3D <1150000>; + + gpio =3D <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&rtmr0_1p15_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_1p8: regulator-rtmr0-1p8 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR0_1P8"; + + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + gpio =3D <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&rtmr0_1p8_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_3p3: regulator-rtmr0-3p3 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR0_3P3"; + + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&rtmr0_3p3_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p15: regulator-rtmr1-1p15 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR1_1P15"; + + regulator-min-microvolt =3D <1150000>; + regulator-max-microvolt =3D <1150000>; + + gpio =3D <&tlmm 188 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&rtmr1_1p15_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p8: regulator-rtmr1-1p8 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR1_1P8"; + + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + gpio =3D <&tlmm 175 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&rtmr1_1p8_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_3p3: regulator-rtmr1-3p3 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR1_3P3"; + + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&tlmm 186 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&rtmr1_3p3_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_nvme: regulator-nvme { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_NVME_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&tlmm 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&nvme_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vph_pwr: regulator-vph-pwr { + compatible =3D "regulator-fixed"; + + regulator-name =3D "vph_pwr"; + regulator-min-microvolt =3D <3700000>; + regulator-max-microvolt =3D <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_WCN_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&wcn_sw_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + /* + * TODO: These two regulators are actually part of the removable M.2 + * card and not the CRD mainboard. Need to describe this differently. + * Functionally it works correctly, because all we need to do is to + * turn on the actual 3.3V supply above. + */ + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_WCN_0P95"; + regulator-min-microvolt =3D <950000>; + regulator-max-microvolt =3D <950000>; + + vin-supply =3D <&vreg_wcn_3p3>; + }; + + vreg_wcn_1p9: regulator-wcn-1p9 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_WCN_1P9"; + regulator-min-microvolt =3D <1900000>; + regulator-max-microvolt =3D <1900000>; + + vin-supply =3D <&vreg_wcn_3p3>; + }; + + sound { + compatible =3D "qcom,x1e80100-sndcard"; + model =3D "X1E80100-Microsoft-Surface-Pro-11"; + audio-routing =3D "SpkrLeft IN", "WSA WSA_SPK1 OUT", + "SpkrRight IN", "WSA WSA_SPK2 OUT", + "VA DMIC0", "vdd-micb", + "VA DMIC1", "vdd-micb"; + + wsa-dai-link { + link-name =3D "WSA Playback"; + + cpu { + sound-dai =3D <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai =3D <&left_spkr>, <&right_spkr>, <&swr0 0>, <&lpass_wsamacro= 0>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + + va-dai-link { + link-name =3D "VA Capture"; + + cpu { + sound-dai =3D <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + codec { + sound-dai =3D <&lpass_vamacro 0>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + }; + + wcn7850-pmu { + compatible =3D "qcom,wcn7850-pmu"; + + vdd-supply =3D <&vreg_wcn_0p95>; + vddio-supply =3D <&vreg_l15b_1p8>; + vddaon-supply =3D <&vreg_wcn_0p95>; + vdddig-supply =3D <&vreg_wcn_0p95>; + vddrfa1p2-supply =3D <&vreg_wcn_1p9>; + vddrfa1p8-supply =3D <&vreg_wcn_1p9>; + + wlan-enable-gpios =3D <&tlmm 117 GPIO_ACTIVE_HIGH>; + bt-enable-gpios =3D <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-0 =3D <&wcn_wlan_bt_en>; + pinctrl-names =3D "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name =3D "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name =3D "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name =3D "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name =3D "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name =3D "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name =3D "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name =3D "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name =3D "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name =3D "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name =3D "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id =3D "b"; + + vdd-bob1-supply =3D <&vph_pwr>; + vdd-bob2-supply =3D <&vph_pwr>; + vdd-l1-l4-l10-supply =3D <&vreg_s4c_1p8>; + vdd-l2-l13-l14-supply =3D <&vreg_bob1>; + vdd-l5-l16-supply =3D <&vreg_bob1>; + vdd-l6-l7-supply =3D <&vreg_bob2>; + vdd-l8-l9-supply =3D <&vreg_bob1>; + vdd-l12-supply =3D <&vreg_s5j_1p2>; + vdd-l15-supply =3D <&vreg_s4c_1p8>; + vdd-l17-supply =3D <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name =3D "vreg_bob1"; + regulator-min-microvolt =3D <3008000>; + regulator-max-microvolt =3D <3960000>; + regulator-initial-mode =3D ; + }; + + vreg_bob2: bob2 { + regulator-name =3D "vreg_bob2"; + regulator-min-microvolt =3D <2504000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name =3D "vreg_l1b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name =3D "vreg_l2b_3p0"; + regulator-min-microvolt =3D <3072000>; + regulator-max-microvolt =3D <3072000>; + regulator-initial-mode =3D ; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name =3D "vreg_l4b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name =3D "vreg_l6b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2960000>; + regulator-initial-mode =3D ; + }; + + vreg_l8b_3p0: ldo8 { + regulator-name =3D "vreg_l8b_3p0"; + regulator-min-microvolt =3D <3072000>; + regulator-max-microvolt =3D <3072000>; + regulator-initial-mode =3D ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name =3D "vreg_l9b_2p9"; + regulator-min-microvolt =3D <2960000>; + regulator-max-microvolt =3D <2960000>; + regulator-initial-mode =3D ; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name =3D "vreg_l10b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l12b_1p2: ldo12 { + regulator-name =3D "vreg_l12b_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name =3D "vreg_l13b_3p0"; + regulator-min-microvolt =3D <3072000>; + regulator-max-microvolt =3D <3072000>; + regulator-initial-mode =3D ; + }; + + vreg_l14b_3p0: ldo14 { + regulator-name =3D "vreg_l14b_3p0"; + regulator-min-microvolt =3D <3072000>; + regulator-max-microvolt =3D <3072000>; + regulator-initial-mode =3D ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name =3D "vreg_l15b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name =3D "vreg_l17b_2p5"; + regulator-min-microvolt =3D <2504000>; + regulator-max-microvolt =3D <2504000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-1 { + compatible =3D "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id =3D "c"; + + vdd-l1-supply =3D <&vreg_s5j_1p2>; + vdd-l2-supply =3D <&vreg_s1f_0p7>; + vdd-l3-supply =3D <&vreg_s1f_0p7>; + vdd-s4-supply =3D <&vph_pwr>; + + vreg_s4c_1p8: smps4 { + regulator-name =3D "vreg_s4c_1p8"; + regulator-min-microvolt =3D <1856000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + }; + + vreg_l1c_1p2: ldo1 { + regulator-name =3D "vreg_l1c_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_l2c_0p8: ldo2 { + regulator-name =3D "vreg_l2c_0p8"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <880000>; + regulator-initial-mode =3D ; + }; + + vreg_l3c_0p8: ldo3 { + regulator-name =3D "vreg_l3c_0p8"; + regulator-min-microvolt =3D <912000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-2 { + compatible =3D "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id =3D "d"; + + vdd-l1-supply =3D <&vreg_s1f_0p7>; + vdd-l2-supply =3D <&vreg_s1f_0p7>; + vdd-l3-supply =3D <&vreg_s4c_1p8>; + vdd-s1-supply =3D <&vph_pwr>; + + vreg_l1d_0p8: ldo1 { + regulator-name =3D "vreg_l1d_0p8"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <880000>; + regulator-initial-mode =3D ; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name =3D "vreg_l2d_0p9"; + regulator-min-microvolt =3D <912000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + }; + + vreg_l3d_1p8: ldo3 { + regulator-name =3D "vreg_l3d_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-3 { + compatible =3D "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id =3D "e"; + + vdd-l2-supply =3D <&vreg_s1f_0p7>; + vdd-l3-supply =3D <&vreg_s5j_1p2>; + + vreg_l2e_0p8: ldo2 { + regulator-name =3D "vreg_l2e_0p8"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <880000>; + regulator-initial-mode =3D ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name =3D "vreg_l3e_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-4 { + compatible =3D "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id =3D "f"; + + vdd-l1-supply =3D <&vreg_s5j_1p2>; + vdd-l2-supply =3D <&vreg_s5j_1p2>; + vdd-l3-supply =3D <&vreg_s5j_1p2>; + vdd-s1-supply =3D <&vph_pwr>; + + vreg_s1f_0p7: smps1 { + regulator-name =3D "vreg_s1f_0p7"; + regulator-min-microvolt =3D <700000>; + regulator-max-microvolt =3D <1100000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-6 { + compatible =3D "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id =3D "i"; + + vdd-l1-supply =3D <&vreg_s4c_1p8>; + vdd-l2-supply =3D <&vreg_s5j_1p2>; + vdd-l3-supply =3D <&vreg_s1f_0p7>; + vdd-s1-supply =3D <&vph_pwr>; + vdd-s2-supply =3D <&vph_pwr>; + + vreg_s1i_0p9: smps1 { + regulator-name =3D "vreg_s1i_0p9"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + }; + + vreg_s2i_1p0: smps2 { + regulator-name =3D "vreg_s2i_1p0"; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1100000>; + regulator-initial-mode =3D ; + }; + + vreg_l1i_1p8: ldo1 { + regulator-name =3D "vreg_l1i_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name =3D "vreg_l2i_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_l3i_0p8: ldo3 { + regulator-name =3D "vreg_l3i_0p8"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <880000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-7 { + compatible =3D "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id =3D "j"; + + vdd-l1-supply =3D <&vreg_s1f_0p7>; + vdd-l2-supply =3D <&vreg_s5j_1p2>; + vdd-l3-supply =3D <&vreg_s1f_0p7>; + vdd-s5-supply =3D <&vph_pwr>; + + vreg_s5j_1p2: smps5 { + regulator-name =3D "vreg_s5j_1p2"; + regulator-min-microvolt =3D <1256000>; + regulator-max-microvolt =3D <1304000>; + regulator-initial-mode =3D ; + }; + + vreg_l1j_0p8: ldo1 { + regulator-name =3D "vreg_l1j_0p8"; + regulator-min-microvolt =3D <912000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + }; + + vreg_l2j_1p2: ldo2 { + regulator-name =3D "vreg_l2j_1p2"; + regulator-min-microvolt =3D <1256000>; + regulator-max-microvolt =3D <1256000>; + regulator-initial-mode =3D ; + }; + + vreg_l3j_0p8: ldo3 { + regulator-name =3D "vreg_l3j_0p8"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <880000>; + regulator-initial-mode =3D ; + }; + }; +}; + +&gpu { + status =3D "okay"; + + zap-shader { + memory-region =3D <&gpu_microcode_mem>; + firmware-name =3D "qcom/x1e80100/microsoft/qcdxkmsuc8380.mbn"; + }; +}; + +&i2c0 { + clock-frequency =3D <400000>; + + status =3D "disabled"; +}; + +&i2c3 { + clock-frequency =3D <400000>; + + status =3D "okay"; + + /* Left-side rear port */ + typec-mux@8 { + compatible =3D "parade,ps8830"; + reg =3D <0x8>; + + reset-gpios =3D <&pm8550_gpios 10 GPIO_ACTIVE_LOW>; + + clocks =3D <&rpmhcc RPMH_RF_CLK3>; + + vdd-supply =3D <&vreg_rtmr0_1p15>; + vdd33-supply =3D <&vreg_rtmr0_3p3>; + vdd33-cap-supply =3D <&vreg_rtmr0_3p3>; + vddar-supply =3D <&vreg_rtmr0_1p15>; + vddat-supply =3D <&vreg_rtmr0_1p15>; + vddio-supply =3D <&vreg_rtmr0_1p8>; + + pinctrl-0 =3D <&rtmr0_default>; + pinctrl-names =3D "default"; + + retimer-switch; + orientation-switch; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + retimer_ss0_ss_out: endpoint { + remote-endpoint =3D <&pmic_glink_ss0_ss_in>; + }; + }; + + port@1 { + reg =3D <1>; + + retimer_ss0_ss_in: endpoint { + remote-endpoint =3D <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg =3D <2>; + + retimer_ss0_con_sbu_out: endpoint { + remote-endpoint =3D <&pmic_glink_ss0_con_sbu_in>; + }; + }; + }; + }; +}; + +&i2c4 { + clock-frequency =3D <400000>; + + status =3D "disabled"; +}; + +&i2c5 { + clock-frequency =3D <400000>; + + status =3D "disabled"; +}; + +&i2c7 { + clock-frequency =3D <400000>; + + status =3D "okay"; + + /* Left-side front port */ + typec-mux@8 { + compatible =3D "parade,ps8830"; + reg =3D <0x8>; + + reset-gpios =3D <&tlmm 176 GPIO_ACTIVE_LOW>; + + clocks =3D <&rpmhcc RPMH_RF_CLK4>; + + vdd-supply =3D <&vreg_rtmr1_1p15>; + vdd33-supply =3D <&vreg_rtmr1_3p3>; + vdd33-cap-supply =3D <&vreg_rtmr1_3p3>; + vddar-supply =3D <&vreg_rtmr1_1p15>; + vddat-supply =3D <&vreg_rtmr1_1p15>; + vddio-supply =3D <&vreg_rtmr1_1p8>; + + retimer-switch; + orientation-switch; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + retimer_ss1_ss_out: endpoint { + remote-endpoint =3D <&pmic_glink_ss1_ss_in>; + }; + }; + + port@1 { + reg =3D <1>; + + retimer_ss1_ss_in: endpoint { + remote-endpoint =3D <&usb_1_ss1_qmpphy_out>; + }; + }; + + port@2 { + reg =3D <2>; + + retimer_ss1_con_sbu_out: endpoint { + remote-endpoint =3D <&pmic_glink_ss1_con_sbu_in>; + }; + }; + }; + }; +}; + +&lpass_tlmm { + spkr_01_sd_n_active: spkr-01-sd-n-active-state { + pins =3D "gpio12"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + output-low; + }; + + spkr_23_sd_n_active: spkr-23-sd-n-active-state { + pins =3D "gpio13"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + output-low; + }; +}; + +&lpass_vamacro { + pinctrl-0 =3D <&dmic01_default>, <&dmic23_default>; + pinctrl-names =3D "default"; + + vdd-micb-supply =3D <&vreg_l1b_1p8>; + qcom,dmic-sample-rate =3D <4800000>; +}; + +&mdss { + status =3D "okay"; +}; + +&mdss_dp0 { + status =3D "okay"; +}; + +&mdss_dp0_out { + link-frequencies =3D /bits/ 64 <1620000000 2700000000 5400000000 81000000= 00>; +}; + +&mdss_dp1 { + status =3D "okay"; +}; + +&mdss_dp1_out { + link-frequencies =3D /bits/ 64 <1620000000 2700000000 5400000000 81000000= 00>; +}; + +&mdss_dp3 { + compatible =3D "qcom,x1e80100-dp"; + /delete-property/ #sound-dai-cells; + + status =3D "okay"; + + aux-bus { + panel: panel { + compatible =3D "edp-panel"; + enable-gpios =3D <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>; + power-supply =3D <&vreg_edp_3p3>; + + pinctrl-0 =3D <&edp_bl_en>; + pinctrl-names =3D "default"; + + port { + edp_panel_in: endpoint { + remote-endpoint =3D <&mdss_dp3_out>; + }; + }; + }; + }; + + ports { + port@1 { + reg =3D <1>; + + mdss_dp3_out: endpoint { + data-lanes =3D <0 1 2 3>; + link-frequencies =3D /bits/ 64 <1620000000 2700000000 5400000000 81000= 00000>; + + remote-endpoint =3D <&edp_panel_in>; + }; + }; + }; +}; + +&mdss_dp3_phy { + vdda-phy-supply =3D <&vreg_l3j_0p8>; + vdda-pll-supply =3D <&vreg_l2j_1p2>; + + status =3D "okay"; +}; + +&pcie4 { + status =3D "okay"; +}; + +&pcie4_phy { + vdda-phy-supply =3D <&vreg_l3i_0p8>; + vdda-pll-supply =3D <&vreg_l3e_1p2>; + + status =3D "okay"; +}; + +&pcie4_port0 { + wifi@0 { + compatible =3D "pci17cb,1107"; + reg =3D <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply =3D <&vreg_pmu_aon_0p59>; + vddwlcx-supply =3D <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply =3D <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply =3D <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply =3D <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply =3D <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply =3D <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply =3D <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply =3D <&vreg_pmu_pcie_1p8>; + }; +}; + +&pcie6a { + perst-gpios =3D <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 154 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply =3D <&vreg_nvme>; + + pinctrl-0 =3D <&pcie6a_default>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie6a_phy { + vdda-phy-supply =3D <&vreg_l1d_0p8>; + vdda-pll-supply =3D <&vreg_l2j_1p2>; + + status =3D "okay"; +}; + +&pm8550_gpios { + rtmr0_default: rtmr0-reset-n-active-state { + pins =3D "gpio10"; + function =3D "normal"; + power-source =3D <1>; /* 1.8V */ + }; + + rtmr0_3p3_reg_en: rtmr0-3p3-reg-en-state { + pins =3D "gpio11"; + function =3D "normal"; + power-source =3D <1>; /* 1.8V */ + }; +}; + +&pm8550ve_9_gpios { + rtmr0_1p8_reg_en: rtmr0-1p8-reg-en-state { + pins =3D "gpio8"; + function =3D "normal"; + power-source =3D <1>; /* 1.8V */ + }; +}; + +&pmc8380_3_gpios { + edp_bl_en: edp-bl-en-state { + pins =3D "gpio4"; + function =3D "normal"; + power-source =3D <1>; /* 1.8V */ + input-disable; + output-enable; + }; +}; + +&pmc8380_5_gpios { + rtmr0_1p15_reg_en: rtmr0-1p15-reg-en-state { + pins =3D "gpio8"; + function =3D "normal"; + power-source =3D <1>; /* 1.8V */ + }; +}; + +&qupv3_0 { + status =3D "okay"; +}; + +&qupv3_1 { + status =3D "okay"; +}; + +&qupv3_2 { + status =3D "okay"; +}; + +&remoteproc_adsp { + firmware-name =3D "qcom/x1e80100/microsoft/Denali/qcadsp8380.mbn", + "qcom/x1e80100/microsoft/Denali/adsp_dtb.mbn"; + + status =3D "okay"; +}; + +&remoteproc_cdsp { + firmware-name =3D "qcom/x1e80100/microsoft/Denali/qccdsp8380.mbn", + "qcom/x1e80100/microsoft/Denali/cdsp_dtb.mbn"; + + status =3D "okay"; +}; + +&smb2360_0 { + status =3D "okay"; +}; + +&smb2360_0_eusb2_repeater { + vdd18-supply =3D <&vreg_l3d_1p8>; + vdd3-supply =3D <&vreg_l2b_3p0>; +}; + +&smb2360_1 { + status =3D "okay"; +}; + +&smb2360_1_eusb2_repeater { + vdd18-supply =3D <&vreg_l3d_1p8>; + vdd3-supply =3D <&vreg_l14b_3p0>; +}; + +&smb2360_2 { + status =3D "okay"; +}; + +&smb2360_2_eusb2_repeater { + vdd18-supply =3D <&vreg_l3d_1p8>; + vdd3-supply =3D <&vreg_l8b_3p0>; +}; + +&swr0 { + status =3D "okay"; + + pinctrl-0 =3D <&wsa_swr_active>, <&spkr_01_sd_n_active>; + pinctrl-names =3D "default"; + + /* WSA8845, Left Speaker */ + left_spkr: speaker@0,0 { + compatible =3D "sdw20217020400"; + reg =3D <0 0>; + reset-gpios =3D <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "SpkrLeft"; + vdd-1p8-supply =3D <&vreg_l15b_1p8>; + vdd-io-supply =3D <&vreg_l12b_1p2>; + qcom,port-mapping =3D <1 2 3 7 10 13>; + }; + + /* WSA8845, Right Speaker */ + right_spkr: speaker@0,1 { + compatible =3D "sdw20217020400"; + reg =3D <0 1>; + reset-gpios =3D <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "SpkrRight"; + vdd-1p8-supply =3D <&vreg_l15b_1p8>; + vdd-io-supply =3D <&vreg_l12b_1p2>; + qcom,port-mapping =3D <4 5 6 7 11 13>; + }; +}; + +&tlmm { + gpio-reserved-ranges =3D <44 4>, /* SPI (TPM) */ + <238 1>; /* UFS Reset */ + + hall_int_n_default: hall-int-n-state { + pins =3D "gpio2"; + function =3D "gpio"; + bias-disable; + }; + + nvme_reg_en: nvme-reg-en-state { + pins =3D "gpio18"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + edp_reg_en: edp-reg-en-state { + pins =3D "gpio70"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + }; + + ssam_state: ssam-state-state { + pins =3D "gpio91"; + function =3D "gpio"; + bias-disable; + }; + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins =3D "gpio147"; + function =3D "pcie4_clk"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-n-pins { + pins =3D "gpio146"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + wake-n-pins { + pins =3D "gpio148"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + pcie6a_default: pcie6a-default-state { + perst-n-pins { + pins =3D "gpio152"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + clkreq-n-pins { + pins =3D "gpio153"; + function =3D "pcie6a_clk"; + drive-strength =3D <2>; + bias-pull-up; + }; + + wake-n-pins { + pins =3D "gpio154"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + rtmr1_1p8_reg_en: rtmr1-1p8-reg-en-state { + pins =3D "gpio175"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + rtmr1_3p3_reg_en: rtmr1-3p3-reg-en-state { + pins =3D "gpio186"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + rtmr1_1p15_reg_en: rtmr1-1p15-reg-en-state { + pins =3D "gpio188"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + cam_indicator_en: cam-indicator-en-state { + pins =3D "gpio225"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + wcn_sw_en: wcn-sw-en-state { + pins =3D "gpio214"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + wcn_wlan_bt_en: wcn-wlan-bt-en-state { + pins =3D "gpio116", "gpio117"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; +}; + +&uart2 { + status =3D "okay"; + + embedded-controller { + compatible =3D "microsoft,surface-sam"; + + interrupts-extended =3D <&tlmm 91 IRQ_TYPE_EDGE_RISING>; + + current-speed =3D <4000000>; + + pinctrl-0 =3D <&ssam_state>; + pinctrl-names =3D "default"; + }; +}; + +&uart14 { + status =3D "okay"; + + bluetooth { + compatible =3D "qcom,wcn7850-bt"; + max-speed =3D <3200000>; + + vddaon-supply =3D <&vreg_pmu_aon_0p59>; + vddwlcx-supply =3D <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply =3D <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply =3D <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply =3D <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply =3D <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply =3D <&vreg_pmu_rfa_1p8>; + }; +}; + +&usb_1_ss0_hsphy { + vdd-supply =3D <&vreg_l3j_0p8>; + vdda12-supply =3D <&vreg_l2j_1p2>; + + phys =3D <&smb2360_0_eusb2_repeater>; + + status =3D "okay"; +}; + +&usb_1_ss0_qmpphy { + vdda-phy-supply =3D <&vreg_l2j_1p2>; + vdda-pll-supply =3D <&vreg_l1j_0p8>; + + status =3D "okay"; +}; + +&usb_1_ss0 { + status =3D "okay"; +}; + +&usb_1_ss0_dwc3 { + dr_mode =3D "host"; +}; + +&usb_1_ss0_dwc3_hs { + remote-endpoint =3D <&pmic_glink_ss0_hs_in>; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint =3D <&retimer_ss0_ss_in>; +}; + +&usb_1_ss1_hsphy { + vdd-supply =3D <&vreg_l3j_0p8>; + vdda12-supply =3D <&vreg_l2j_1p2>; + + phys =3D <&smb2360_1_eusb2_repeater>; + + status =3D "okay"; +}; + +&usb_1_ss1_qmpphy { + vdda-phy-supply =3D <&vreg_l2j_1p2>; + vdda-pll-supply =3D <&vreg_l2d_0p9>; + + status =3D "okay"; +}; + +&usb_1_ss1 { + status =3D "okay"; +}; + +&usb_1_ss1_dwc3 { + dr_mode =3D "host"; +}; + +&usb_1_ss1_dwc3_hs { + remote-endpoint =3D <&pmic_glink_ss1_hs_in>; +}; + +&usb_1_ss1_qmpphy_out { + remote-endpoint =3D <&retimer_ss1_ss_in>; +}; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-denali-oled.dts b/= arch/arm64/boot/dts/qcom/x1e80100-microsoft-denali-oled.dts new file mode 100644 index 000000000000..f7159eef1d85 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-denali-oled.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2025 Dale Whinham + */ + +/dts-v1/; + +#include "x1e80100.dtsi" +#include "x1-microsoft-denali.dtsi" + +/ { + model =3D "Microsoft Surface Pro 11th Edition (OLED)"; + compatible =3D "microsoft,denali-oled", "microsoft,denali", + "qcom,x1e80100"; +}; + +&panel { + compatible =3D "samsung,atna30dw01", "samsung,atna33xc20"; +}; diff --git a/arch/arm64/boot/dts/qcom/x1p64100-microsoft-denali.dts b/arch/= arm64/boot/dts/qcom/x1p64100-microsoft-denali.dts new file mode 100644 index 000000000000..7c064ad49395 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1p64100-microsoft-denali.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2025 Dale Whinham + */ + +/dts-v1/; + +#include "x1e80100.dtsi" +#include "x1-microsoft-denali.dtsi" + +/ { + model =3D "Microsoft Surface Pro 11th Edition (LCD)"; + compatible =3D "microsoft,denali-lcd", "microsoft,denali", + "qcom,x1p64100", "qcom,x1e80100"; +}; --=20 2.52.0 From nobody Mon Dec 1 22:35:40 2025 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D34741A08DB for ; Mon, 1 Dec 2025 01:15:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764551760; cv=none; b=K56Yhy68LOHi5x2HddibKE12iEnMjeqwvgEYnqrDP55P/fXztzPMh0QOldjGHGxDeizSWFi78tiVuFoa/nHgN3gcZ0Fux3nIn8dFtgcMSyxQREZ1bDfyROTj3QRD+5CiHs7tVwLjW9D8nu4NGzYwDqLsToYJzLnOeW/sLDjHxjU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764551760; c=relaxed/simple; bh=WpXEEsGtOokvuvQlhuEmKMzc+nHK2ks6LTfaSKXNgvo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=d9l5ZGQiGXQq7V88obBrizylfQPfMqQrow34GEh2pxyas33f4yCszhcaNNmYNxqYNdpaKH36aI52Eh5h5FS8rusyotnBlPmmUCY4U+SXVFRXIJ9RAgv8sAqxpW9Ja71wVdXm7fRb9qQZz32D82mY5SuvVcuMduZR6ujaSM52XD8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=FGMkj8DI; arc=none smtp.client-ip=209.85.128.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="FGMkj8DI" Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-477770019e4so29002605e9.3 for ; Sun, 30 Nov 2025 17:15:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1764551757; x=1765156557; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=p+Y5hX1CqH3Pzk70YwUH5BikC9q1gOEENG1USkXY4XU=; b=FGMkj8DI3Q83wjp0741Qpe4hVMi+8FjRKWi8jms5YBlALLFDDgpRict9RYl2l0hsOm IvIsjUBOqtU5OXUAnJuByOB3lH3PsCvRhq5f7+tRsNFNHldMYs2CU0/qR2ywCSnaR+Yp b4V53JL/dF08kTEGdCaM4Xs26YDgJtj2t68prHllFdZ1slenQXH13dk9TV3lfcU2rN3h 7GbxY5jOC9BrDayZ6U5e51a+kIfu0VYrV+xl8kQ9B57Ukzc/GW5vRUUo1to5p29NIbBV xlGNf8Xdwvoni9OZgY1e+k0yj7P0TutfFulTQ8G9fbsD0xCkVj2PgLB2YGHJEt5PyLKF Ek0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764551757; x=1765156557; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=p+Y5hX1CqH3Pzk70YwUH5BikC9q1gOEENG1USkXY4XU=; b=BMFh1ZxS8CWPUPbUvYDqtGzw5VT5s6wemtJXLZc6ot8Y26mmJTw6zdUZLrRNNYYJo9 5nWOgWdnPXRE46mGHvPhV+X9u7iPiWIxNfqlFPGr1dScLX5k8OYd6kunINAbhVeesyXW pEej8jpQ6roblOpR0s3OqXQPBu9/gN139MopQSJh+OyIEoNiQFrbv2Odpu1GBIgjThKc ljdYIji5eXRx0wLsVerSZwC2BWensjl8xDjmJqPLY/nf8QPkCE0fa808EIL/2vExEoJC sbkqyho9Oqh1c4wKe+SkShq7FQyqmqEG+diIUrgxhNRrn5Fi1+jU3UElZ3Fw0uCvabQn MEWQ== X-Forwarded-Encrypted: i=1; AJvYcCVkCabNjSKLUtPK3CO9oWsia59I6YAQUFtkpC9MycYD/aWdJYr9WliqNVc+4xq/DG8SckoL0h0WDwgvQKs=@vger.kernel.org X-Gm-Message-State: AOJu0YxiStVyPUAueao4u3wiukN8OOBtqHwXs04JoeSfCEX/KBMEU8xu rszvQ39A9J9umVI0Pk8JrBGA5wiLYIyrPcM9To2pDgoiSQbGKpST/Tut X-Gm-Gg: ASbGncvjacy9Atkfz2naULI89N77uRmfzgTlP5Qu1pqC2del5VAVy73b7wsNCO6PAg1 FK+ZBPSQ2jxIH6O8OS1yMNS8wFzcUa2iYvBjNUYhZPhj/Lxs5MoR49IfV1lTUUP5TH8X45QBUSw /lFF5wDPwq8VTART6kFUgwa9x26Wmy1uMMeXUAK4KKlJGzBL4UGZGO4MaThj+ivQRBmATP4s2cj V5he7DxzLoAHQp6qtSv9uPOgdNZ9OqYmHlgpRQFCag1NMEExaOGYV2iDNHUOYwTx3DC9/rET/wD +8xXl79gCFwHnbCOthux1PAJ0WkxFoGPmaE9WHoTz9AgUubz4YTxHDY/qYDSPUPLoaPUBu42ErV hwiuCRTW5s/WunGiTK37QU5E4fuJmkuJNhb/1bMm+Py7HExoQbVy/ZJ0xj+0LRKyocVcA104c6c mxBjDb/IbH9nhgjkRZ4G8ZTAvfyYA4uKX7AfRhy++CRwdJnQuR7pw13w== X-Google-Smtp-Source: AGHT+IHVL/BEiWldm0y8g1R198i5I9jbvyca4K2bOXMaJ5CPndp+saFe0w/sAbEG0HAV5P3htWvg4A== X-Received: by 2002:a05:600c:3b0a:b0:477:9574:d641 with SMTP id 5b1f17b1804b1-47904b1b2ecmr214675995e9.22.1764551756984; Sun, 30 Nov 2025 17:15:56 -0800 (PST) Received: from alarm (92.40.200.0.threembb.co.uk. [92.40.200.0]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-479110b6da9sm216152305e9.0.2025.11.30.17.15.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Nov 2025 17:15:56 -0800 (PST) From: Dale Whinham To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten Cc: =?UTF-8?q?J=C3=A9r=C3=B4me=20de=20Bretagne?= , Dale Whinham , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org Subject: [PATCH v2 5/8] drm/msm/dp: Add dpcd link_rate quirk for Surface Pro 11 OLED Date: Mon, 1 Dec 2025 01:14:46 +0000 Message-ID: <20251201011457.17422-6-daleyo@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251201011457.17422-1-daleyo@gmail.com> References: <20251201011457.17422-1-daleyo@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: J=C3=A9r=C3=B4me de Bretagne The Samsung ATNA30DW01-1 OLED panel in Microsoft Surface Pro 11 (Denali) reports a max link rate value of 0 in the DPCD register, causing the panel to fail to probe. Add a quirk for this panel during DPCD read to set the max link rate to 8.1Gbps (HBR3), which is the expected value as reported by the "EDPOverrideDPCDCaps" block found in the DSDT (0x1E). Signed-off-by: J=C3=A9r=C3=B4me de Bretagne Tested-by: Dale Whinham --- drivers/gpu/drm/display/drm_dp_helper.c | 2 ++ drivers/gpu/drm/msm/dp/dp_panel.c | 14 ++++++++++++++ include/drm/display/drm_dp_helper.h | 7 +++++++ 3 files changed, 23 insertions(+) diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/disp= lay/drm_dp_helper.c index 4aaeae4fa03c..a533fbb2988d 100644 --- a/drivers/gpu/drm/display/drm_dp_helper.c +++ b/drivers/gpu/drm/display/drm_dp_helper.c @@ -2543,6 +2543,8 @@ static const struct dpcd_quirk dpcd_quirk_list[] =3D { { OUI(0x00, 0x0C, 0xE7), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_HBLANK_E= XPANSION_REQUIRES_DSC) }, /* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low DP_MAX_= LINK_RATE */ { OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, BIT(= DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) }, + /* Samsung ATNA30DW01-1 OLED panel in Microsoft Surface Pro 11 reports a = DP_MAX_LINK_RATE of 0 */ + { OUI(0xBA, 0x41, 0x59), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_CAN_DO_M= AX_LINK_RATE_8_1_GBPS) }, }; =20 #undef OUI diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_= panel.c index 15b7f6c7146e..6bcfefd457c4 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -91,6 +91,7 @@ static int msm_dp_panel_read_dpcd(struct msm_dp_panel *ms= m_dp_panel) int rc, max_lttpr_lanes, max_lttpr_rate; struct msm_dp_panel_private *panel; struct msm_dp_link_info *link_info; + struct drm_dp_desc desc; u8 *dpcd, major, minor; =20 panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_= panel); @@ -99,6 +100,19 @@ static int msm_dp_panel_read_dpcd(struct msm_dp_panel *= msm_dp_panel) if (rc) return rc; =20 + rc =3D drm_dp_read_desc(panel->aux, &desc, drm_dp_is_branch(dpcd)); + if (rc) + return rc; + + /* + * for some reason the ATNA30DW01-1 OLED panel in Microsoft Surface Pro 11 + * reports a max link rate of 0 in the DPCD register. Fix this to match t= he + * EDPOverrideDPCDCaps value (0x1E) found in the ACPI DSDT + */ + if (drm_dp_has_quirk(&desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_8_1_GBPS))= { + dpcd[1] =3D DP_LINK_BW_8_1; + } + msm_dp_panel->vsc_sdp_supported =3D drm_dp_vsc_sdp_supported(panel->aux, = dpcd); link_info =3D &msm_dp_panel->link_info; link_info->revision =3D dpcd[DP_DPCD_REV]; diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_= dp_helper.h index 87caa4f1fdb8..737ec5317666 100644 --- a/include/drm/display/drm_dp_helper.h +++ b/include/drm/display/drm_dp_helper.h @@ -820,6 +820,13 @@ enum drm_dp_quirk { * requires enabling DSC. */ DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC, + /** + * @DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_8_1_GBPS: + * + * The device supports a link rate of 8.1 Gbps / HBR3 (0x1e) despite + * the DP_MAX_LINK_RATE register reporting a lower max multiplier. + */ + DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_8_1_GBPS, }; =20 /** --=20 2.52.0 From nobody Mon Dec 1 22:35:40 2025 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 551EA1C84A6 for ; Mon, 1 Dec 2025 01:16:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764551762; cv=none; b=GWqbNMUlwjnUeoS1fGjDHVyPVlCbjuuaqdTimTJB5CDUbYz6G0jkWrZ5t5px4HwH2dCa2lQ2Lh//xrH6JSWKKWdTyfiegojDAjVJdALM7P3RfhVQyAbtCoX9LJw5/fQ+5CQ4PKPotDrCororKI9NZpCWk4mJbM2bErr7s7cSiaU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764551762; c=relaxed/simple; bh=DQZX0aUN3deUMYMHSt3awIN0HT0UN+IAtGAYEYKj0VQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=kleTZIhYSkHDegIhFOmpxWUl2yTyUYdAkOutWa4JUiZXXgJrhR+L1rHFaPn57yQjM7dy+DPgXpjanvw9a5qGh/lU9rXRSbAP0IAhBHpViUr5dx/WhGz+3DODUIylD2A1W2Mo17QIThN5fOuCb8Q2bsH3S8dtU6CaPX7Lrh9esIU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=braBkDvA; arc=none smtp.client-ip=209.85.128.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="braBkDvA" Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-4775ae77516so37229785e9.1 for ; Sun, 30 Nov 2025 17:16:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1764551759; x=1765156559; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/vBWJ3jPxPdxJcqHzl2HAKyWXdjwinH4jPFuqseBeF4=; b=braBkDvA/sZjIRDpvf9C03Emab5eKXMJhN3NKbFpw+Dpk0idMAC3wahAiIRlaax76y Lj2AmB7KfAWonjkm6/emTjk4p1cw/vv9N47Cb1eVvTrmRmt7yMnZbw0Glu+8x3beRqXJ FmePu7hoHbrzu2GUT46NOlmI8iCOtqP4Qx8V9MBlBzt0LgKYr+08pSavu9P5Rht/LlJh 2buZOga+5RtWIJI9CBWcgULquhlcFkzG9RSlo19rGZa+p+vb4ZNS4jT3w1SMw5JHNDMY kTx2YjnWV9lYlR/a18JQh8jMPVO1txh8/IGlct6HPJJAxctYIWYFjQXk1fnnSuq2OFqF UHzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764551759; x=1765156559; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=/vBWJ3jPxPdxJcqHzl2HAKyWXdjwinH4jPFuqseBeF4=; b=aolSnrmM4Lne57kCJANJ0Kx1zq+ntLY+J0ttQcyaXA/mqCznX8nA1XkyM9w4gilF8A 4OQytjFXC1uZBka//DjCJTFtLyO+J7KyPr/1DrzoVnnFermKIvTLKNxWB21tQeAHQuca uyts3Vn6+tAd/kRS/7oXVppMUzKXrRkCB2/jCBSOi9CCN9eiIwCILZCZnsYjIowHt74w FuV5Q9j61URUV4r75HYXM2+7u9ZXnoehw5NYSg2GFlFGbFITX2aIQNUVWmEONvYkOxlQ OZByzsej5f+soZWJwNRQ3wzly8xSYwDWwreWaDlGBx05oKBZtij/ZxDI2kjFElOIUevK 8seQ== X-Forwarded-Encrypted: i=1; AJvYcCXW/QkYUDZOZf76j+BItikw+p4x5HS03RNpcvRd3M86R/vvUmacmvQUbPmdXwN+Rz2SNOxFQeDblZmr3OI=@vger.kernel.org X-Gm-Message-State: AOJu0YxO1qL4feAnCcFlaQM++QDEFsCEs5vzfFl4+shlZkBQvh45UdON Uzi2+3iVIr1WegdeaAWVrcupTzoDw//ZkRW5sJGKeVDpabUEEb4wrRiF X-Gm-Gg: ASbGncu3M67UHgoPH0G6qie0+zzT9wuy34VdHSyHhDWsB28r3fI1zEM1TLImi2EbdTD XpW5qHW4U5whJjqqZVyDySPlFGWA71cRtGHULwIxOww6eD5PtsiMina6czEK8+1SUvt60X3D7Xj LP0Tc3+x5f5c3CrtzFBxVzzwAhlz4/TpQwHulfMYCl96cb63tHuN23dp+NQLscW1Sz3nxMZQDrV jhkAo3hrOe7WZ5W7tjPnF4knCosWghKypH0KSA13Y0lSqrVklS4zjMh3elG0crziI7j/aFkHsPE jPLT9Adz3n7P4LtZwVyhH8ZRPLCGqbjdc2vJvOkBOar+93f/3ghcwwlck1yQ6uafYn1jLM9SCWE Jymax0ZIErDfxezb2/YMXqReBeT9ACdr4qmARqU9xU32AzcQgRLzAxl3PcAeIA6UKynmUZ/qYZ3 7AAeW88Y0CSxMjZLdWBekVJiPwOWxOSz4OluYlIpCZLz3mRXex3MAeCA== X-Google-Smtp-Source: AGHT+IHPudKEEX4VAjuHNzkSbk45c8iSpRbQfuQpSIb3ohjq0wxflc5C6EoWRIJcTjRDZbjpyIxAHA== X-Received: by 2002:a05:600c:8b35:b0:475:d8b3:a9d5 with SMTP id 5b1f17b1804b1-477c10d6fdamr360907655e9.10.1764551758470; Sun, 30 Nov 2025 17:15:58 -0800 (PST) Received: from alarm (92.40.200.0.threembb.co.uk. [92.40.200.0]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-479110b6da9sm216152305e9.0.2025.11.30.17.15.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Nov 2025 17:15:58 -0800 (PST) From: Dale Whinham To: Johannes Berg , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jeff Johnson Cc: =?UTF-8?q?J=C3=A9r=C3=B4me=20de=20Bretagne?= , Dale Whinham , Jeff Johnson , linux-wireless@vger.kernel.org, devicetree@vger.kernel.org, ath12k@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 6/8] dt-bindings: wireless: ath12k: Add disable-rfkill property Date: Mon, 1 Dec 2025 01:14:47 +0000 Message-ID: <20251201011457.17422-7-daleyo@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251201011457.17422-1-daleyo@gmail.com> References: <20251201011457.17422-1-daleyo@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: J=C3=A9r=C3=B4me de Bretagne rfkill should be disabled according to the Surface Pro 11's DSDT. https://lore.kernel.org/all/20250113074810.29729-3-quic_lingbok@quicinc.com/ has added support to read the ACPI bitflag when ACPI is supported. Document the disable-rfkill property to expose one specific feature (DISABLE_RFKILL_BIT) for devices described with a DT, so that the feature can be disabled. Signed-off-by: J=C3=A9r=C3=B4me de Bretagne Signed-off-by: Dale Whinham --- .../devicetree/bindings/net/wireless/qcom,ath12k.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/net/wireless/qcom,ath12k.yam= l b/Documentation/devicetree/bindings/net/wireless/qcom,ath12k.yaml index dc68dd59988f..be44b1495ecc 100644 --- a/Documentation/devicetree/bindings/net/wireless/qcom,ath12k.yaml +++ b/Documentation/devicetree/bindings/net/wireless/qcom,ath12k.yaml @@ -54,6 +54,9 @@ properties: vddpcie1p8-supply: description: VDD_PCIE_1P8 supply regulator handle =20 + disable-rfkill: + type: boolean + required: - compatible - reg --=20 2.52.0 From nobody Mon Dec 1 22:35:40 2025 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68DD6288D2 for ; Mon, 1 Dec 2025 01:16:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764551763; cv=none; b=qBmTKIBv8OESvryliA8C2r86dKXlcjKmFIzCOr9R6pMkN+LS/k9896qJ/64RVg1eX/BaTKjZWJzj2uSAzEX3WlichjA5evvHKGcv9jGXcBMw22A5vIcARUVtrpf6emCgopnzCrZ+yv11b/bOsn9EjU48OyUGFw1jXKuhHgK6nCY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764551763; c=relaxed/simple; bh=kL8pNkspxY32oK4P0WLuxKf2uxEIHREei2L7z0gtL1o=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=PaINlZKgpOxB7S5XlEMseaqrNrDWKzqFdmvc3pXd0+x0VKXX2RXzlFuwYSkIoAEmJ/l49t314QjX1CL0AuCmEpcNyoeLDujWqiE9WjOl2bqIt91F56sZ1HAwkhdP1VagbipibfxAMRwKtmnhGZJzjaOyBZh45tSVdZYXPfT0Vns= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=FpwWlrgb; arc=none smtp.client-ip=209.85.128.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="FpwWlrgb" Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-4779a637712so20694955e9.1 for ; Sun, 30 Nov 2025 17:16:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1764551760; x=1765156560; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Mo4q7JKeuUk4aiyRFRdMebz2WrMLhSzb/XBqsXZtV5s=; b=FpwWlrgb1NK+V4xlebIacjrffG+K7cxx4Wl85nlpZiTHoQpTWSMb38ZvXvOXW0/8DM UMaOrD0M2njM4PBCbZetcxcL5b4Qcn0mdjz1WMjt5UkMpKbkFJKJCshTeM9HEADvYDug 8Z8gWz2IWFutDXRNNrAPrquPkr2d/YCR27okvc21xeNH36yKWeoldF4sLZvkN6EKKMMI m6jVkq0+Xnbe0+FG9gG2lADinoCKAJn2TmerOavym67PrDYraipT/nZ9SFbrXu4U+Xz/ YM305YvbmGOlyjrA8PIuowLeHtNls6o1lwg6I9rNoUPJAu4MDg3NqrE0/6VRBDGTkMNJ 6HyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764551760; x=1765156560; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=Mo4q7JKeuUk4aiyRFRdMebz2WrMLhSzb/XBqsXZtV5s=; b=JxHHdgDFkr8z/N1w1j6/9rS0YbZ2rgajwhMJWKLPaUIRuQbXkpww6KWl1cFxSOSdwS ixB+QNjBRttor9lz6STzIb6v5ffHwoQVC5O0hSsa5I0uLM85IU9Z6UPF7eVTN8ibHWaS 3l8+bS7lFlpI9WOLw4VH6vTKZLCjtxRVcRqYtvBL9K8ZCm9hmWvh/HNnVho3/Oy8CBAm 2wE14KRuqb+spXL2ECkXfagI79uM+jZeKu4hQ+sLd0r1QQ5Dhqh0ztBRibvthByeNTaZ uO/T+aV4p5Mkk/jUGTV3RLlB5TA+hn9tOdDhENKrohBa9AlXqimyhbTUM18dkR0vvJ5C AcAg== X-Forwarded-Encrypted: i=1; AJvYcCWWwVxYQ3YWbAjxQLnqSURsdBZnRdnSWUFxgCW/8Z0DDGNwVC3EfySWlxFDe7czLxLY2xzilZrCypKxBf8=@vger.kernel.org X-Gm-Message-State: AOJu0YzbuhUDGO41wxs/Z+lo4cxpjcG92BlsVHmuKCO1N9jtZH7EYeD5 I2NuxDxhJu73LnOnf6UrDFP5SeosIB0xAdq6UwyC2IVYpvU+Jjaa4BCoSQ/w8QW9 X-Gm-Gg: ASbGncvECyd4q+NvcFsZnMEdD+BvgPp4qZNRjO79nWL7mfe9aUmw78ZZtpz4StTh+fu cToiA+36lnueCbC5gYiLZSEKQjyVWqQD2S/Lqs2Ols0/Zk5EiER3FV74P2xj3buP1Fukr3y66Mi VX5CSKWZWt48ke06rvRltpiU96p+vihRJm8ZECmA2pdTaKqVKyAB+cErRUanWpsEcG7mBcJfktZ R417ZJqTK/hQTX0Z/etKJ1kAZiYKPKEetkfZzhZ+ZnX98reWrbtJ8Y8f+67wcYAd6Iy3YI7TGHK +CTuV+tI/0CeyRiAaYh8XrLirmL6A3z+pko/SSaem5D29uqa5ultVbWfYsUq0BOogfis5/gY10W cC8eQ4sjeGQXxU4M0bWdQIjsE2/Bx8RgW1G+Jwv+f/HweAzbvyU80Iu9ImeHd8dMUZ9r3tVmFTZ jPKvGQmEPR9ZDtvOagZepMkktQ16uFZTzMujIZm41a19dEuVyHJ1e65A== X-Google-Smtp-Source: AGHT+IH5rUuYD4eqKwAK50niTL5lsEFRsaD9OQ4iOSbw+TFAzVIVsM+nWiZuPk0ZntcRHhpGuzcYRQ== X-Received: by 2002:a05:600c:450f:b0:46d:ba6d:65bb with SMTP id 5b1f17b1804b1-477c01eb9bdmr404432425e9.31.1764551759501; Sun, 30 Nov 2025 17:15:59 -0800 (PST) Received: from alarm (92.40.200.0.threembb.co.uk. [92.40.200.0]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-479110b6da9sm216152305e9.0.2025.11.30.17.15.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Nov 2025 17:15:59 -0800 (PST) From: Dale Whinham To: Jeff Johnson Cc: =?UTF-8?q?J=C3=A9r=C3=B4me=20de=20Bretagne?= , Dale Whinham , linux-wireless@vger.kernel.org, ath12k@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 7/8] wifi: ath12k: Add support for disabling rfkill via devicetree Date: Mon, 1 Dec 2025 01:14:48 +0000 Message-ID: <20251201011457.17422-8-daleyo@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251201011457.17422-1-daleyo@gmail.com> References: <20251201011457.17422-1-daleyo@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Some devices (e.g. Microsoft Surface Pro 11) indicate that the rfkill feature should be disabled by means of an ACPI bitflag. If ACPI is not being used (i.e. booting using a devicetree) then this property will not be read and therefore rfkill may be enabled and the ath12k will be hard-blocked with no way to disable it. Add a devicetree property that allows us to disable the rfkill feature. Tested-by: J=C3=A9r=C3=B4me de Bretagne Signed-off-by: Dale Whinham --- drivers/net/wireless/ath/ath12k/core.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/wireless/ath/ath12k/core.c b/drivers/net/wireless/= ath/ath12k/core.c index 5d494c5cdc0d..954028495ea6 100644 --- a/drivers/net/wireless/ath/ath12k/core.c +++ b/drivers/net/wireless/ath/ath12k/core.c @@ -78,6 +78,9 @@ static int ath12k_core_rfkill_config(struct ath12k_base *= ab) if (ath12k_acpi_get_disable_rfkill(ab)) return 0; =20 + if (of_property_read_bool(ab->dev->of_node, "disable-rfkill")) + return 0; + for (i =3D 0; i < ab->num_radios; i++) { ar =3D ab->pdevs[i].ar; =20 --=20 2.52.0 From nobody Mon Dec 1 22:35:40 2025 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8697D1DE8BE for ; Mon, 1 Dec 2025 01:16:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764551764; cv=none; b=iLCCcHSSNDXNEJW8bq7AXwL9LwbSQIcbrCIWX0CZHHkLAjPYEvB4zeDnj4JSJaKaG9sDt9eBoJ1WvvsSyPCeGFOCAZkTHA1mph2H+qJvWvCrsqJx8/ePTgOkm7zv2RzEt3kGqRxNNupvhM+YQRQF0rXJkd9Hw8wm8jFcR0ImdQ0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764551764; c=relaxed/simple; bh=OkCDO9ck5Q4rj4jCmkv7rseTzENdZD+IfBXalzly0hU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=QisMU2HmJpVwrLgNfIwDAMrT+uMNXORnoXmCbFMBJPzRCzvUT0E30QailGMpxr7b5OiokH+4V/Unkb2II9RT8iVtoQ7DKgNXjAiVeb56inrSZQgRGfRWIY3yzc4W4s6M2rtYpEca0ee1ALBWwL7PfG6KerRatW938yEGW8XsoUs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=i9rSoWvf; arc=none smtp.client-ip=209.85.128.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="i9rSoWvf" Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-477563e28a3so23916415e9.1 for ; Sun, 30 Nov 2025 17:16:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1764551761; x=1765156561; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TIc9HiGTae4NKzXvKMP64+f0l48VwiinzatOpKlXzB8=; b=i9rSoWvfZe4uuG3eI56V3MCwO/elqwfYQj+MITbG1BrjMXeTLL3P0WbFh1x8vpxz8h cKWzwyjYuL9pHqKbVIeG5lX+LmcIwfo75RwStRu2TkKe5frpL00b5iA85BFXWMP8tOZp HkZUCShQTABCXb5K+7RLyxRaRilvUkNESkbqvKX7UxfHTZ8lGXKHOz6vw2os4kNHSKnY 0iw6tTgzFIsE2jYY9F3K1e/rpoaz9+cLw++OLoqVNGxIg1vPentu9UTd6PfOQvW8UD1D vDfiB3Ny3PpvEHFGGYBrWiYE0eqzdDJG/Me2mwrHZLodbq1rE+vg2+TDlo82DelOgmle 4Vdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764551761; x=1765156561; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=TIc9HiGTae4NKzXvKMP64+f0l48VwiinzatOpKlXzB8=; b=En+GYogFn+P6W5t7JoCp+PV3L0ES0jgPOc3Zwk6N5mvr1U4rpilUBK8bA9SQdBp8Ei Gf+uTZE/HwA5+WYtM9MwMOFWaPzNyoqFTPWz1KRnOANbbLAxOdLtOfMiaOGz/jzKD/yZ AEVUrxD3PiE+QfPaR8iSskhy6jPnUruKCuwsQeg98hosw4cywsiv1UXbCn/wEzcUbgcX fFUOLwYuvDEbeRQSr/c2FbcbEx59DEBLY7CJfHHMnC4FLIwjtbRfWx402niulllBE3j6 CtUM8Col35ponBXohFsQon8BJ1382nkXRLMUXArJCpjUc3Sm7Tz42DVjQh0GLhr92UKz yv3g== X-Forwarded-Encrypted: i=1; AJvYcCXLVtX1tyVEJsrCyYHuM/p9UQL+qFZ4Ov6RALl/jq6KU3VnSngdhIcfH1RXNt/s4rkXOH9iSgQ1/JbcSko=@vger.kernel.org X-Gm-Message-State: AOJu0Yzt2bebwTSalsnZ9GHm8tYYgGdjMGNLoN83R45bMKrDgkZH8I/F UlDOwDDVp1tlz749rVnVvYSlk/jWHmtWTOm7SJTzymtMnSEnQbPKfIE2 X-Gm-Gg: ASbGncvpiJ8616h3z1sg+czVU+naXm+257v7YvW8RimqUl457xxJTDHgIfvWAojBra1 NqvrgqvgaGh+sJfYRLxLHGo1P/zibc5I66xpQGyK2r+C4VHfKFV9MkyypRpYORioe9N+01iMP0c iYjuDZjzwTMd4swj/8YnEMJRGIM5lKcPMH6ttG6OzLYFwMwJ2ROq8PS2iAcmpyI7HqmRuwOSG7E NxHYeX6hhjOCt21XqyUYnDLHNOIgBKjZoLsKXTHnRVeAi6VepPxV5zikGtDQsfnsM0+y5Rw9XmH bfV83BZbIjTshYBwssWd29MwqG9+QF6PcpD08WNT++1VCPat95Q/KfqVkF6cDzFRynIguQZa3Lc UmxjpezH2y7qH2IVNCWO+IALDAlRaV8wva4NV7uqqWyt4e089RZGJtTofFrhraxjQr8UcB4vwY1 zqYyEsP1FrkbjZpNUnd1bBqr8UkiNPQpf67w9PSws/vGsOGdN7GCnb/1TXSTOqC09M X-Google-Smtp-Source: AGHT+IGm4gC/z/V448V0Dya/MA433KTldbgXox5LV2IX+XB9gf9DTH0dNZJEX3DhUVGCCIzrPAaDhg== X-Received: by 2002:a05:600c:21c7:b0:477:75b4:d2d1 with SMTP id 5b1f17b1804b1-477b9ef50b4mr305611365e9.15.1764551760881; Sun, 30 Nov 2025 17:16:00 -0800 (PST) Received: from alarm (92.40.200.0.threembb.co.uk. [92.40.200.0]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-479110b6da9sm216152305e9.0.2025.11.30.17.15.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Nov 2025 17:16:00 -0800 (PST) From: Dale Whinham To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: =?UTF-8?q?J=C3=A9r=C3=B4me=20de=20Bretagne?= , Dale Whinham , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 8/8] arm64: dts: qcom: x1-microsoft-denali: Disable rfkill for wifi0 Date: Mon, 1 Dec 2025 01:14:49 +0000 Message-ID: <20251201011457.17422-9-daleyo@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251201011457.17422-1-daleyo@gmail.com> References: <20251201011457.17422-1-daleyo@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Disable rfkill as it is supposed to be according to the ath12k feature flags in the Microsoft Surface Pro 11 ACPI DSDT. Signed-off-by: Dale Whinham Signed-off-by: J=C3=A9r=C3=B4me de Bretagne --- arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi b/arch/arm64= /boot/dts/qcom/x1-microsoft-denali.dtsi index 64eabe2b96cf..0bde0db01f47 100644 --- a/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi @@ -976,6 +976,8 @@ wifi@0 { vddrfa1p8-supply =3D <&vreg_pmu_rfa_1p8>; vddpcie0p9-supply =3D <&vreg_pmu_pcie_0p9>; vddpcie1p8-supply =3D <&vreg_pmu_pcie_1p8>; + + disable-rfkill; }; }; =20 --=20 2.52.0