From nobody Mon Dec 1 22:36:19 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BFC88A55; Mon, 1 Dec 2025 00:31:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764549065; cv=none; b=aJaLw6wB6aVgPSTzAAdboFEjz6yoCBo0CnJK2BxaJLqsiqO9EDiynZ45FcRDiUeuMKXtbQsFvWffUQmLzit8Pd6okho9A/pwK/BtPDBZutU18CnAAph+OVk3TjOLM1SPtPIzQF1BikjnbxAHKKgIuK7jvlndhcwAMSiKRmT23xk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764549065; c=relaxed/simple; bh=qq3bh/4Q+gsaYZv2rX/TRb2x3pUU1Bkzv3I7M+0D4tc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=UrBESeaXsr6rNqsr71aOQuY3K9e/2fE2DcY7t03q/sg8LgqGCkYRmqbWGh1As+oMb+TOfQYFBXqhMEB9DY4sWE79U/kZiiLAnJD46dCaXBOeOcJs6WRGo6MVW8R5MoHUtof+pk3ze1RDvGc98p/g2KAyAo3Qxv7KU2/Pjb1Wuaw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=BOvUOcnb; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="BOvUOcnb" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D02E3C16AAE; Mon, 1 Dec 2025 00:31:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1764549063; bh=qq3bh/4Q+gsaYZv2rX/TRb2x3pUU1Bkzv3I7M+0D4tc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BOvUOcnbIDpEi99q+vwQaQAbXboGrrAKLol1N/vXUGQ1YkD4lvgX1TBXAeD+pms6M pkWwpPVslYlE1tk5C9gHJx2Po0OgNS74LgqIbtAdZZAMSL3lc14rq9S4CCfd74LS8p ziuqH3w6M1A9353hpiNLACOZOZOLxp/alQfozSvqwOlAYv9v8fIVUrzpjxBH282Ck5 S+YQFIjlqyGaJuiprXRU76jHQwz8sMKwoBGV/dMm1idtK9k4UHtYfWwqHoeTq0Oace BEviOrlhUCHc851uTVtuyVkJyCJEIK+FdiJwhWmg3q9jihHQTlOPGtROu5GzsRUZgf X+lA49p9f6DzQ== From: guoren@kernel.org To: paul.walmsley@sifive.com, palmer@dabbelt.com, guoren@kernel.org, leobras@redhat.com, ajones@ventanamicro.com, anup@brainfault.org, atish.patra@linux.dev, corbet@lwn.net Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org Subject: [RFC PATCH V3 1/4] RISC-V: paravirt: Add pvqspinlock KVM backend Date: Sun, 30 Nov 2025 19:30:38 -0500 Message-Id: <20251201003041.695081-2-guoren@kernel.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20251201003041.695081-1-guoren@kernel.org> References: <20251201003041.695081-1-guoren@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: "Guo Ren (Alibaba DAMO Academy)" Add the files functions needed to support the SBI PVLOCK (paravirt qspinlock kick_cpu) extension. Implement kvm_sbi_ext_pvlock_kick_- cpu(), and we only need to call the kvm_vcpu_kick() and bring target_vcpu from the halt state. Reviewed-by: Leonardo Bras Signed-off-by: Guo Ren (Alibaba DAMO Academy) --- arch/riscv/include/asm/kvm_vcpu_sbi.h | 1 + arch/riscv/include/asm/sbi.h | 5 +++ arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/Makefile | 1 + arch/riscv/kvm/vcpu_sbi.c | 4 ++ arch/riscv/kvm/vcpu_sbi_pvlock.c | 57 +++++++++++++++++++++++++++ 6 files changed, 69 insertions(+) create mode 100644 arch/riscv/kvm/vcpu_sbi_pvlock.c diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm= /kvm_vcpu_sbi.h index 3497489e04db..d0df83ecd9fd 100644 --- a/arch/riscv/include/asm/kvm_vcpu_sbi.h +++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h @@ -107,6 +107,7 @@ extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext= _sta; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_fwft; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_experimental; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_vendor; +extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_pvlock; =20 #ifdef CONFIG_RISCV_PMU_SBI extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_pmu; diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index ccc77a89b1e2..dd0734e1ebb6 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -37,6 +37,7 @@ enum sbi_ext_id { SBI_EXT_NACL =3D 0x4E41434C, SBI_EXT_FWFT =3D 0x46574654, SBI_EXT_MPXY =3D 0x4D505859, + SBI_EXT_PVLOCK =3D 0x50564C4B, =20 /* Experimentals extensions must lie within this range */ SBI_EXT_EXPERIMENTAL_START =3D 0x08000000, @@ -505,6 +506,10 @@ enum sbi_mpxy_rpmi_attribute_id { #define SBI_MPXY_CHAN_CAP_SEND_WITHOUT_RESP BIT(4) #define SBI_MPXY_CHAN_CAP_GET_NOTIFICATIONS BIT(5) =20 +enum sbi_ext_pvlock_fid { + SBI_EXT_PVLOCK_KICK_CPU =3D 0, +}; + /* SBI spec version fields */ #define SBI_SPEC_VERSION_DEFAULT 0x1 #define SBI_SPEC_VERSION_MAJOR_SHIFT 24 diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/as= m/kvm.h index 759a4852c09a..9d447995de84 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -211,6 +211,7 @@ enum KVM_RISCV_SBI_EXT_ID { KVM_RISCV_SBI_EXT_STA, KVM_RISCV_SBI_EXT_SUSP, KVM_RISCV_SBI_EXT_FWFT, + KVM_RISCV_SBI_EXT_PVLOCK, KVM_RISCV_SBI_EXT_MAX, }; =20 diff --git a/arch/riscv/kvm/Makefile b/arch/riscv/kvm/Makefile index 07197395750e..40ddb7c06ffe 100644 --- a/arch/riscv/kvm/Makefile +++ b/arch/riscv/kvm/Makefile @@ -35,6 +35,7 @@ kvm-y +=3D vcpu_sbi_sta.o kvm-y +=3D vcpu_sbi_system.o kvm-$(CONFIG_RISCV_SBI_V01) +=3D vcpu_sbi_v01.o kvm-y +=3D vcpu_switch.o +kvm-y +=3D vcpu_sbi_pvlock.o kvm-y +=3D vcpu_timer.o kvm-y +=3D vcpu_vector.o kvm-y +=3D vm.o diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c index 1b13623380e1..dd74f789f44c 100644 --- a/arch/riscv/kvm/vcpu_sbi.c +++ b/arch/riscv/kvm/vcpu_sbi.c @@ -90,6 +90,10 @@ static const struct kvm_riscv_sbi_extension_entry sbi_ex= t[] =3D { .ext_idx =3D KVM_RISCV_SBI_EXT_VENDOR, .ext_ptr =3D &vcpu_sbi_ext_vendor, }, + { + .ext_idx =3D KVM_RISCV_SBI_EXT_PVLOCK, + .ext_ptr =3D &vcpu_sbi_ext_pvlock, + }, }; =20 static const struct kvm_riscv_sbi_extension_entry * diff --git a/arch/riscv/kvm/vcpu_sbi_pvlock.c b/arch/riscv/kvm/vcpu_sbi_pvl= ock.c new file mode 100644 index 000000000000..aeb48c3fca50 --- /dev/null +++ b/arch/riscv/kvm/vcpu_sbi_pvlock.c @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c), 2025 Alibaba Damo Academy + * + * Authors: + * Guo Ren + */ + +#include +#include +#include +#include +#include + +static int kvm_sbi_ext_pvlock_kick_cpu(struct kvm_vcpu *vcpu) +{ + struct kvm_cpu_context *cp =3D &vcpu->arch.guest_context; + struct kvm *kvm =3D vcpu->kvm; + struct kvm_vcpu *target; + + target =3D kvm_get_vcpu_by_id(kvm, cp->a0); + if (!target) + return SBI_ERR_INVALID_PARAM; + + kvm_vcpu_kick(target); + + if (READ_ONCE(target->ready)) + kvm_vcpu_yield_to(target); + + return SBI_SUCCESS; +} + +static int kvm_sbi_ext_pvlock_handler(struct kvm_vcpu *vcpu, struct kvm_ru= n *run, + struct kvm_vcpu_sbi_return *retdata) +{ + int ret =3D 0; + struct kvm_cpu_context *cp =3D &vcpu->arch.guest_context; + unsigned long funcid =3D cp->a6; + + switch (funcid) { + case SBI_EXT_PVLOCK_KICK_CPU: + ret =3D kvm_sbi_ext_pvlock_kick_cpu(vcpu); + break; + default: + ret =3D SBI_ERR_NOT_SUPPORTED; + } + + retdata->err_val =3D ret; + + return 0; +} + +const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_pvlock =3D { + .extid_start =3D SBI_EXT_PVLOCK, + .extid_end =3D SBI_EXT_PVLOCK, + .handler =3D kvm_sbi_ext_pvlock_handler, +}; --=20 2.40.1