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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2025 11:09:19.4905 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 28c5793a-31ac-4ff0-5080-08de30ca131c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0E0.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6460 On some platforms, UMA allocation size can be set using the ATCS methods. Add helper functions to interact with this functionality. Co-developed-by: Mario Limonciello (AMD) Signed-off-by: Mario Limonciello (AMD) Reviewed-by: Alex Deucher Signed-off-by: Yo-Jung Leo Lin (AMD) --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 7 ++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 43 ++++++++++++++++++++++++++++= ++++ drivers/gpu/drm/amd/include/amd_acpi.h | 30 ++++++++++++++++++++++ 3 files changed, 80 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdg= pu/amdgpu.h index ca9c2b54045b..cd9a71abf4c5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1718,12 +1718,14 @@ int amdgpu_acpi_init(struct amdgpu_device *adev); void amdgpu_acpi_fini(struct amdgpu_device *adev); bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_devic= e *adev); bool amdgpu_acpi_is_power_shift_control_supported(void); +bool amdgpu_acpi_is_set_uma_allocation_size_supported(void); int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, u8 perf_req, bool advertise); int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, u8 dev_state, bool drv_state); int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev, enum amdgpu_ss ss_state); +int amdgpu_acpi_set_uma_allocation_size(struct amdgpu_device *adev, u8 ind= ex, u8 type); int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset, u64 *tmr_size); @@ -1752,6 +1754,7 @@ static inline bool amdgpu_acpi_should_gpu_reset(struc= t amdgpu_device *adev) { re static inline void amdgpu_acpi_detect(void) { } static inline void amdgpu_acpi_release(void) { } static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { re= turn false; } +static inline bool amdgpu_acpi_is_set_uma_allocation_size_supported(void) = { return false; } static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *ad= ev, u8 dev_state, bool drv_state) { return 0; } static inline int amdgpu_acpi_smart_shift_update(struct amdgpu_device *ade= v, @@ -1759,6 +1762,10 @@ static inline int amdgpu_acpi_smart_shift_update(str= uct amdgpu_device *adev, { return 0; } +static inline int amdgpu_acpi_set_uma_allocation_size(struct amdgpu_device= *adev, u8 index, u8 type) +{ + return -EINVAL; +} static inline void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlig= ht_caps *caps) { } #endif =20 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd= /amdgpu/amdgpu_acpi.c index 92070738bd42..bce9027fa241 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c @@ -670,6 +670,11 @@ bool amdgpu_acpi_is_power_shift_control_supported(void) return amdgpu_acpi_priv.atcs.functions.power_shift_control; } =20 +bool amdgpu_acpi_is_set_uma_allocation_size_supported(void) +{ + return amdgpu_acpi_priv.atcs.functions.set_uma_allocation_size; +} + /** * amdgpu_acpi_pcie_notify_device_ready * @@ -910,6 +915,44 @@ static struct amdgpu_numa_info *amdgpu_acpi_get_numa_i= nfo(uint32_t pxm) } #endif =20 +/** + * amdgpu_acpi_set_uma_allocation_size - Set Unified Memory Architecture a= llocation size via ACPI + * @adev: Pointer to the amdgpu_device structure + * @index: Index specifying the UMA allocation + * @type: Type of UMA allocation + * + * This function configures the UMA allocation size for the specified devi= ce + * using ACPI methods. The allocation is determined by the provided index = and type. + * Returns 0 on success or a negative error code on failure. + */ +int amdgpu_acpi_set_uma_allocation_size(struct amdgpu_device *adev, u8 ind= ex, u8 type) +{ + struct atcs_set_uma_allocation_size_input atcs_input; + struct amdgpu_atcs *atcs =3D &amdgpu_acpi_priv.atcs; + struct acpi_buffer params; + union acpi_object *info; + + if (!amdgpu_acpi_is_set_uma_allocation_size_supported()) + return -EINVAL; + + atcs_input.size =3D sizeof(struct atcs_set_uma_allocation_size_input); + atcs_input.uma_size_index =3D index; + atcs_input.uma_size_type =3D type; + + params.length =3D sizeof(struct atcs_set_uma_allocation_size_input); + params.pointer =3D &atcs_input; + + info =3D amdgpu_atcs_call(atcs, ATCS_FUNCTION_SET_UMA_ALLOCATION_SIZE, &p= arams); + if (!info) { + drm_err(adev_to_drm(adev), "ATCS UMA allocation size update failed\n"); + return -EIO; + } + + kfree(info); + + return 0; +} + /** * amdgpu_acpi_get_node_id - obtain the NUMA node id for corresponding amd= gpu * acpi device handle diff --git a/drivers/gpu/drm/amd/include/amd_acpi.h b/drivers/gpu/drm/amd/i= nclude/amd_acpi.h index e582339e8e8e..84933c07f720 100644 --- a/drivers/gpu/drm/amd/include/amd_acpi.h +++ b/drivers/gpu/drm/amd/include/amd_acpi.h @@ -24,6 +24,8 @@ #ifndef AMD_ACPI_H #define AMD_ACPI_H =20 +#include + #define ACPI_AC_CLASS "ac_adapter" =20 struct atif_verify_interface { @@ -112,6 +114,17 @@ struct atcs_pwr_shift_input { u8 drv_state; /* 0 =3D operational, 1 =3D not operational */ } __packed; =20 +struct atcs_get_uma_size_output { + u16 size; /* structure size in bytes (includes size field) */ + u32 uma_size_mb; /* allocated UMA size in MB */ +} __packed; + +struct atcs_set_uma_allocation_size_input { + u16 size; /* structure size in bytes (includes size field) */ + u8 uma_size_index; /* UMA size index */ + u8 uma_size_type; /* UMA size type */ +} __packed; + /* AMD hw uses four ACPI control methods: * 1. ATIF * ARG0: (ACPI_INTEGER) function code @@ -494,4 +507,21 @@ struct atcs_pwr_shift_input { * OUTPUT: none */ =20 +#define ATCS_FUNCTION_GET_UMA_SIZE 0x6 +/* ARG0: ATCS_FUNCTION_GET_UMA_SIZE + * ARG1: none + * OUTPUT: + * WORD - structure size in bytes (includes size field) + * DWORD - allocated UMA size in MB + */ + +#define ATCS_FUNCTION_SET_UMA_ALLOCATION_SIZE 0xA +/* ARG0: ATCS_FUNCTION_SET_UMA_ALLOCATION_SIZE + * ARG1: + * WORD - structure size in bytes (includes size field) + * BYTE - UMA size index + * BYTE - UMA size type + * OUTPUT: none + */ + #endif --=20 2.43.0