From nobody Mon Dec 1 22:37:08 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5C613287257; Mon, 1 Dec 2025 06:29:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764570577; cv=none; b=hwiHu63BugDvHE1Hu3hoEJMaF2B21Vj0QC25n95zAvgDmJD6IAYLvgAtdnwLy53s7++CrZWYYmopXAg/evPCY+36dL6jKxYXiYSJUzbxk5CAw8IQRJrhTjzGw+szaJoZIEQvX+ThuCpa5PNpAyYiAJ5gDAsNuhLySjwljaVl0kM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764570577; c=relaxed/simple; bh=/twL2B0Pnt+j9loTcmUqQd/0tnO4Dsh0qXF90ASTQ3c=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=htuCh/P4lPo+9VMFQ2scRG+x23OMQxjKJCaV//8Qp/xQi7VrXYYpvwScs7aL+NcSzkrhyVhv9Jj4uVGxfZAyabgO6QPi335NFcdQ/mSVwZFORCPtq4eay6pLk+2j/YNB0BuyiwNM9Eb9wDdVT2m+Of2/lAmbngqL8YCGv26rV4A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Mon, 1 Dec 2025 14:29:16 +0800 Received: from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Mon, 1 Dec 2025 14:29:16 +0800 From: Jacky Chou Date: Mon, 1 Dec 2025 14:29:15 +0800 Subject: [PATCH v6 5/7] PCI: Add FMT, TYPE and CPL status definition for TLP header Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20251201-upstream_pcie_rc-v6-5-8c8800c56b16@aspeedtech.com> References: <20251201-upstream_pcie_rc-v6-0-8c8800c56b16@aspeedtech.com> In-Reply-To: <20251201-upstream_pcie_rc-v6-0-8c8800c56b16@aspeedtech.com> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , "Andrew Jeffery" , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , "Manivannan Sadhasivam" , Linus Walleij , Philipp Zabel CC: , , , , , , Andrew Jeffery , , , Jacky Chou X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764570556; l=1690; i=jacky_chou@aspeedtech.com; s=20251031; h=from:subject:message-id; bh=/twL2B0Pnt+j9loTcmUqQd/0tnO4Dsh0qXF90ASTQ3c=; b=S1f2Bl/VlL3nz8Tm8pL4k6a9p3j+uTpa098bKvGFkGlGoxMbOSLz4oMLK30DeIBuZfF4mMBdq rhgNzaXtU8NA7mYmETdc9ncKJ9ic/0JWthuUrQ4WIgayFXCAaINcGME X-Developer-Key: i=jacky_chou@aspeedtech.com; a=ed25519; pk=8XBx7KFM1drEsfCXTH9QC2lbMlGU4XwJTA6Jt9Mabdo= According to PCIe specification, add FMT, TYPE and CPL status definition for TLP header. Acked-by: Bjorn Helgaas Signed-off-by: Jacky Chou --- drivers/pci/pci.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 36f8c0985430..b186f3ea6a78 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -63,6 +63,18 @@ struct pcie_tlp_log; #define PCIE_LINK_WAIT_MAX_RETRIES 10 #define PCIE_LINK_WAIT_SLEEP_MS 90 =20 +/* Format of TLP; PCIe r7.0, sec 2.2.1 */ +#define PCIE_TLP_FMT_3DW_NO_DATA 0x00 /* 3DW header, no data */ +#define PCIE_TLP_FMT_4DW_NO_DATA 0x01 /* 4DW header, no data */ +#define PCIE_TLP_FMT_3DW_DATA 0x02 /* 3DW header, with data */ +#define PCIE_TLP_FMT_4DW_DATA 0x03 /* 4DW header, with data */ + +/* Type of TLP; PCIe r7.0, sec 2.2.1 */ +#define PCIE_TLP_TYPE_CFG0_RD 0x04 /* Config Type 0 Read Request */ +#define PCIE_TLP_TYPE_CFG0_WR 0x04 /* Config Type 0 Write Request */ +#define PCIE_TLP_TYPE_CFG1_RD 0x05 /* Config Type 1 Read Request */ +#define PCIE_TLP_TYPE_CFG1_WR 0x05 /* Config Type 1 Write Request */ + /* Message Routing (r[2:0]); PCIe r6.0, sec 2.2.8 */ #define PCIE_MSG_TYPE_R_RC 0 #define PCIE_MSG_TYPE_R_ADDR 1 @@ -84,6 +96,9 @@ struct pcie_tlp_log; #define PCIE_MSG_CODE_DEASSERT_INTC 0x26 #define PCIE_MSG_CODE_DEASSERT_INTD 0x27 =20 +/* Cpl. status of Complete; PCIe r7.0, sec 2.2.9.1 */ +#define PCIE_CPL_STS_SUCCESS 0x00 /* Successful Completion */ + #define PCI_BUS_BRIDGE_IO_WINDOW 0 #define PCI_BUS_BRIDGE_MEM_WINDOW 1 #define PCI_BUS_BRIDGE_PREF_MEM_WINDOW 2 --=20 2.34.1