From nobody Mon Dec 1 21:30:54 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 085C4255F31; Mon, 1 Dec 2025 11:22:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588133; cv=none; b=WsCZo0VoARrlKbzjylkAUs+vgLZrXc3zjyCaBKXJmAWwmTYrS8gyYU+rCgnWW19J6h9H4HwwqDVhYEsiy6fsckCWGDWIoKRhDJ9O9JaYGsA4hB1IEiz0EtXqkvvYkeBDA8Fzd0/RbBspi3dR4hZIEc92qsOGqKQkrFAp3AGE6HE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588133; c=relaxed/simple; bh=WzPIT7JrkPATOGEn6EDeq+ISNkYbUEBxIuW8y7cUFbg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MiQFyYI8GfBXukc2aHfgGQBbEeep0Q+Sf++/rMC4CLj5MDnzTRA0HewP4TxD7C7wMAejHHtrG4rUA5C926KgHcPznjTziUiykXBvCmtBv53AGF53Ci4JIuPCVGJ5qr0BIa0yiING9SqVzxl7qnAvdRgbnzVoPmiIy/UT4EXJsQY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D39701595; Mon, 1 Dec 2025 03:22:03 -0800 (PST) Received: from e132581.arm.com (e132581.arm.com [10.1.196.87]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B23FC3F59E; Mon, 1 Dec 2025 03:22:08 -0800 (PST) From: Leo Yan Date: Mon, 01 Dec 2025 11:21:51 +0000 Subject: [PATCH 01/19] coresight: trbe: Use helpers for checking errata Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251201-trbe_buffer_refactor_v1-1-v1-1-7da32b076b28@arm.com> References: <20251201-trbe_buffer_refactor_v1-1-v1-0-7da32b076b28@arm.com> In-Reply-To: <20251201-trbe_buffer_refactor_v1-1-v1-0-7da32b076b28@arm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Anshuman Khandual , Yeoreum Yun , Will Deacon , Mark Rutland , Tamas Petz , Tamas Zsoldos , Arnaldo Carvalho de Melo , Namhyung Kim , Jiri Olsa , Ian Rogers , Adrian Hunter Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Leo Yan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764588125; l=1969; i=leo.yan@arm.com; s=20250604; h=from:subject:message-id; bh=WzPIT7JrkPATOGEn6EDeq+ISNkYbUEBxIuW8y7cUFbg=; b=6YaGZArGMrS7ML/KajEPsrZHMzjRZMdzjMsh9THC9ulWERs8ss1yDgMpkkmrHqS4OsYaWKrUD AHKWQAbvmHGBT8OuWGN6d7Z9suNVa+z29sH6HVky3wjkVcKXejOb6h8 X-Developer-Key: i=leo.yan@arm.com; a=ed25519; pk=k4BaDbvkCXzBFA7Nw184KHGP5thju8lKqJYIrOWxDhI= Use the existed helpers for checking errata instead of open coded equivalent. Signed-off-by: Leo Yan --- drivers/hwtracing/coresight/coresight-trbe.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtraci= ng/coresight/coresight-trbe.c index 293715b4ff0eb0abe30f9b477700ca94f81cd4a2..0ddb3db0213cf0014e29decfb79= da68b0a351b31 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -723,7 +723,7 @@ static unsigned long trbe_get_trace_size(struct perf_ou= tput_handle *handle, * the space we skipped with IGNORE packets. And we are always * guaranteed to have at least a PAGE_SIZE space in the buffer. */ - if (trbe_has_erratum(buf->cpudata, TRBE_WORKAROUND_OVERWRITE_FILL_MODE) && + if (trbe_may_overwrite_in_fill_mode(buf->cpudata) && !WARN_ON(size < overwrite_skip)) __trbe_pad_buf(buf, start_off, overwrite_skip); =20 @@ -946,7 +946,7 @@ static int trbe_apply_work_around_before_enable(struct = trbe_buf *buf) * - At trace collection: * - Pad the 256bytes skipped above again with IGNORE packets. */ - if (trbe_has_erratum(buf->cpudata, TRBE_WORKAROUND_OVERWRITE_FILL_MODE)) { + if (trbe_may_overwrite_in_fill_mode(buf->cpudata)) { if (WARN_ON(!IS_ALIGNED(buf->trbe_write, PAGE_SIZE))) return -EINVAL; buf->trbe_hw_base =3D buf->trbe_write; @@ -970,7 +970,7 @@ static int trbe_apply_work_around_before_enable(struct = trbe_buf *buf) * - Adjust the TRBLIMITR.LIMIT to leave the extra PAGE outside * the TRBE's range (i.e [TRBBASER, TRBLIMITR.LIMI] ). */ - if (trbe_has_erratum(buf->cpudata, TRBE_WORKAROUND_WRITE_OUT_OF_RANGE)) { + if (trbe_may_write_out_of_range(buf->cpudata)) { s64 space =3D buf->trbe_limit - buf->trbe_write; /* * We must have more than a PAGE_SIZE worth space in the proposed --=20 2.34.1 From nobody Mon Dec 1 21:30:54 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id AC00825B662; Mon, 1 Dec 2025 11:22:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588137; cv=none; b=fHqQY0VZinrsBq+8zsr2XMXWZN8tMROlupKlvJH+688zgGQXW25fK3QDQsDZc7Ds/owQKV2Ukl0ykQJrMyHulbeK1RoJ+1iUUHaxuPsDKdoRATSd0gg26+06DdvnuVQfyWAF8n+VYVuX4LYyfK8sQPbavKTUU7UGXkjir1Jyjdg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588137; c=relaxed/simple; bh=LVlL57O5P5f7MwWK5l7g8QTDQyd/AvEeHETO4d4e2Ps=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=s8hxLvqX9z63kZns+2lFsHoyU81E4U1PDDGQjJnqd1cnwRWK+mDHVMst84BxxCOX08EUU0wINN5NUuYzb5jv8tfUOqlioQ9WAE/ynGtZtC6eqsO2pO3pAANkEZD+ngISPX6YSLoPNWBdoOs/bXeu9pKrwbALRt8TrLA4EgUxweE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A143B153B; Mon, 1 Dec 2025 03:22:06 -0800 (PST) Received: from e132581.arm.com (e132581.arm.com [10.1.196.87]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 805AB3F59E; Mon, 1 Dec 2025 03:22:11 -0800 (PST) From: Leo Yan Date: Mon, 01 Dec 2025 11:21:52 +0000 Subject: [PATCH 02/19] coresight: trbe: Remove redundant disable operation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251201-trbe_buffer_refactor_v1-1-v1-2-7da32b076b28@arm.com> References: <20251201-trbe_buffer_refactor_v1-1-v1-0-7da32b076b28@arm.com> In-Reply-To: <20251201-trbe_buffer_refactor_v1-1-v1-0-7da32b076b28@arm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Anshuman Khandual , Yeoreum Yun , Will Deacon , Mark Rutland , Tamas Petz , Tamas Zsoldos , Arnaldo Carvalho de Melo , Namhyung Kim , Jiri Olsa , Ian Rogers , Adrian Hunter Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Leo Yan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764588125; l=2104; i=leo.yan@arm.com; s=20250604; h=from:subject:message-id; bh=LVlL57O5P5f7MwWK5l7g8QTDQyd/AvEeHETO4d4e2Ps=; b=RpodhpxKvSfrsVziIYFhBHNuTW4TcjqOsI2+VAr7kwEFjn4Vb6bkxQ253NbM7fqnMsHaGEGHR zATlaMhkjzpDuIQ/+wXvqc+ZA5nKyeDYzZ5bqIQdpyoe8z14OWmxV+H X-Developer-Key: i=leo.yan@arm.com; a=ed25519; pk=k4BaDbvkCXzBFA7Nw184KHGP5thju8lKqJYIrOWxDhI= The trace unit is already disabled when trbe_stop_and_truncate_event() is called, so draining and stopping the buffer in the function is redundant. Remove the unnecessary disable operation and rename the function to trbe_truncate_event() to better reflect its purpose. Signed-off-by: Leo Yan --- drivers/hwtracing/coresight/coresight-trbe.c | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtraci= ng/coresight/coresight-trbe.c index 0ddb3db0213cf0014e29decfb79da68b0a351b31..2f44e4a65e0ee2b2c8fdd06a51a= b01fc57f44a4e 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -284,18 +284,10 @@ static void trbe_report_wrap_event(struct perf_output= _handle *handle) perf_aux_output_flag(handle, PERF_AUX_FLAG_COLLISION); } =20 -static void trbe_stop_and_truncate_event(struct perf_output_handle *handle) +static void trbe_truncate_event(struct perf_output_handle *handle) { struct trbe_buf *buf =3D etm_perf_sink_config(handle); =20 - /* - * We cannot proceed with the buffer collection and we - * do not have any data for the current session. The - * etm_perf driver expects to close out the aux_buffer - * at event_stop(). So disable the TRBE here and leave - * the update_buffer() to return a 0 size. - */ - trbe_drain_and_disable_local(buf->cpudata); perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED); perf_aux_output_end(handle, 0); *this_cpu_ptr(buf->cpudata->drvdata->handle) =3D NULL; @@ -1008,7 +1000,7 @@ static int __arm_trbe_enable(struct trbe_buf *buf, trbe_enable_hw(buf); return 0; err: - trbe_stop_and_truncate_event(handle); + trbe_truncate_event(handle); return ret; } =20 @@ -1169,7 +1161,7 @@ static irqreturn_t arm_trbe_irq_handler(int irq, void= *dev) trbe_handle_spurious(handle); break; case TRBE_FAULT_ACT_FATAL: - trbe_stop_and_truncate_event(handle); + trbe_truncate_event(handle); truncated =3D true; break; } --=20 2.34.1 From nobody Mon Dec 1 21:30:54 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 52E382522B6; Mon, 1 Dec 2025 11:22:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588138; cv=none; b=rjQL1cE9F5and33FDzG8ndZGzVhFD2BWPtkM/jdZWva0ox0VmfmJQX1dF91binxgB3ytfHGYPNVZunbOgm/rQa2CmAmmSFpeI3yuFu8eGi83ZIpfh6lXSDOnX3IowioFhJ+a8n0s2xJ8fIG6zIRnuV3+WHr/nQ8s9MDyV8WdTKY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588138; c=relaxed/simple; bh=VfCA2xij8QWg5fgbHHGPURuv0el1gynI6szJM+HB2gM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qp9tc9j2OilAGy6FJBleYYrms6Qw5i8R8ovACq5YlSJIkj0BQYUHkfbkGp8T1/47UKcEmNqhPmxUkO4evQZIn+T3WOWsxnWMvroeHMksD8lA1WQ5GswI+JRUdqgC5zGsGbeA6KTWnkQYeCxELB8QVgRnc4+ZYKRCfAx+TxLh8oA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6A7E01595; Mon, 1 Dec 2025 03:22:09 -0800 (PST) Received: from e132581.arm.com (e132581.arm.com [10.1.196.87]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4DDCB3F59E; Mon, 1 Dec 2025 03:22:14 -0800 (PST) From: Leo Yan Date: Mon, 01 Dec 2025 11:21:53 +0000 Subject: [PATCH 03/19] coresight: trbe: Remove buffer disabling in trbe_handle_overflow() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251201-trbe_buffer_refactor_v1-1-v1-3-7da32b076b28@arm.com> References: <20251201-trbe_buffer_refactor_v1-1-v1-0-7da32b076b28@arm.com> In-Reply-To: <20251201-trbe_buffer_refactor_v1-1-v1-0-7da32b076b28@arm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Anshuman Khandual , Yeoreum Yun , Will Deacon , Mark Rutland , Tamas Petz , Tamas Zsoldos , Arnaldo Carvalho de Melo , Namhyung Kim , Jiri Olsa , Ian Rogers , Adrian Hunter Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Leo Yan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764588125; l=915; i=leo.yan@arm.com; s=20250604; h=from:subject:message-id; bh=VfCA2xij8QWg5fgbHHGPURuv0el1gynI6szJM+HB2gM=; b=NvAsNFDv9EktNPgNlt7jE4Vq/oSojP7+Zpm263ij1qv1aKjw9OdZ8wn5/U+WsXIYyLxV6Tg3h MBbs3Y9nF7nAHA8KocPCKyG6btzGt3FDSCrNGhjQ12VNAYoSLGxxsL/ X-Developer-Key: i=leo.yan@arm.com; a=ed25519; pk=k4BaDbvkCXzBFA7Nw184KHGP5thju8lKqJYIrOWxDhI= When trbe_handle_overflow() runs, the buffer has already been disabled and drained, so the duplicate operation is unnecessary. Remove it. Signed-off-by: Leo Yan --- drivers/hwtracing/coresight/coresight-trbe.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtraci= ng/coresight/coresight-trbe.c index 2f44e4a65e0ee2b2c8fdd06a51ab01fc57f44a4e..f5597bd9b5fba9a8f5053d5823b= 03380fd468b5c 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -1077,7 +1077,6 @@ static int trbe_handle_overflow(struct perf_output_ha= ndle *handle) * is able to detect this with a disconnected handle * (handle->event =3D NULL). */ - trbe_drain_and_disable_local(buf->cpudata); *this_cpu_ptr(buf->cpudata->drvdata->handle) =3D NULL; return -EINVAL; } --=20 2.34.1 From nobody Mon Dec 1 21:30:54 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 35BDE3081D8; Mon, 1 Dec 2025 11:22:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588141; cv=none; b=llEapL4maaXDE9efZOAu5pfn6ISzRSCGrEsOeogFkyJt9l95c5vOIbu4eDDuCIpw7SbXVjimWHIQKERxXbErHjUzkrhVz9MJNdsRyu+rYxUNYLZBT8vcHiuaguQFpYpc2JvG9RAeNDJUGNswdILdtktUOHSUYa83UwOsOoJs3vg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588141; c=relaxed/simple; bh=rwVi7zeVOB5lCUwpbBU1QGzW3dLjviyCuoRWQcOnTXc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PPYfQPFxHs5aTwPwoq0wDMO5x7Dv4ktmguJr8ZV4dtxQQJPBkdpY0FwdWi/K5+vtLBCnI7pR0RdPHa7WNstbJ1g0Blw/IF1YNtV1U2G3BflGjEnshcS2am2XITBfQJ3Kh8mjirpsVoahkghsaxX0rBGby6V+3O9pQKkz2xIN4GU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 37C4F153B; Mon, 1 Dec 2025 03:22:12 -0800 (PST) Received: from e132581.arm.com (e132581.arm.com [10.1.196.87]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1A1423F59E; Mon, 1 Dec 2025 03:22:16 -0800 (PST) From: Leo Yan Date: Mon, 01 Dec 2025 11:21:54 +0000 Subject: [PATCH 04/19] coresight: trbe: Remove set_trbe_disabled() from the enable flow Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251201-trbe_buffer_refactor_v1-1-v1-4-7da32b076b28@arm.com> References: <20251201-trbe_buffer_refactor_v1-1-v1-0-7da32b076b28@arm.com> In-Reply-To: <20251201-trbe_buffer_refactor_v1-1-v1-0-7da32b076b28@arm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Anshuman Khandual , Yeoreum Yun , Will Deacon , Mark Rutland , Tamas Petz , Tamas Zsoldos , Arnaldo Carvalho de Melo , Namhyung Kim , Jiri Olsa , Ian Rogers , Adrian Hunter Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Leo Yan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764588125; l=995; i=leo.yan@arm.com; s=20250604; h=from:subject:message-id; bh=rwVi7zeVOB5lCUwpbBU1QGzW3dLjviyCuoRWQcOnTXc=; b=byRbhSXOveTKDzaZ6UfsBWqNMZLzd5c09kdE4FJAAR83fUUILgQ6dH7iEJgIYK7SVLuqRvmiR AJBg9vHJgk0BRv30MlxVjW2mCg43KL5W0mXtjeU+k8b7JgnpuVfWeWm X-Developer-Key: i=leo.yan@arm.com; a=ed25519; pk=k4BaDbvkCXzBFA7Nw184KHGP5thju8lKqJYIrOWxDhI= set_trbe_disabled() should never appear in the enable flow, otherwise, it may potentially hide bugs in the disable flow. Remove set_trbe_disabled() from the enable path. Signed-off-by: Leo Yan --- drivers/hwtracing/coresight/coresight-trbe.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtraci= ng/coresight/coresight-trbe.c index f5597bd9b5fba9a8f5053d5823b03380fd468b5c..e426991e2c2c398a9d3982e9d0f= 7f542e404cbab 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -629,7 +629,6 @@ static void trbe_enable_hw(struct trbe_buf *buf) WARN_ON(buf->trbe_hw_base < buf->trbe_base); WARN_ON(buf->trbe_write < buf->trbe_hw_base); WARN_ON(buf->trbe_write >=3D buf->trbe_limit); - set_trbe_disabled(buf->cpudata); clr_trbe_status(); set_trbe_base_pointer(buf->trbe_hw_base); set_trbe_write_pointer(buf->trbe_write); --=20 2.34.1 From nobody Mon Dec 1 21:30:54 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3664E308F28; Mon, 1 Dec 2025 11:22:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588144; cv=none; b=vFQ2F4KLHOeAngYihY7ezlabvOHTqPWQNjDoxTSegBB64KJtg0Ki8+f4CQesiOhHGeQ3yDg3jmhM43Q0WvXjHNQftKVLrj6hJdDmYL98wt3J26fyGvChNzEDcJCkL9i2nXwjAJhmPwMyUzOto1rH90igwR/1ijhjyhHR1tDDM5c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588144; c=relaxed/simple; bh=lB/NC74zZrDVCqfwFSRLgRpttiHzTgZXwBAD9mmFzVM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=n7/afdw0SUzJNBV02Hoayo51d/undo/svNPPaqxaPb52Fna6o5LChIWr5ZUo6jwciHeLL/NC6fV4cIqIbBs6KCq/7ZaZ+8uWC20JHOzFf8/JSjLs9+tSVX+U5r1IyYrny26LI9CjtcIv/ffVnmHjhR/Eif3IHfWoUU1FODk3V2s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 04AC9153B; Mon, 1 Dec 2025 03:22:15 -0800 (PST) Received: from e132581.arm.com (e132581.arm.com [10.1.196.87]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DB5B23F59E; Mon, 1 Dec 2025 03:22:19 -0800 (PST) From: Leo Yan Date: Mon, 01 Dec 2025 11:21:55 +0000 Subject: [PATCH 05/19] coresight: trbe: Refactor status clearing Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251201-trbe_buffer_refactor_v1-1-v1-5-7da32b076b28@arm.com> References: <20251201-trbe_buffer_refactor_v1-1-v1-0-7da32b076b28@arm.com> In-Reply-To: <20251201-trbe_buffer_refactor_v1-1-v1-0-7da32b076b28@arm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Anshuman Khandual , Yeoreum Yun , Will Deacon , Mark Rutland , Tamas Petz , Tamas Zsoldos , Arnaldo Carvalho de Melo , Namhyung Kim , Jiri Olsa , Ian Rogers , Adrian Hunter Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Leo Yan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764588125; l=1736; i=leo.yan@arm.com; s=20250604; h=from:subject:message-id; bh=lB/NC74zZrDVCqfwFSRLgRpttiHzTgZXwBAD9mmFzVM=; b=IeoS+fXPb5TGOyYZgypSVdCG859ipU9WOW5rq3/di9udWyJqYqCiH3YljHwdz/NfPitGMPKfa nqSNvOFWDvrCzkIpXQ5osHvR5/dWyClsHnW/Tnr+sdyCr4DvqEBKZBH X-Developer-Key: i=leo.yan@arm.com; a=ed25519; pk=k4BaDbvkCXzBFA7Nw184KHGP5thju8lKqJYIrOWxDhI= If the driver does not clear the status when disabling the trace buffer unit, stale state will carry over to the next enable, though the driver clears it again on enable. Explicitly clear status after the trace is disabled in the interrupt handling and when a perf session ends. Keep the status for spurious interrupts for continuous tracing. Signed-off-by: Leo Yan --- drivers/hwtracing/coresight/coresight-trbe.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtraci= ng/coresight/coresight-trbe.c index e426991e2c2c398a9d3982e9d0f7f542e404cbab..9e565122816949b37b8ff5e4ba0= 4cfbc317c6f25 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -629,7 +629,6 @@ static void trbe_enable_hw(struct trbe_buf *buf) WARN_ON(buf->trbe_hw_base < buf->trbe_base); WARN_ON(buf->trbe_write < buf->trbe_hw_base); WARN_ON(buf->trbe_write >=3D buf->trbe_limit); - clr_trbe_status(); set_trbe_base_pointer(buf->trbe_hw_base); set_trbe_write_pointer(buf->trbe_write); =20 @@ -1036,6 +1035,8 @@ static int arm_trbe_disable(struct coresight_device *= csdev) return -EINVAL; =20 trbe_drain_and_disable_local(cpudata); + clr_trbe_status(); + buf->cpudata =3D NULL; cpudata->buf =3D NULL; cpudata->mode =3D CS_MODE_DISABLED; @@ -1151,6 +1152,10 @@ static irqreturn_t arm_trbe_irq_handler(int irq, voi= d *dev) return IRQ_NONE; =20 act =3D trbe_get_fault_act(handle, status); + + if (act !=3D TRBE_FAULT_ACT_SPURIOUS) + clr_trbe_status(); + switch (act) { case TRBE_FAULT_ACT_WRAP: truncated =3D !!trbe_handle_overflow(handle); --=20 2.34.1 From nobody Mon Dec 1 21:30:54 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DD0ED2E5D17; Mon, 1 Dec 2025 11:22:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588147; cv=none; b=IVaBrCYRZ3dwkCBXqpBiOvfH1AYVVVluGkL0NNz/Gk22S9fj6bCJfwvBxrlSIqxtqRT02FT7J8EhZRyCYd8vPQjraXMeMDGGx+uSJ8yHEjPA1hzvVosyGZ+eViMcIhT4b58wjA1daXqD5SvDYs/37VwBqsBVfIfxJpIqF8ACfqo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588147; c=relaxed/simple; bh=rS7n6GqYxBhjQifAmikJPjJWBJ0+WduJEB52j0HxrUc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=eg4cdltKMHXo2fmNZpOUFhSFKsxeQ3M7MgsjB4ogYh5vSdBbYGfYQjFiesMYqQuSI8DHP0Hdr7YkwoNVqhufUF/ls6y6dPZ5VFbygTJkqAPdocAFsCQpk0HTSFwXKeVwfgALFfP9l26iG6+1WTUO/YAY/N2qFBaSHyBwadcXW5A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C6BA3153B; Mon, 1 Dec 2025 03:22:17 -0800 (PST) Received: from e132581.arm.com (e132581.arm.com [10.1.196.87]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A89F83F59E; Mon, 1 Dec 2025 03:22:22 -0800 (PST) From: Leo Yan Date: Mon, 01 Dec 2025 11:21:56 +0000 Subject: [PATCH 06/19] coresight: trbe: Refactor syndrome decoding Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251201-trbe_buffer_refactor_v1-1-v1-6-7da32b076b28@arm.com> References: <20251201-trbe_buffer_refactor_v1-1-v1-0-7da32b076b28@arm.com> In-Reply-To: <20251201-trbe_buffer_refactor_v1-1-v1-0-7da32b076b28@arm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Anshuman Khandual , Yeoreum Yun , Will Deacon , Mark Rutland , Tamas Petz , Tamas Zsoldos , Arnaldo Carvalho de Melo , Namhyung Kim , Jiri Olsa , Ian Rogers , Adrian Hunter Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Leo Yan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764588125; l=4359; i=leo.yan@arm.com; s=20250604; h=from:subject:message-id; bh=rS7n6GqYxBhjQifAmikJPjJWBJ0+WduJEB52j0HxrUc=; b=j2R99VhM0xRCEGs9Df6BspIDlCsqEPA0TdAW9zgg7opexB+TMQv2IZXgjHuEHaqsxSf8Rfn+0 siZbfpHRgTVA2u0tY12czMXtmPRWBTWMLKT9N+FT+TZqLe27g92sSq0 X-Developer-Key: i=leo.yan@arm.com; a=ed25519; pk=k4BaDbvkCXzBFA7Nw184KHGP5thju8lKqJYIrOWxDhI= It gives priority to TRBSR_EL1.EA (external abort); an external abort will immediately bail out and return an error. Next, the syndrome decoding is refactored based on two levels of information: the EC (Event Class) bits and the BSC (Trace Buffer Status Code) bits. If TRBSR_EL1.EC=3D=3D0b000000, the driver continues parsing TRBSR_EL1.BSC to identify the specific trace buffer event. Otherwise, any non-zero TRBSR_EL1.EC is treated as an error. For error cases, the driver prints an error string and dumps registers for debugging. No additional checks are required for wrap mode beyond verifying the TRBSR_EL1.WRAP bit, even on units with overwrite errata, as this bit reliably indicates a buffer wrap. Signed-off-by: Leo Yan --- drivers/hwtracing/coresight/coresight-trbe.c | 60 +++++++++++++++++++++---= ---- drivers/hwtracing/coresight/coresight-trbe.h | 8 ++-- 2 files changed, 51 insertions(+), 17 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtraci= ng/coresight/coresight-trbe.c index 9e565122816949b37b8ff5e4ba04cfbc317c6f25..28e2bfa68074f19ccaa4a737d00= af577aea818fe 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -643,29 +643,61 @@ static void trbe_enable_hw(struct trbe_buf *buf) static enum trbe_fault_action trbe_get_fault_act(struct perf_output_handle= *handle, u64 trbsr) { + const char *err_str; int ec =3D get_trbe_ec(trbsr); int bsc =3D get_trbe_bsc(trbsr); - struct trbe_buf *buf =3D etm_perf_sink_config(handle); - struct trbe_cpudata *cpudata =3D buf->cpudata; =20 WARN_ON(is_trbe_running(trbsr)); - if (is_trbe_trg(trbsr) || is_trbe_abort(trbsr)) - return TRBE_FAULT_ACT_FATAL; =20 - if ((ec =3D=3D TRBE_EC_STAGE1_ABORT) || (ec =3D=3D TRBE_EC_STAGE2_ABORT)) - return TRBE_FAULT_ACT_FATAL; + if (is_trbe_abort(trbsr)) { + err_str =3D "External abort"; + goto out_fatal; + } =20 - /* - * If the trbe is affected by TRBE_WORKAROUND_OVERWRITE_FILL_MODE, - * it might write data after a WRAP event in the fill mode. - * Thus the check TRBPTR =3D=3D TRBBASER will not be honored. - */ - if ((is_trbe_wrap(trbsr) && (ec =3D=3D TRBE_EC_OTHERS) && (bsc =3D=3D TRB= E_BSC_FILLED)) && - (trbe_may_overwrite_in_fill_mode(cpudata) || - get_trbe_write_pointer() =3D=3D get_trbe_base_pointer())) + switch (ec) { + case TRBE_EC_OTHERS: + break; + case TRBE_EC_BUF_MGMT_IMPL: + err_str =3D "Unexpected implemented management"; + goto out_fatal; + case TRBE_EC_GP_CHECK_FAULT: + err_str =3D "Granule Protection Check fault"; + goto out_fatal; + case TRBE_EC_STAGE1_ABORT: + err_str =3D "Stage 1 data abort"; + goto out_fatal; + case TRBE_EC_STAGE2_ABORT: + err_str =3D "Stage 2 data abort"; + goto out_fatal; + default: + err_str =3D "Unknown error code"; + goto out_fatal; + } + + switch (bsc) { + case TRBE_BSC_NOT_STOPPED: + break; + case TRBE_BSC_FILLED: + break; + case TRBE_BSC_TRIGGERED: + err_str =3D "Unexpected trigger status"; + goto out_fatal; + default: + err_str =3D "Unexpected buffer status code"; + goto out_fatal; + } + + if (is_trbe_wrap(trbsr)) return TRBE_FAULT_ACT_WRAP; =20 return TRBE_FAULT_ACT_SPURIOUS; + +out_fatal: + pr_err_ratelimited("%s on CPU %d [TRBSR=3D0x%016llx, TRBPTR=3D0x%016llx, = TRBLIMITR=3D0x%016llx]\n", + err_str, smp_processor_id(), trbsr, + read_sysreg_s(SYS_TRBPTR_EL1), + read_sysreg_s(SYS_TRBLIMITR_EL1)); + return TRBE_FAULT_ACT_FATAL; } =20 static unsigned long trbe_get_trace_size(struct perf_output_handle *handle, diff --git a/drivers/hwtracing/coresight/coresight-trbe.h b/drivers/hwtraci= ng/coresight/coresight-trbe.h index 45202c48accec7c86ba56130e2737bc2d1830fae..d7f7cd763c0c7139cf322b7336e= e563073e3bea0 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.h +++ b/drivers/hwtracing/coresight/coresight-trbe.h @@ -35,9 +35,11 @@ static inline bool is_trbe_enabled(void) return trblimitr & TRBLIMITR_EL1_E; } =20 -#define TRBE_EC_OTHERS 0 -#define TRBE_EC_STAGE1_ABORT 36 -#define TRBE_EC_STAGE2_ABORT 37 +#define TRBE_EC_OTHERS 0x0 +#define TRBE_EC_GP_CHECK_FAULT 0X1e +#define TRBE_EC_BUF_MGMT_IMPL 0x1f +#define TRBE_EC_STAGE1_ABORT 0x24 +#define TRBE_EC_STAGE2_ABORT 0x25 =20 static inline int get_trbe_ec(u64 trbsr) { --=20 2.34.1 From nobody Mon Dec 1 21:30:54 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 675023093A7; Mon, 1 Dec 2025 11:22:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588150; cv=none; b=AN+HKr3mxERo8wR6PHmz/b3Lqn2GVJTSNxx4na6usHl0q5XY6VCBlb/ggypJbVByMlms21tKlS0Cm7ixhoWlOzLpFdAq9uKKxf5dWXJziU7qqcNUbJdGFpuD50FjJ5CWKSVDbYFpBqa3vsYKuYxojRfZZr+26dKEMoZRV+o5FvE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588150; c=relaxed/simple; bh=W/JeYnunOoLhYN6hczuLJvjEZ+swqNz13PSBPwFvoT8=; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251201-trbe_buffer_refactor_v1-1-v1-7-7da32b076b28@arm.com> References: <20251201-trbe_buffer_refactor_v1-1-v1-0-7da32b076b28@arm.com> In-Reply-To: <20251201-trbe_buffer_refactor_v1-1-v1-0-7da32b076b28@arm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Anshuman Khandual , Yeoreum Yun , Will Deacon , Mark Rutland , Tamas Petz , Tamas Zsoldos , Arnaldo Carvalho de Melo , Namhyung Kim , Jiri Olsa , Ian Rogers , Adrian Hunter Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Leo Yan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764588125; l=3290; i=leo.yan@arm.com; s=20250604; h=from:subject:message-id; bh=W/JeYnunOoLhYN6hczuLJvjEZ+swqNz13PSBPwFvoT8=; b=49j4rwio/yVC2wwPB9Z9UiUECEUH03HHUoBb3VifuBNB8Y+ISShfg7DiQ4nBoshKwWSux9vlm TWhR+mz3crPCd5r1VNehnxNPG5t14B+GOOMRrPM/R8VEmlDUI1ARPhp X-Developer-Key: i=leo.yan@arm.com; a=ed25519; pk=k4BaDbvkCXzBFA7Nw184KHGP5thju8lKqJYIrOWxDhI= Rather than spreading AUX flag setting in different functions, use trbe_get_fault_act() as a central place for setting the flag. Later we will support WRAP mode with continuous trace, so the WRAP event does not necessarily cause the trace discontinuity, change to check the stop status instead. Signed-off-by: Leo Yan --- drivers/hwtracing/coresight/coresight-trbe.c | 38 +++++++++++++-----------= ---- 1 file changed, 17 insertions(+), 21 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtraci= ng/coresight/coresight-trbe.c index 28e2bfa68074f19ccaa4a737d00af577aea818fe..b06885a08e082fd34f68d958851= 8807b5c47c86e 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -265,25 +265,6 @@ static void trbe_reset_local(struct trbe_cpudata *cpud= ata) write_sysreg_s(0, SYS_TRBSR_EL1); } =20 -static void trbe_report_wrap_event(struct perf_output_handle *handle) -{ - /* - * Mark the buffer to indicate that there was a WRAP event by - * setting the COLLISION flag. This indicates to the user that - * the TRBE trace collection was stopped without stopping the - * ETE and thus there might be some amount of trace that was - * lost between the time the WRAP was detected and the IRQ - * was consumed by the CPU. - * - * Setting the TRUNCATED flag would move the event to STOPPED - * state unnecessarily, even when there is space left in the - * ring buffer. Using the COLLISION flag doesn't have this side - * effect. We only set TRUNCATED flag when there is no space - * left in the ring buffer. - */ - perf_aux_output_flag(handle, PERF_AUX_FLAG_COLLISION); -} - static void trbe_truncate_event(struct perf_output_handle *handle) { struct trbe_buf *buf =3D etm_perf_sink_config(handle); @@ -687,6 +668,23 @@ static enum trbe_fault_action trbe_get_fault_act(struc= t perf_output_handle *hand goto out_fatal; } =20 + /* + * Mark the buffer to indicate that there was a WRAP event by + * setting the COLLISION flag. This indicates to the user that + * the TRBE trace collection was stopped without stopping the + * ETE and thus there might be some amount of trace that was + * lost between the time the WRAP was detected and the IRQ + * was consumed by the CPU. + * + * Setting the TRUNCATED flag would move the event to STOPPED + * state unnecessarily, even when there is space left in the + * ring buffer. Using the COLLISION flag doesn't have this side + * effect. We only set TRUNCATED flag when there is no space + * left in the ring buffer. + */ + if (!is_trbe_running(trbsr)) + perf_aux_output_flag(handle, PERF_AUX_FLAG_COLLISION); + if (is_trbe_wrap(trbsr)) return TRBE_FAULT_ACT_WRAP; =20 @@ -878,7 +876,6 @@ static unsigned long arm_trbe_update_buffer(struct core= sight_device *csdev, goto done; } =20 - trbe_report_wrap_event(handle); wrap =3D true; } =20 @@ -1099,7 +1096,6 @@ static int trbe_handle_overflow(struct perf_output_ha= ndle *handle) if (buf->snapshot) handle->head +=3D size; =20 - trbe_report_wrap_event(handle); perf_aux_output_end(handle, size); event_data =3D perf_aux_output_begin(handle, event); if (!event_data) { --=20 2.34.1 From nobody Mon Dec 1 21:30:54 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5DCEE309EE3; Mon, 1 Dec 2025 11:22:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588152; cv=none; b=VWQwujOhfswP2yQLDAXeBNSrgcFv+qdjv82NUtd/xDAbDKjpSsz8VSkTb7yJ+7oITwfan+LCSy7tmKKDmjpVMnG2ZnuSigluBU/0gOYlMYjruQrf3q7UgcTwIwB82W1/m+S9yU5InGR+XfoYEpiZNUNmFSmX07DtAhu9ui/twVQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588152; c=relaxed/simple; bh=45Ukm1pq3z+aAFJGvQBiBA1GyyPqXQWhw0CPZGZjIh8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QRrNza3YUyJFTPm+tyr2AswiaSAEtGgq5vikP61jX81Kx/RsaufBBXUaHWLfvCSkxGIIHZun/bSgbedYv2JVOhz9NZAoc3UULtwebiaTnAvxXQ9ZWKVKAgDUgheic9Yudo9WAPBLzmLaZAmLScrVTt3lhacqJBN0LFxJ/sIQfQY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6420C1595; Mon, 1 Dec 2025 03:22:23 -0800 (PST) Received: from e132581.arm.com (e132581.arm.com [10.1.196.87]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 44CCA3F59E; Mon, 1 Dec 2025 03:22:28 -0800 (PST) From: Leo Yan Date: Mon, 01 Dec 2025 11:21:58 +0000 Subject: [PATCH 08/19] coresight: trbe: Use PERF_AUX_FLAG_PARTIAL instead of PERF_AUX_FLAG_COLLISION Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251201-trbe_buffer_refactor_v1-1-v1-8-7da32b076b28@arm.com> References: <20251201-trbe_buffer_refactor_v1-1-v1-0-7da32b076b28@arm.com> In-Reply-To: <20251201-trbe_buffer_refactor_v1-1-v1-0-7da32b076b28@arm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Anshuman Khandual , Yeoreum Yun , Will Deacon , Mark Rutland , Tamas Petz , Tamas Zsoldos , Arnaldo Carvalho de Melo , Namhyung Kim , Jiri Olsa , Ian Rogers , Adrian Hunter Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Leo Yan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764588125; l=2104; i=leo.yan@arm.com; s=20250604; h=from:subject:message-id; bh=45Ukm1pq3z+aAFJGvQBiBA1GyyPqXQWhw0CPZGZjIh8=; b=rv8WJ/wDAP2cVLXQAucOIQ4EXKHQSz3w7jwIFos9rHOyjzA5djR1DbHPp8dhlSMqvqQTqPf4D EaUSOON1dr7BGqkzwUyKzCvEq4yAyZ2fgRMWU7HlzH5QRSKSawtHDUE X-Developer-Key: i=leo.yan@arm.com; a=ed25519; pk=k4BaDbvkCXzBFA7Nw184KHGP5thju8lKqJYIrOWxDhI= When tracing stops, there is no collision with other samples, so using PERF_AUX_FLAG_COLLISION does not accurately reflect the trace state and may mislead userspace. Use PERF_AUX_FLAG_PARTIAL instead to indicate that tracing stopped and the record may contain gaps. Signed-off-by: Leo Yan --- drivers/hwtracing/coresight/coresight-trbe.c | 19 ++++++------------- 1 file changed, 6 insertions(+), 13 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtraci= ng/coresight/coresight-trbe.c index b06885a08e082fd34f68d9588518807b5c47c86e..0caa4a6b437a3aa39fc6bcc72a2= 3711b54f7c598 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -669,21 +669,14 @@ static enum trbe_fault_action trbe_get_fault_act(stru= ct perf_output_handle *hand } =20 /* - * Mark the buffer to indicate that there was a WRAP event by - * setting the COLLISION flag. This indicates to the user that - * the TRBE trace collection was stopped without stopping the - * ETE and thus there might be some amount of trace that was - * lost between the time the WRAP was detected and the IRQ - * was consumed by the CPU. - * - * Setting the TRUNCATED flag would move the event to STOPPED - * state unnecessarily, even when there is space left in the - * ring buffer. Using the COLLISION flag doesn't have this side - * effect. We only set TRUNCATED flag when there is no space - * left in the ring buffer. + * Mark the buffer to indicate that the trace is stopped by setting + * the PARTIAL flag. This indicates to the user that the TRBE trace + * collection was stopped without stopping the ETE and thus there + * might be some amount of trace that was lost between the time the + * TRBE event was detected and the IRQ was consumed by the CPU. */ if (!is_trbe_running(trbsr)) - perf_aux_output_flag(handle, PERF_AUX_FLAG_COLLISION); + perf_aux_output_flag(handle, PERF_AUX_FLAG_PARTIAL); =20 if (is_trbe_wrap(trbsr)) return TRBE_FAULT_ACT_WRAP; --=20 2.34.1 From nobody Mon Dec 1 21:30:54 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3BD0930AACA; Mon, 1 Dec 2025 11:22:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588155; cv=none; b=hqMzkrGB4XSkA+dyDWExsFhqmXPPEZpAYvlotyiqklB4eolZsIJ3aicr23wweQBv3e8HTexMvngI89Ud+5VPubTPxC5Bg6srrQhMy+nCuLFLYFoRJbdw8VYPYYVjgYTTrHk6WKELlX6JdkvelZAeVx0nHKP/ltpdt0BeLTpuMdM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588155; c=relaxed/simple; bh=ksnOW813/iK1sop8lflRXFLjB5lzQz2UyBhXvDajeUw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=f/iAhsW0UVEBB8OVWlJmo27zqrv2V+YsmOMS+ZP0OyOGsHJ7B2xd6CUY8tBa0hEhMl3swqg/yQlUSaMDhsKB+j2zit+84TTI++0HgDNO8mpSHJLNOdEVG6a9QWzeVfU3E+XTBGxMwtOZnY5W+sAkgRA37FyPlzhDJARm54u9Nks= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 35121153B; Mon, 1 Dec 2025 03:22:26 -0800 (PST) Received: from e132581.arm.com (e132581.arm.com [10.1.196.87]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 13E583F59E; Mon, 1 Dec 2025 03:22:30 -0800 (PST) From: Leo Yan Date: Mon, 01 Dec 2025 11:21:59 +0000 Subject: [PATCH 09/19] coresight: trbe: Add fault action argument to trbe_handle_overflow() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251201-trbe_buffer_refactor_v1-1-v1-9-7da32b076b28@arm.com> References: <20251201-trbe_buffer_refactor_v1-1-v1-0-7da32b076b28@arm.com> In-Reply-To: <20251201-trbe_buffer_refactor_v1-1-v1-0-7da32b076b28@arm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Anshuman Khandual , Yeoreum Yun , Will Deacon , Mark Rutland , Tamas Petz , Tamas Zsoldos , Arnaldo Carvalho de Melo , Namhyung Kim , Jiri Olsa , Ian Rogers , Adrian Hunter Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Leo Yan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764588125; l=1665; i=leo.yan@arm.com; s=20250604; h=from:subject:message-id; bh=ksnOW813/iK1sop8lflRXFLjB5lzQz2UyBhXvDajeUw=; b=FymtGmZmDoYUeDSYYDJzHDfusIr5gd+3LCACayX07U7EGpHbpD/+PMIJnWQTugSmTqfH0PXGq LRhPTtr7wwiAxLQTaUOGwzOHMYh5s/lK2CI47ZA0OnwDtEerPJg1MSC X-Developer-Key: i=leo.yan@arm.com; a=ed25519; pk=k4BaDbvkCXzBFA7Nw184KHGP5thju8lKqJYIrOWxDhI= Add a new argument to trbe_handle_overflow() for the fault action, which is used to compare the wrap event for trace size calculation. No functional change intended; this is preparation for a later update. Signed-off-by: Leo Yan --- drivers/hwtracing/coresight/coresight-trbe.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtraci= ng/coresight/coresight-trbe.c index 0caa4a6b437a3aa39fc6bcc72a23711b54f7c598..f56ecdeaa6596afb440e4d53732= e08a85f9bf89d 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -1078,14 +1078,15 @@ static void trbe_handle_spurious(struct perf_output= _handle *handle) set_trbe_enabled(buf->cpudata, trblimitr); } =20 -static int trbe_handle_overflow(struct perf_output_handle *handle) +static int trbe_handle_overflow(struct perf_output_handle *handle, + enum trbe_fault_action act) { struct perf_event *event =3D handle->event; struct trbe_buf *buf =3D etm_perf_sink_config(handle); unsigned long size; struct etm_event_data *event_data; =20 - size =3D trbe_get_trace_size(handle, buf, true); + size =3D trbe_get_trace_size(handle, buf, act =3D=3D TRBE_FAULT_ACT_WRAP); if (buf->snapshot) handle->head +=3D size; =20 @@ -1179,7 +1180,7 @@ static irqreturn_t arm_trbe_irq_handler(int irq, void= *dev) =20 switch (act) { case TRBE_FAULT_ACT_WRAP: - truncated =3D !!trbe_handle_overflow(handle); + truncated =3D !!trbe_handle_overflow(handle, act); break; case TRBE_FAULT_ACT_SPURIOUS: trbe_handle_spurious(handle); --=20 2.34.1 From nobody Mon Dec 1 21:30:54 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B6ABC30AD00; Mon, 1 Dec 2025 11:22:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588158; cv=none; b=YK3G0q34bXkBgXe9uAcE16g280QwMi0bg73p4kFC/O7CrnvgFmoakXQNRa2UI7YGS129G9eeaDaR8BKreHsDYLyEMRHlihDbPSOrob1jBld8aQj4r3AvJp7lCSyYGndi22quKb9anR1/CmjkWb/J+unZnED8II1fBcMMCDvHumo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588158; c=relaxed/simple; bh=19hsKtZvm/XjHbnhnNNNKO3wE2KHI7/1sDLKvI2Gz50=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=tF7/AzSQ09iBE5weYcUS3o1zexPp25UA5FkcfVRb7BTwxwWH6cS8Up610tTu8MOcEqScOhCcpSWSG3onwDl02yu+5sBE36CciTCpM8t0tpK1oTosT4aq2chN5ZPm81LX0kF2EfnP8aDAxeox5M65OvVLzjb7kFxeNBRe94Yat/M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 00A921595; Mon, 1 Dec 2025 03:22:29 -0800 (PST) Received: from e132581.arm.com (e132581.arm.com [10.1.196.87]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D600E3F59E; Mon, 1 Dec 2025 03:22:33 -0800 (PST) From: Leo Yan Date: Mon, 01 Dec 2025 11:22:00 +0000 Subject: [PATCH 10/19] coresight: trbe: Always check fault action when updating buffer Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251201-trbe_buffer_refactor_v1-1-v1-10-7da32b076b28@arm.com> References: <20251201-trbe_buffer_refactor_v1-1-v1-0-7da32b076b28@arm.com> In-Reply-To: <20251201-trbe_buffer_refactor_v1-1-v1-0-7da32b076b28@arm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Anshuman Khandual , Yeoreum Yun , Will Deacon , Mark Rutland , Tamas Petz , Tamas Zsoldos , Arnaldo Carvalho de Melo , Namhyung Kim , Jiri Olsa , Ian Rogers , Adrian Hunter Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Leo Yan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764588125; l=1745; i=leo.yan@arm.com; s=20250604; h=from:subject:message-id; bh=19hsKtZvm/XjHbnhnNNNKO3wE2KHI7/1sDLKvI2Gz50=; b=8n4+DTzS10CUKp2NbJ+DyZWEvFEL1+PXV1SpJ3BDr6n+4wRuWUa2C6q2/hZ1eCDj8o28E+q7i EPgYQV4HJPCA/CzTRI0GK1JPf7SF2cokf8x2mWVYtalawIGlx/dXa2q X-Developer-Key: i=leo.yan@arm.com; a=ed25519; pk=k4BaDbvkCXzBFA7Nw184KHGP5thju8lKqJYIrOWxDhI= The current code checks the fault action only via the IRQ status bit, which is unreliable due to possible hardware latency. Move the fault action check out of the IRQ status condition. This also causes the buffer size to be calculated for non-WRAP and fault cases, which is fine since the write pointer is trusted for the calculation. Signed-off-by: Leo Yan --- drivers/hwtracing/coresight/coresight-trbe.c | 17 +++-------------- 1 file changed, 3 insertions(+), 14 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtraci= ng/coresight/coresight-trbe.c index f56ecdeaa6596afb440e4d53732e08a85f9bf89d..e579ea98523c24d23a0cd265dcd= d0a46b52b52da 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -806,7 +806,6 @@ static unsigned long arm_trbe_update_buffer(struct core= sight_device *csdev, enum trbe_fault_action act; unsigned long size, status; unsigned long flags; - bool wrap =3D false; =20 WARN_ON(buf->cpudata !=3D cpudata); WARN_ON(cpudata->cpu !=3D smp_processor_id()); @@ -858,21 +857,11 @@ static unsigned long arm_trbe_update_buffer(struct co= resight_device *csdev, */ clr_trbe_irq(); isb(); - - act =3D trbe_get_fault_act(handle, status); - /* - * If this was not due to a WRAP event, we have some - * errors and as such buffer is empty. - */ - if (act !=3D TRBE_FAULT_ACT_WRAP) { - size =3D 0; - goto done; - } - - wrap =3D true; } =20 - size =3D trbe_get_trace_size(handle, buf, wrap); + act =3D trbe_get_fault_act(handle, status); + + size =3D trbe_get_trace_size(handle, buf, act =3D=3D TRBE_FAULT_ACT_WRAP); =20 done: local_irq_restore(flags); --=20 2.34.1 From nobody Mon Dec 1 21:30:54 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 82D8B30B536; Mon, 1 Dec 2025 11:22:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588160; cv=none; b=P3zM0fMGKI/OtfWu84rXLktHr6lWK7nq4Cng6ZjsibPFPkdhmfJHHh3PQLjlVyazDzaBqsBtVRcQv47QJa+YVwXeoi9PxUQuXfbNjrJ3Uoa6wS/IsQpJnFZweyQjki+07217hcxu/9UVOClm+Py01pq9alx0estpSiT/OscxyuU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588160; c=relaxed/simple; bh=zPgqK7cT5HRw0jmMlFJlZiw1Qze5S36cdWxXgWmVrNo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=H3KmoOkFEUgENTducTwqp4goJMpeYnbExX/RSAuzcZ0x84MDP6m8LWqduD7h1WYMhExE38dXN0Jh3XRLCwL/6W1iXirjY/q40biDBL84x7FifldK2ZDMTezDjsuOMLn8H156WLkxttcc0CSBtPkqXHrGo8G1kUnfY1RYak78bS0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C2684153B; Mon, 1 Dec 2025 03:22:31 -0800 (PST) Received: from e132581.arm.com (e132581.arm.com [10.1.196.87]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A46FC3F59E; Mon, 1 Dec 2025 03:22:36 -0800 (PST) From: Leo Yan Date: Mon, 01 Dec 2025 11:22:01 +0000 Subject: [PATCH 11/19] coresight: trbe: Apply overwrite erratum for only wrap event Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251201-trbe_buffer_refactor_v1-1-v1-11-7da32b076b28@arm.com> References: <20251201-trbe_buffer_refactor_v1-1-v1-0-7da32b076b28@arm.com> In-Reply-To: <20251201-trbe_buffer_refactor_v1-1-v1-0-7da32b076b28@arm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Anshuman Khandual , Yeoreum Yun , Will Deacon , Mark Rutland , Tamas Petz , Tamas Zsoldos , Arnaldo Carvalho de Melo , Namhyung Kim , Jiri Olsa , Ian Rogers , Adrian Hunter Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Leo Yan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764588125; l=1418; i=leo.yan@arm.com; s=20250604; h=from:subject:message-id; bh=zPgqK7cT5HRw0jmMlFJlZiw1Qze5S36cdWxXgWmVrNo=; b=0m6xNEMS4HJ8tkJXOqGn+u0uyMMVUB0T6iKZ8Uf469sl+ePiLcER3p8nvin6+E5g9tAzGRpq0 VvzQeV6frqAD1s3U8PKT/La3jBobNX74D0Auq+2WgksHHITGx/kBW4u X-Developer-Key: i=leo.yan@arm.com; a=ed25519; pk=k4BaDbvkCXzBFA7Nw184KHGP5thju8lKqJYIrOWxDhI= The overwrite erratum occurs only on wrap events, so apply the extra wrap condition check in the workaround. Signed-off-by: Leo Yan --- drivers/hwtracing/coresight/coresight-trbe.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtraci= ng/coresight/coresight-trbe.c index e579ea98523c24d23a0cd265dcdd0a46b52b52da..2600af12a8fb94bb8c74efda2a1= 01aacd01b0b34 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -714,7 +714,7 @@ static unsigned long trbe_get_trace_size(struct perf_ou= tput_handle *handle, * 64bytes. Thus we ignore the potential triggering of the erratum * on WRAP and limit the data to LIMIT. */ - if (wrap) + if (wrap && trbe_may_overwrite_in_fill_mode(buf->cpudata)) write =3D get_trbe_limit_pointer(); else write =3D get_trbe_write_pointer(); @@ -736,7 +736,7 @@ static unsigned long trbe_get_trace_size(struct perf_ou= tput_handle *handle, * the space we skipped with IGNORE packets. And we are always * guaranteed to have at least a PAGE_SIZE space in the buffer. */ - if (trbe_may_overwrite_in_fill_mode(buf->cpudata) && + if (wrap && trbe_may_overwrite_in_fill_mode(buf->cpudata) && !WARN_ON(size < overwrite_skip)) __trbe_pad_buf(buf, start_off, overwrite_skip); =20 --=20 2.34.1 From nobody Mon Dec 1 21:30:54 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4E77730BBA5; Mon, 1 Dec 2025 11:22:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588163; cv=none; b=UlpkvAzxjL8b9dmhQ6BbQ+ITP048Wu5nc3fM6QuKWis6GzYZQHu8vKY9+hCR38ny/RnG7DpDmJqH96ZH6Wr/uI/tAc+wOHdyofenge52zPf246kBhX6cvld2sQcSEkgHtBSLwH+TYIrvMpAd8gBhE6lytvKfHW+2xw/FWNFQvtY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588163; c=relaxed/simple; bh=YiG3r48nDifBFjpQKNGxPwH2NFBQuAbAaMlyQ0TBHdQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=iJo3uVKH7TwtUPpSRWs/K9LHsPdNAG8/nLhwDkfkfGHRzktjbXK0RwBGHJeUfjxQxIlWONtM50k7rnl507hiWthkEhj8bNGg35GhXpDr3QlMUnvcM0+/nvEsca11ObzPHz3jzpur8D3Y8yWnehaXa4MuiY8SFVMr6L3vdKBq1ZM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 922CD153B; Mon, 1 Dec 2025 03:22:34 -0800 (PST) Received: from e132581.arm.com (e132581.arm.com [10.1.196.87]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7236B3F59E; Mon, 1 Dec 2025 03:22:39 -0800 (PST) From: Leo Yan Date: Mon, 01 Dec 2025 11:22:02 +0000 Subject: [PATCH 12/19] coresight: trbe: Calculate size for buffer wrapping Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251201-trbe_buffer_refactor_v1-1-v1-12-7da32b076b28@arm.com> References: <20251201-trbe_buffer_refactor_v1-1-v1-0-7da32b076b28@arm.com> In-Reply-To: <20251201-trbe_buffer_refactor_v1-1-v1-0-7da32b076b28@arm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Anshuman Khandual , Yeoreum Yun , Will Deacon , Mark Rutland , Tamas Petz , Tamas Zsoldos , Arnaldo Carvalho de Melo , Namhyung Kim , Jiri Olsa , Ian Rogers , Adrian Hunter Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Leo Yan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764588125; l=1661; i=leo.yan@arm.com; s=20250604; h=from:subject:message-id; bh=YiG3r48nDifBFjpQKNGxPwH2NFBQuAbAaMlyQ0TBHdQ=; b=WPVW4J1nxfTXlcM++NTc5Fb3Dr4++iWibPixr4rGthRR2HcJdd1yTZDLV5JhH0wTwZa+HlfG0 nA53uhBl3/TDcEZ+p2WMKneTR81p+MedxQaDzmOl2IDiUqG2rs9OIG6 X-Developer-Key: i=leo.yan@arm.com; a=ed25519; pk=k4BaDbvkCXzBFA7Nw184KHGP5thju8lKqJYIrOWxDhI= Calculate the wrapped size when the end position is less than the start. If the start equals the end, the "wrap" flag is used to decide whether the buffer is full or empty. Signed-off-by: Leo Yan --- drivers/hwtracing/coresight/coresight-trbe.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtraci= ng/coresight/coresight-trbe.c index 2600af12a8fb94bb8c74efda2a101aacd01b0b34..48bc03bd339908b5eac9466dc60= 325ff1b238976 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -696,7 +696,7 @@ static unsigned long trbe_get_trace_size(struct perf_ou= tput_handle *handle, { u64 write; u64 start_off, end_off; - u64 size; + u64 size, buf_size; u64 overwrite_skip =3D TRBE_WORKAROUND_OVERWRITE_FILL_MODE_SKIP_BYTES; =20 /* @@ -726,11 +726,18 @@ static unsigned long trbe_get_trace_size(struct perf_= output_handle *handle, */ end_off =3D write - buf->trbe_base; start_off =3D PERF_IDX2OFF(handle->head, buf); + buf_size =3D buf->trbe_limit - buf->trbe_base; + + if (end_off > start_off) + size =3D end_off - start_off; + else if (end_off < start_off) + size =3D end_off + buf_size - start_off; + else if (wrap) + /* The start is the same as the end, just wrapped */ + size =3D buf_size; + else + size =3D 0; =20 - if (WARN_ON_ONCE(end_off < start_off)) - return 0; - - size =3D end_off - start_off; /* * If the TRBE is affected by the following erratum, we must fill * the space we skipped with IGNORE packets. And we are always --=20 2.34.1 From nobody Mon Dec 1 21:30:54 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5B09F30BF75; Mon, 1 Dec 2025 11:22:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588166; cv=none; b=a54fdTrwl9zF1iAGUQJepvEThLI4WGflu97YsBlz/LIAvCaKQWPd8D4SSOEuXyLsyn8Nwp317XJGOZy6ALeZaTne+NOguuJL8mAM69jVIPtnqsiH3pgCq20Cm7zr4pskKatzi9KI+QruBAKIYR305uWR2Yq/YATlO3obgiu/DNw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588166; c=relaxed/simple; bh=tI23wHWbnF4yzdYIODYmTmujHYxBfWMJv1sYUQXmTec=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=b0DWhAC9FYiz3srNlVAicw2Z+O5asLB+Fqm6EQcmiDEzSgaGs6gNJEJRFQZqUx+nsyz8vF7Jns+gyMOapVFQ/MwFoCm88EcMEddyALWnA8DjjWIIMduVmUckKdRuBxTOs17WgwDFseVq7TMviTpJPLzzIe2eEV9jgfhqPXF3gfo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 63F85153B; Mon, 1 Dec 2025 03:22:37 -0800 (PST) Received: from e132581.arm.com (e132581.arm.com [10.1.196.87]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 41E053F59E; Mon, 1 Dec 2025 03:22:42 -0800 (PST) From: Leo Yan Date: Mon, 01 Dec 2025 11:22:03 +0000 Subject: [PATCH 13/19] coresight: trbe: Remove misleading comment Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251201-trbe_buffer_refactor_v1-1-v1-13-7da32b076b28@arm.com> References: <20251201-trbe_buffer_refactor_v1-1-v1-0-7da32b076b28@arm.com> In-Reply-To: <20251201-trbe_buffer_refactor_v1-1-v1-0-7da32b076b28@arm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Anshuman Khandual , Yeoreum Yun , Will Deacon , Mark Rutland , Tamas Petz , Tamas Zsoldos , Arnaldo Carvalho de Melo , Namhyung Kim , Jiri Olsa , Ian Rogers , Adrian Hunter Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Leo Yan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764588125; l=1975; i=leo.yan@arm.com; s=20250604; h=from:subject:message-id; bh=tI23wHWbnF4yzdYIODYmTmujHYxBfWMJv1sYUQXmTec=; b=RIRbbXcq3hGGI2EJ1tcNL6xKmXI8GPtNQJN0zCfuGLhEufkzi2hxCfk9zj/nB4NPQprWUPel+ NNUomz9IsgYA1ODwFJFyowfrz5o9URya2JGODB2lFPLrysXOSBGdyR4 X-Developer-Key: i=leo.yan@arm.com; a=ed25519; pk=k4BaDbvkCXzBFA7Nw184KHGP5thju8lKqJYIrOWxDhI= Since the rounded-up wakeup address is always higher than the head, the limit cannot be less than the head caused by wakeup capping. The described scenario is never valid caused by wakeup capping, remove the comment to avoid confusion. Signed-off-by: Leo Yan --- drivers/hwtracing/coresight/coresight-trbe.c | 16 ++-------------- 1 file changed, 2 insertions(+), 14 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtraci= ng/coresight/coresight-trbe.c index 48bc03bd339908b5eac9466dc60325ff1b238976..206eaf103cd94f36220cb6bddd1= a78012f5de35a 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -488,10 +488,10 @@ static unsigned long __trbe_normal_offset(struct perf= _output_handle *handle) limit =3D min(limit, round_up(wakeup, PAGE_SIZE)); =20 /* - * There are two situation when this can happen i.e limit is before + * There is a situation when this can happen i.e limit is before * the head and hence TRBE cannot be configured. * - * 1) head < tail (aligned down with PAGE_SIZE) and also they are both + * head < tail (aligned down with PAGE_SIZE) and also they are both * within the same PAGE size range. * * PAGE_SIZE @@ -502,18 +502,6 @@ static unsigned long __trbe_normal_offset(struct perf_= output_handle *handle) * |$$$$$$$$$$$$$$$$$$$|=3D=3D=3D=3D=3D=3D=3D=3D|$$$$$$$| * +------------|------|--------|-------+ * trbe_base trbe_base + nr_pages - * - * 2) head < wakeup (aligned up with PAGE_SIZE) < tail and also both - * head and wakeup are within same PAGE size range. - * - * PAGE_SIZE - * |----------------------| - * - * limit head wakeup tail - * +----|------|-------|--------|-------+ - * |$$$$$$$$$$$|=3D=3D=3D=3D=3D=3D=3D|=3D=3D=3D=3D=3D=3D=3D=3D|$$$$$$$| - * +----|------|-------|--------|-------+ - * trbe_base trbe_base + nr_pages */ if (limit > head) return limit; --=20 2.34.1 From nobody Mon Dec 1 21:30:54 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3F05730C36C; Mon, 1 Dec 2025 11:22:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588169; cv=none; b=K9ETTWtKzT8yWTy4SR4AOleKmAHaAkRUGiz65N3W+dpYRsaBS3J2nuMJ1dEJK+Y97sXV9C41JKfje9YZutV6ggzB3TIvbGNHxBpxslMjyInfwTYRc3acZRkuLC2/1JV7Js8R7qGKN11qxV1q7ozProk9sqh4XO3npgx8jVH9eoo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588169; c=relaxed/simple; bh=pdBR+vHQTejdXMyQCGeDWKUBEJWy99o13yGFD4L3f8I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bRrYRPvPZ00UdOK//XDnmTBM9oAvL50JyG/0nbrycT0WhElIm32K1jSkFAZ3V3yuaFTZm+dETEobovpIPBhXtEAGKmdGcTvuukBLXPsBWGTOH8uDY+Byt4sZfdY9b1Eo6UglrP84Z6ybdY7S3pwQlufYvVTrCJgPEyC5kPXPcN4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 320D71595; Mon, 1 Dec 2025 03:22:40 -0800 (PST) Received: from e132581.arm.com (e132581.arm.com [10.1.196.87]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 10BF63F7B4; Mon, 1 Dec 2025 03:22:44 -0800 (PST) From: Leo Yan Date: Mon, 01 Dec 2025 11:22:04 +0000 Subject: [PATCH 14/19] coresight: trbe: Refactor compute_trbe_buffer_limit() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251201-trbe_buffer_refactor_v1-1-v1-14-7da32b076b28@arm.com> References: <20251201-trbe_buffer_refactor_v1-1-v1-0-7da32b076b28@arm.com> In-Reply-To: <20251201-trbe_buffer_refactor_v1-1-v1-0-7da32b076b28@arm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Anshuman Khandual , Yeoreum Yun , Will Deacon , Mark Rutland , Tamas Petz , Tamas Zsoldos , Arnaldo Carvalho de Melo , Namhyung Kim , Jiri Olsa , Ian Rogers , Adrian Hunter Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Leo Yan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764588125; l=3669; i=leo.yan@arm.com; s=20250604; h=from:subject:message-id; bh=pdBR+vHQTejdXMyQCGeDWKUBEJWy99o13yGFD4L3f8I=; b=Hmo3a2QT2DsoM7rDrG/lKaNtOxyiNlks/bbGtYN9y7F7T2KvSHz41ysRmE4Y8+Oui2MvkevKV GJQHuQ2gOsjDSaahhZzNT2OPPflU2YZDrAv1xoLcJUGBRluhPm2QoxV X-Developer-Key: i=leo.yan@arm.com; a=ed25519; pk=k4BaDbvkCXzBFA7Nw184KHGP5thju8lKqJYIrOWxDhI= Refactor compute_trbe_buffer_limit() to perform the computation and handle failures. The return type is changed from a limit offset to an error number (0 is for success). This refactoring is for future extensions, such as calculating additional values (e.g., the trigger count). No functional changes are introduced. Signed-off-by: Leo Yan --- drivers/hwtracing/coresight/coresight-trbe.c | 44 +++++++++++++++++-------= ---- 1 file changed, 27 insertions(+), 17 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtraci= ng/coresight/coresight-trbe.c index 206eaf103cd94f36220cb6bddd1a78012f5de35a..941aa46e9b11f60c707eb400939= 64de454a3fd83 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -332,7 +332,7 @@ static void trbe_pad_buf(struct perf_output_handle *han= dle, int len) perf_aux_output_skip(handle, len); } =20 -static unsigned long trbe_snapshot_offset(struct perf_output_handle *handl= e) +static int trbe_snapshot_offset(struct perf_output_handle *handle) { struct trbe_buf *buf =3D etm_perf_sink_config(handle); =20 @@ -341,7 +341,8 @@ static unsigned long trbe_snapshot_offset(struct perf_o= utput_handle *handle) * the decoder to reset in case of an overflow or corruption. * So we can use the entire buffer for the snapshot mode. */ - return buf->nr_pages * PAGE_SIZE; + buf->trbe_limit =3D buf->trbe_base + buf->nr_pages * PAGE_SIZE; + return 0; } =20 static u64 trbe_min_trace_buf_size(struct perf_output_handle *handle) @@ -510,7 +511,7 @@ static unsigned long __trbe_normal_offset(struct perf_o= utput_handle *handle) return 0; } =20 -static unsigned long trbe_normal_offset(struct perf_output_handle *handle) +static int trbe_normal_offset(struct perf_output_handle *handle) { struct trbe_buf *buf =3D etm_perf_sink_config(handle); u64 limit =3D __trbe_normal_offset(handle); @@ -529,19 +530,34 @@ static unsigned long trbe_normal_offset(struct perf_o= utput_handle *handle) limit =3D __trbe_normal_offset(handle); head =3D PERF_IDX2OFF(handle->head, buf); } - return limit; + + if (!limit) + return -ENOSPC; + + buf->trbe_limit =3D buf->trbe_base + limit; + return 0; } =20 -static unsigned long compute_trbe_buffer_limit(struct perf_output_handle *= handle) +static int trbe_compute_next(struct perf_output_handle *handle) { struct trbe_buf *buf =3D etm_perf_sink_config(handle); - unsigned long offset; + int ret; + + perf_aux_output_flag(handle, PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW); =20 if (buf->snapshot) - offset =3D trbe_snapshot_offset(handle); + ret =3D trbe_snapshot_offset(handle); else - offset =3D trbe_normal_offset(handle); - return buf->trbe_base + offset; + ret =3D trbe_normal_offset(handle); + + if (ret) + return ret; + + buf->trbe_write =3D buf->trbe_base + PERF_IDX2OFF(handle->head, buf); + + /* Set the base of the TRBE to the buffer base */ + buf->trbe_hw_base =3D buf->trbe_base; + return 0; } =20 static void clr_trbe_status(void) @@ -986,15 +1002,9 @@ static int __arm_trbe_enable(struct trbe_buf *buf, { int ret =3D 0; =20 - perf_aux_output_flag(handle, PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW); - buf->trbe_limit =3D compute_trbe_buffer_limit(handle); - buf->trbe_write =3D buf->trbe_base + PERF_IDX2OFF(handle->head, buf); - if (buf->trbe_limit =3D=3D buf->trbe_base) { - ret =3D -ENOSPC; + ret =3D trbe_compute_next(handle); + if (ret) goto err; - } - /* Set the base of the TRBE to the buffer base */ - buf->trbe_hw_base =3D buf->trbe_base; =20 ret =3D trbe_apply_work_around_before_enable(buf); if (ret) --=20 2.34.1 From nobody Mon Dec 1 21:30:54 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E93E530C61B; Mon, 1 Dec 2025 11:22:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588172; cv=none; b=Erlo7bx4smTplico5xFkX5TIMKQAITw2+3Oacm2mLlDPdF3NnhgghputGYAUjLI6tmsPTQEWR2eJkB0PJX6x/8EwDw0fTVmBJtR6JBGDws/KAsqpX8NaW+wUCQnsAlMrJGzPMQNfz0GXmWB1uuYyvfp0Apgw1gUrbFWkdViMJ4I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588172; c=relaxed/simple; bh=f8fiAsWWNi9eG7kzbI25lHuMO+0SEpBi2vesAPCLkBQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VtxXD3tmriWu38nyzQLcw2n3XhZxg/XEDNYsIQE9BZNA5dMHR2LAq1JnszrozoxIyKhc5GZpC59oEvj7IQc9+Q/yZO40QQiqK+0SfNV2kH8aZHl1uejud6lYsp4XxyoGehbHgMuzuHsg7lANetzVDzpM5uKMRb/oVwXYcPQYLOI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F1ADF153B; Mon, 1 Dec 2025 03:22:42 -0800 (PST) Received: from e132581.arm.com (e132581.arm.com [10.1.196.87]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D2D583F59E; Mon, 1 Dec 2025 03:22:47 -0800 (PST) From: Leo Yan Date: Mon, 01 Dec 2025 11:22:05 +0000 Subject: [PATCH 15/19] coresight: trbe: Add static key for bypassing trigger mode Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251201-trbe_buffer_refactor_v1-1-v1-15-7da32b076b28@arm.com> References: <20251201-trbe_buffer_refactor_v1-1-v1-0-7da32b076b28@arm.com> In-Reply-To: <20251201-trbe_buffer_refactor_v1-1-v1-0-7da32b076b28@arm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Anshuman Khandual , Yeoreum Yun , Will Deacon , Mark Rutland , Tamas Petz , Tamas Zsoldos , Arnaldo Carvalho de Melo , Namhyung Kim , Jiri Olsa , Ian Rogers , Adrian Hunter Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Leo Yan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764588125; l=1845; i=leo.yan@arm.com; s=20250604; h=from:subject:message-id; bh=f8fiAsWWNi9eG7kzbI25lHuMO+0SEpBi2vesAPCLkBQ=; b=siS5jicoBJRIEarVYCG4OsMb2IDUFmciW/1Nkg+AM25TbL8IlrHgAYVJqIIaH1u9S9Qal+dNp i8heRWCOmCKDw3rmu9hdz7xMe10PTYu9LJWEPrKBPdbZbxF3IFKX7PQ X-Developer-Key: i=leo.yan@arm.com; a=ed25519; pk=k4BaDbvkCXzBFA7Nw184KHGP5thju8lKqJYIrOWxDhI= To avoid complexity, if any CPU in the system has the fill mode erratum, the driver will not use trigger mode, it simply rolls back to fill mode only and apply the workaround on it. Add a static key to control trigger mode bypassing. During each CPU probe, the key is enabled when the relevant erratum is detected. Signed-off-by: Leo Yan --- drivers/hwtracing/coresight/coresight-trbe.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtraci= ng/coresight/coresight-trbe.c index 941aa46e9b11f60c707eb40093964de454a3fd83..8390d0a8fe23d35945610df15f2= 1751279ee37ee 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -17,6 +17,7 @@ =20 #include #include +#include #include #include =20 @@ -147,6 +148,12 @@ struct trbe_drvdata { struct platform_device *pdev; }; =20 +DEFINE_STATIC_KEY_FALSE(trbe_trigger_mode_bypass); + +#define trbe_trigger_mode_need_bypass(cpudata) \ + (trbe_may_overwrite_in_fill_mode((cpudata)) || \ + trbe_may_write_out_of_range((cpudata))) + static void trbe_check_errata(struct trbe_cpudata *cpudata) { int i; @@ -1306,6 +1313,14 @@ static void arm_trbe_register_coresight_cpu(struct t= rbe_drvdata *drvdata, int cp =20 dev_set_drvdata(&trbe_csdev->dev, cpudata); coresight_set_percpu_sink(cpu, trbe_csdev); + + /* + * If any CPU cannot use trigger mode, bypass the mode globally for + * consistent tracing behaviour. + */ + if (trbe_trigger_mode_need_bypass(cpudata)) + static_branch_enable(&trbe_trigger_mode_bypass); + return; cpu_clear: cpumask_clear_cpu(cpu, &drvdata->supported_cpus); --=20 2.34.1 From nobody Mon Dec 1 21:30:54 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B1C2130CDA9; Mon, 1 Dec 2025 11:22:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588175; cv=none; b=Fzcd6pdgJTu/ZyLdMne7EZQ3G8r2XYs9L1YqUIY1RREsJ04TgdUkoOnvxWRHiPxm6adwbpXlknK2AnElw5735eBWCmFWLq3pNFmCAPdhXmkObeSU22niY1CPvRj5EuNi+ghJcEH2+ei/4M6325JxUtlcqDzYSN7BQeGiYMRHMM4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588175; c=relaxed/simple; bh=zYJhpNe0EK769mhWSNYuRDSmTNRSyJS198EDuKt61lQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=sKgWZAdNgC0IWskLEd03EVdELTAw07eYT3VaChwRtaJvYdvnjYDnbtmLA/y/ZYzVYSYu1NBb1QBxYvGXYC977991PKvGi7dz5KWXc4WkDbxs8dfA+muxoVpLgsJU5zRCyCb66gV+Pq5LNJukzj8CTl7SwJuPQXZ0y8IQUgd7F8s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C18BD1595; Mon, 1 Dec 2025 03:22:45 -0800 (PST) Received: from e132581.arm.com (e132581.arm.com [10.1.196.87]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A157B3F59E; Mon, 1 Dec 2025 03:22:50 -0800 (PST) From: Leo Yan Date: Mon, 01 Dec 2025 11:22:06 +0000 Subject: [PATCH 16/19] coresight: trbe: Support trigger mode Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251201-trbe_buffer_refactor_v1-1-v1-16-7da32b076b28@arm.com> References: <20251201-trbe_buffer_refactor_v1-1-v1-0-7da32b076b28@arm.com> In-Reply-To: <20251201-trbe_buffer_refactor_v1-1-v1-0-7da32b076b28@arm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Anshuman Khandual , Yeoreum Yun , Will Deacon , Mark Rutland , Tamas Petz , Tamas Zsoldos , Arnaldo Carvalho de Melo , Namhyung Kim , Jiri Olsa , Ian Rogers , Adrian Hunter Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Leo Yan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764588125; l=9993; i=leo.yan@arm.com; s=20250604; h=from:subject:message-id; bh=zYJhpNe0EK769mhWSNYuRDSmTNRSyJS198EDuKt61lQ=; b=EHKqfO6SdCjRT/8ah8Z2CPX8+ZPjYj8MbsNsvZx2QAKpdc1Q/vgPVeGGUr67gPzXCTN8D7uVb 6seRiq8uTzKDkHxA5KCSOu2LSMXRBPS1W1E2LGSM39R1ZKvzg++o0PX X-Developer-Key: i=leo.yan@arm.com; a=ed25519; pk=k4BaDbvkCXzBFA7Nw184KHGP5thju8lKqJYIrOWxDhI= The buffer currently operates in fill mode, where tracing stops when it reaches the end of the buffer and a maintenance interrupt is raised. However, due to IRQ latency, trace data may be lost during the window in which tracing is halted but the program continues to run. To mitigate the issue, this commit enables the trigger count to support buffer maintenance without disabling tracing. This is fulfilled with two modes: 1) Set a trigger count as a watermark and use fill mode to prevent the buffer from being overwritten. Once the count is decremented to zero, an interrupt is raised for buffer maintenance, but the hardware continues collecting trace data until limit. head watermark tail +----+---------------+---------+-------+ |$$$$| | |$$$$$$$| +----+---------------+---------+-------+ base `---- count ----' limit base + nr_pages $$$ : Filled trace data 2) Use wrap mode so that tracing continues when reach the top of the buffer. The trigger count is configured as "Stop on trigger" to guard the trace data not to be overwritten. watermark tail head +--------+-----------+---------+-------+ | | |$$$$$$$$$| | +--------+-----------+---------+-------+ base base + nr_pages limit `-------> >-- counter ---------' $$$ : Filled trace data The modes are selected by comparing the limit with the trigger position. An extra TRBE_FAULT_ACT_TRIG state is introduced for fault action, it is used to distinguish the trigger event from the WRAP event. Signed-off-by: Leo Yan --- drivers/hwtracing/coresight/coresight-trbe.c | 101 +++++++++++++++++++++--= ---- drivers/hwtracing/coresight/coresight-trbe.h | 14 ++++ 2 files changed, 94 insertions(+), 21 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtraci= ng/coresight/coresight-trbe.c index 8390d0a8fe23d35945610df15f21751279ee37ee..0551ea9b4f8286c156e3c9c7ac9= 4e2ecd3b9dc3f 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -48,6 +48,7 @@ #define TRBE_TRACE_MIN_BUF_SIZE 64 =20 enum trbe_fault_action { + TRBE_FAULT_ACT_TRIG, TRBE_FAULT_ACT_WRAP, TRBE_FAULT_ACT_SPURIOUS, TRBE_FAULT_ACT_FATAL, @@ -67,6 +68,7 @@ struct trbe_buf { unsigned long trbe_hw_base; unsigned long trbe_limit; unsigned long trbe_write; + unsigned long trbe_count; int nr_pages; void **pages; bool snapshot; @@ -478,6 +480,10 @@ static unsigned long __trbe_normal_offset(struct perf_= output_handle *handle) if (head < tail) limit =3D round_down(tail, PAGE_SIZE); =20 + /* If trigger mode is enabled, no need to use limit for watermark */ + if (!static_branch_unlikely(&trbe_trigger_mode_bypass)) + goto out; + /* * Wakeup may be arbitrarily far into the future. If it's not in the * current generation, either we'll wrap before hitting it, or it's @@ -495,6 +501,7 @@ static unsigned long __trbe_normal_offset(struct perf_o= utput_handle *handle) if (handle->wakeup < (handle->head + handle->size) && head <=3D wakeup) limit =3D min(limit, round_up(wakeup, PAGE_SIZE)); =20 +out: /* * There is a situation when this can happen i.e limit is before * the head and hence TRBE cannot be configured. @@ -518,6 +525,39 @@ static unsigned long __trbe_normal_offset(struct perf_= output_handle *handle) return 0; } =20 +static u64 __trbe_normal_trigger_count(struct perf_output_handle *handle) +{ + struct trbe_buf *buf =3D etm_perf_sink_config(handle); + struct trbe_cpudata *cpudata =3D buf->cpudata; + u64 limit, head, wakeup; + u64 count =3D 0; + + if (static_branch_unlikely(&trbe_trigger_mode_bypass)) + return 0; + + limit =3D buf->trbe_limit - buf->trbe_base; + head =3D PERF_IDX2OFF(handle->head, buf); + wakeup =3D PERF_IDX2OFF(handle->wakeup, buf); + + /* Set the count to guard the end of free buffer after wrap around */ + if (limit =3D=3D buf->nr_pages * PAGE_SIZE && (head + handle->size) > lim= it) + count =3D handle->size; + + /* + * If the watermark is less than the limit, use the trigger count for + * the watermark maintenance. + */ + if (handle->wakeup < (handle->head + handle->size) && head <=3D wakeup) { + u64 wakeup_count =3D + round_up(wakeup - head, cpudata->trbe_hw_align); + + if (head + wakeup_count < limit) + count =3D wakeup_count; + } + + return count; +} + static int trbe_normal_offset(struct perf_output_handle *handle) { struct trbe_buf *buf =3D etm_perf_sink_config(handle); @@ -542,6 +582,7 @@ static int trbe_normal_offset(struct perf_output_handle= *handle) return -ENOSPC; =20 buf->trbe_limit =3D buf->trbe_base + limit; + buf->trbe_count =3D __trbe_normal_trigger_count(handle); return 0; } =20 @@ -594,24 +635,40 @@ static void set_trbe_limit_pointer_enabled(struct trb= e_buf *buf) trblimitr &=3D ~TRBLIMITR_EL1_TM_MASK; trblimitr &=3D ~TRBLIMITR_EL1_LIMIT_MASK; =20 - /* - * Fill trace buffer mode is used here while configuring the - * TRBE for trace capture. In this particular mode, the trace - * collection is stopped and a maintenance interrupt is raised - * when the current write pointer wraps. This pause in trace - * collection gives the software an opportunity to capture the - * trace data in the interrupt handler, before reconfiguring - * the TRBE. - */ - trblimitr |=3D (TRBLIMITR_EL1_FM_FILL << TRBLIMITR_EL1_FM_SHIFT) & - TRBLIMITR_EL1_FM_MASK; + if (!buf->trbe_count || + buf->trbe_write + buf->trbe_count =3D=3D buf->trbe_limit) { + /* + * Fill trace buffer mode is used here while configuring the + * TRBE for trace capture. In this particular mode, the trace + * collection is stopped and a maintenance interrupt is raised + * when the current write pointer wraps. This pause in trace + * collection gives the software an opportunity to capture the + * trace data in the interrupt handler, before reconfiguring + * the TRBE. + */ + trblimitr |=3D FIELD_PREP(TRBLIMITR_EL1_FM_MASK, TRBLIMITR_EL1_FM_FILL) | + FIELD_PREP(TRBLIMITR_EL1_TM_MASK, TRBLIMITR_EL1_TM_IGNR); + } else if (buf->trbe_write + buf->trbe_count < buf->trbe_limit) { + /* + * Fill mode is used here to stop trace collection and prevent + * the buffer from being overwritten. Trigger mode continues + * trace collection and raises a maintenance interrupt on a + * trigger event, which acts as a watermark for notifying + * userspace. + */ + trblimitr |=3D FIELD_PREP(TRBLIMITR_EL1_FM_MASK, TRBLIMITR_EL1_FM_FILL) | + FIELD_PREP(TRBLIMITR_EL1_TM_MASK, TRBLIMITR_EL1_TM_IRQ); + } else if (buf->trbe_write + buf->trbe_count > buf->trbe_limit) { + /* + * Wrap buffer mode continues trace collection and raises + * maintenance interrupt on buffer wrap. Trigger mode stops + * trace on trigger event to guard the buffer from being + * overwritten. + */ + trblimitr |=3D FIELD_PREP(TRBLIMITR_EL1_FM_MASK, TRBLIMITR_EL1_FM_WRAP) | + FIELD_PREP(TRBLIMITR_EL1_TM_MASK, TRBLIMITR_EL1_TM_STOP); + } =20 - /* - * Trigger mode is not used here while configuring the TRBE for - * the trace capture. Hence just keep this in the ignore mode. - */ - trblimitr |=3D (TRBLIMITR_EL1_TM_IGNR << TRBLIMITR_EL1_TM_SHIFT) & - TRBLIMITR_EL1_TM_MASK; trblimitr |=3D (addr & PAGE_MASK); set_trbe_enabled(buf->cpudata, trblimitr); } @@ -623,6 +680,7 @@ static void trbe_enable_hw(struct trbe_buf *buf) WARN_ON(buf->trbe_write >=3D buf->trbe_limit); set_trbe_base_pointer(buf->trbe_hw_base); set_trbe_write_pointer(buf->trbe_write); + set_trbe_trigger_count(buf->trbe_count); =20 /* * Synchronize all the register updates @@ -639,8 +697,6 @@ static enum trbe_fault_action trbe_get_fault_act(struct= perf_output_handle *hand int ec =3D get_trbe_ec(trbsr); int bsc =3D get_trbe_bsc(trbsr); =20 - WARN_ON(is_trbe_running(trbsr)); - if (is_trbe_abort(trbsr)) { err_str =3D "External abort"; goto out_fatal; @@ -672,8 +728,7 @@ static enum trbe_fault_action trbe_get_fault_act(struct= perf_output_handle *hand case TRBE_BSC_FILLED: break; case TRBE_BSC_TRIGGERED: - err_str =3D "Unexpected trigger status"; - goto out_fatal; + break; default: err_str =3D "Unexpected buffer status code"; goto out_fatal; @@ -692,6 +747,9 @@ static enum trbe_fault_action trbe_get_fault_act(struct= perf_output_handle *hand if (is_trbe_wrap(trbsr)) return TRBE_FAULT_ACT_WRAP; =20 + if (is_trbe_trg(trbsr)) + return TRBE_FAULT_ACT_TRIG; + return TRBE_FAULT_ACT_SPURIOUS; =20 out_fatal: @@ -1180,6 +1238,7 @@ static irqreturn_t arm_trbe_irq_handler(int irq, void= *dev) clr_trbe_status(); =20 switch (act) { + case TRBE_FAULT_ACT_TRIG: case TRBE_FAULT_ACT_WRAP: truncated =3D !!trbe_handle_overflow(handle, act); break; diff --git a/drivers/hwtracing/coresight/coresight-trbe.h b/drivers/hwtraci= ng/coresight/coresight-trbe.h index d7f7cd763c0c7139cf322b7336ee563073e3bea0..4c65d164a946ec9860825e75641= 96745b60d730b 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.h +++ b/drivers/hwtracing/coresight/coresight-trbe.h @@ -114,6 +114,20 @@ static inline void set_trbe_write_pointer(unsigned lon= g addr) write_sysreg_s(addr, SYS_TRBPTR_EL1); } =20 +static inline void set_trbe_trigger_count(unsigned long count) +{ + u64 trbsr; + + write_sysreg_s(count, SYS_TRBTRG_EL1); + + /* TRBSR_EL1.TRG has been cleared in clr_trbe_status() */ + if (!count) + return; + + trbsr =3D read_sysreg_s(SYS_TRBSR_EL1); + write_sysreg_s(trbsr | TRBSR_EL1_TRG, SYS_TRBSR_EL1); +} + static inline unsigned long get_trbe_limit_pointer(void) { u64 trblimitr =3D read_sysreg_s(SYS_TRBLIMITR_EL1); --=20 2.34.1 From nobody Mon Dec 1 21:30:54 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 8CCDA30C61B; Mon, 1 Dec 2025 11:22:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588178; cv=none; b=dpYtwRFdkwqOrLhVlO5mERlwD6raZNygbRmPmNEH/i+gmipAc5Gw7uM69C6iNeiLvlcYJHk+Jvb4wA7u9wVyT7dGSq6zG10O8gu6FiAQn+Vm4V4aI79AN9BhJu46ZpwEqlezPlee2R4blILAKwYUQIiv4u4lHrWAFJZScYqWgKw= ARC-Message-Signature: i=1; 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Mon, 1 Dec 2025 03:22:53 -0800 (PST) From: Leo Yan Date: Mon, 01 Dec 2025 11:22:07 +0000 Subject: [PATCH 17/19] coresight: trbe: Enable circle mode for snapshot Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251201-trbe_buffer_refactor_v1-1-v1-17-7da32b076b28@arm.com> References: <20251201-trbe_buffer_refactor_v1-1-v1-0-7da32b076b28@arm.com> In-Reply-To: <20251201-trbe_buffer_refactor_v1-1-v1-0-7da32b076b28@arm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Anshuman Khandual , Yeoreum Yun , Will Deacon , Mark Rutland , Tamas Petz , Tamas Zsoldos , Arnaldo Carvalho de Melo , Namhyung Kim , Jiri Olsa , Ian Rogers , Adrian Hunter Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Leo Yan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764588125; l=1408; i=leo.yan@arm.com; s=20250604; h=from:subject:message-id; bh=eJElq7gC/JnnPBEjj1BBHX13g7bjZ8CcdBXjEePLB/4=; b=HQEoNUUs9+ttxYbCdH0xtRa8oIkNFKPAR0kgNljjd84BooIOh8Sfb9YOFOnI16mZeSDc1ZOIV omtaVR/7aqGAU2xmRk+/cxq/XLmW1ei1HSb3CgzG5AArMTyPRhhjME1 X-Developer-Key: i=leo.yan@arm.com; a=ed25519; pk=k4BaDbvkCXzBFA7Nw184KHGP5thju8lKqJYIrOWxDhI= A snapshot session captures trace data only when userspace receives a signal and disables tracing. Before disabling, enable circle mode instead of fill mode to avoid unnecessary interrupt handling. Signed-off-by: Leo Yan --- drivers/hwtracing/coresight/coresight-trbe.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtraci= ng/coresight/coresight-trbe.c index 0551ea9b4f8286c156e3c9c7ac94e2ecd3b9dc3f..ee9993d518d2a41f0d709b7d069= 0b2dfe0bef2d9 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -635,6 +635,12 @@ static void set_trbe_limit_pointer_enabled(struct trbe= _buf *buf) trblimitr &=3D ~TRBLIMITR_EL1_TM_MASK; trblimitr &=3D ~TRBLIMITR_EL1_LIMIT_MASK; =20 + if (buf->snapshot) { + trblimitr |=3D FIELD_PREP(TRBLIMITR_EL1_FM_MASK, TRBLIMITR_EL1_FM_CBUF) | + FIELD_PREP(TRBLIMITR_EL1_TM_MASK, TRBLIMITR_EL1_TM_IGNR); + goto enable_trace_buf; + } + if (!buf->trbe_count || buf->trbe_write + buf->trbe_count =3D=3D buf->trbe_limit) { /* @@ -669,6 +675,7 @@ static void set_trbe_limit_pointer_enabled(struct trbe_= buf *buf) FIELD_PREP(TRBLIMITR_EL1_TM_MASK, TRBLIMITR_EL1_TM_STOP); } =20 +enable_trace_buf: trblimitr |=3D (addr & PAGE_MASK); set_trbe_enabled(buf->cpudata, trblimitr); } --=20 2.34.1 From nobody Mon Dec 1 21:30:54 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 7657730E836; Mon, 1 Dec 2025 11:22:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588181; cv=none; b=K+KEAee19HTwvPJgXlRCWaHKcAK6vj9r3iD5jYipSKALXevU0wLt4X73O6tCKV1BdzLqkot85jPFL7oVXF5IhlVpxJ0KzSSKUm5JgZPC3u82HDmMWr7D0yW3WlFy7jyL1+wzzZ9IJTVLZ2TixQ1NwCK578DHg5RxCEPGGso9Adk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588181; c=relaxed/simple; bh=8RrcyuAmXl4l9e1cKb6duyp4YPXzhlLxNp/3AlZJifs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fqrp+Q1ahA5pSYEaR6qaxlOo2jPvJsFpPvdi2XgeYJsKCt9IWYrc9n7fumJaRenQaMJkc3b+JDfxKOfjdwDXsU7L34cNJ5wphhqRJ5Q7cWrCvT+E87B5cevS8jGYW+1z33z+yVAYkyuiX+jXAgeVku/GGtz7wc9qO8o4GdNu5Ro= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7915F1596; Mon, 1 Dec 2025 03:22:51 -0800 (PST) Received: from e132581.arm.com (e132581.arm.com [10.1.196.87]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3C3B73F59E; Mon, 1 Dec 2025 03:22:56 -0800 (PST) From: Leo Yan Date: Mon, 01 Dec 2025 11:22:08 +0000 Subject: [PATCH 18/19] coresight: trbe: Add kunit tests Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251201-trbe_buffer_refactor_v1-1-v1-18-7da32b076b28@arm.com> References: <20251201-trbe_buffer_refactor_v1-1-v1-0-7da32b076b28@arm.com> In-Reply-To: <20251201-trbe_buffer_refactor_v1-1-v1-0-7da32b076b28@arm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Anshuman Khandual , Yeoreum Yun , Will Deacon , Mark Rutland , Tamas Petz , Tamas Zsoldos , Arnaldo Carvalho de Melo , Namhyung Kim , Jiri Olsa , Ian Rogers , Adrian Hunter Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Leo Yan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764588125; l=26933; i=leo.yan@arm.com; s=20250604; h=from:subject:message-id; bh=8RrcyuAmXl4l9e1cKb6duyp4YPXzhlLxNp/3AlZJifs=; b=5QDU0iQZnycrovffIn+bvP3nYITunOC/cf88qD7cIMaHRIDBgF0g67HHADsScSqZr4Nwnm3cU nptNHlTVFQaD5csXLmqd0FtzRXmwG/yyt+NeASH3wwXPVyqbXZCeEND X-Developer-Key: i=leo.yan@arm.com; a=ed25519; pk=k4BaDbvkCXzBFA7Nw184KHGP5thju8lKqJYIrOWxDhI= Add tests to verify the calculation of the limit and trigger count. Because trigger mode can be disabled, provide two test suites: one with trigger mode enabled and one with it disabled. The cpudata structure is initialized by the test stub, so move its definition into the header for including. Signed-off-by: Leo Yan --- drivers/hwtracing/coresight/Kconfig | 9 + drivers/hwtracing/coresight/Makefile | 1 + .../coresight/coresight-trbe-kunit-tests.c | 536 +++++++++++++++++= ++++ drivers/hwtracing/coresight/coresight-trbe.c | 112 +---- drivers/hwtracing/coresight/coresight-trbe.h | 89 ++++ 5 files changed, 660 insertions(+), 87 deletions(-) diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresi= ght/Kconfig index 6a4239ebb582e95f0ebe8e9c8738a726f27f60a1..f5758563c0090141cdca67f16e7= b7b32e7c75bb8 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -214,6 +214,15 @@ config CORESIGHT_TRBE To compile this driver as a module, choose M here: the module will be called coresight-trbe. =20 +config CORESIGHT_TRBE_KUNIT_TESTS + tristate "Enable Coresight TRBE unit tests" + depends on KUNIT + depends on CORESIGHT_TRBE + default KUNIT_ALL_TESTS + help + Enable Coresight TRBE unit tests. Only useful for development and not + intended for production. + config ULTRASOC_SMB tristate "Ultrasoc system memory buffer drivers" depends on ACPI || COMPILE_TEST diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/cores= ight/Makefile index ab16d06783a572ea1308dfb3a30c96df9e5ffdb7..f8961f6883d167bc2c4bca8008e= ceb08c3c3a0e9 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -57,3 +57,4 @@ obj-$(CONFIG_CORESIGHT_DUMMY) +=3D coresight-dummy.o obj-$(CONFIG_CORESIGHT_CTCU) +=3D coresight-ctcu.o coresight-ctcu-y :=3D coresight-ctcu-core.o obj-$(CONFIG_CORESIGHT_KUNIT_TESTS) +=3D coresight-kunit-tests.o +obj-$(CONFIG_CORESIGHT_TRBE_KUNIT_TESTS) +=3D coresight-trbe-kunit-tests.o diff --git a/drivers/hwtracing/coresight/coresight-trbe-kunit-tests.c b/dri= vers/hwtracing/coresight/coresight-trbe-kunit-tests.c new file mode 100644 index 0000000000000000000000000000000000000000..836f76dce155d533f9076e85dc9= 7ba25221b7bbf --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-trbe-kunit-tests.c @@ -0,0 +1,536 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include + +#include "coresight-priv.h" +#include "coresight-trbe.h" + +MODULE_IMPORT_NS("EXPORTED_FOR_KUNIT_TESTING"); + +static void test_compute_offset(struct kunit *test) +{ + struct perf_output_handle handle =3D { 0 }; + struct trbe_buf buf =3D { 0 }; + struct trbe_cpudata cpudata =3D { .trbe_align =3D PAGE_SIZE }; + unsigned long limit; + + if (!static_branch_unlikely(&trbe_trigger_mode_bypass)) + return; + + cpudata.trbe_hw_align =3D 1; + + buf.nr_pages =3D SZ_1M / SZ_4K; + buf.cpudata =3D &cpudata; + + handle.rb =3D (void *)&buf; + + /* + * ### : Free space, $$$ : Filled space + * + * |################|################| + * `head `wakeup + * `tail `limit + */ + handle.head =3D 0; + handle.size =3D SZ_1M; + handle.wakeup =3D SZ_1M / 2; + + limit =3D __trbe_normal_offset(&handle); + KUNIT_ASSERT_EQ(test, limit, SZ_1M / 2); + + /* + * |################|################| + * `head `wakeup `tail + * `limit + */ + handle.head =3D 0; + handle.size =3D SZ_1M - 1; + handle.wakeup =3D SZ_1M / 2; + + limit =3D __trbe_normal_offset(&handle); + KUNIT_ASSERT_EQ(test, limit, SZ_1M / 2); + + /* + * |#################################| + * `head `tail + * `wakeup `limit + */ + handle.head =3D 0; + handle.size =3D SZ_1M - 1; + handle.wakeup =3D 0; + + limit =3D __trbe_normal_offset(&handle); + KUNIT_ASSERT_EQ(test, limit, 0); + + /* + * |#################################| + * `head `tail + * `wakeup + * `limit + */ + handle.head =3D 0; + handle.size =3D SZ_1M - 1; + handle.wakeup =3D SZ_1M; + + limit =3D __trbe_normal_offset(&handle); + KUNIT_ASSERT_EQ(test, limit, SZ_1M - SZ_4K); + + /* + * |$$$$$$$$$$$$$$$$|########|#######| + * `head `tail + * `wakeup + * `limit + */ + handle.head =3D SZ_1M / 2; + handle.size =3D SZ_1M / 2 - 1; + handle.wakeup =3D SZ_1M * 3 / 4; + + limit =3D __trbe_normal_offset(&handle); + KUNIT_ASSERT_EQ(test, limit, SZ_1M * 3 / 4); + + /* + * |$$$$$$$$|$$$$$$$|################| + * `head `tail + * `wakeup + * `limit + */ + handle.head =3D SZ_1M / 2; + handle.size =3D SZ_1M / 2 - 1; + handle.wakeup =3D SZ_1M * 1 / 4; + + limit =3D __trbe_normal_offset(&handle); + KUNIT_ASSERT_EQ(test, limit, SZ_1M - SZ_4K); + + /* + * |$$$$$$$$$$$$$$$$|################| + * `head `tail + * `wakeup + * `limit + */ + handle.head =3D SZ_1M / 2; + handle.size =3D SZ_1M / 2 - 1; + handle.wakeup =3D SZ_1M - 1; + + limit =3D __trbe_normal_offset(&handle); + KUNIT_ASSERT_EQ(test, limit, SZ_1M - SZ_4K); + + /* + * |#########|$$$$$$$$$$|########|###| + * `tail `head `wakeup + * `limit + */ + handle.head =3D SZ_1M * 3 / 4; + handle.size =3D SZ_1M / 2; + handle.wakeup =3D handle.head + SZ_1M / 8; + + limit =3D __trbe_normal_offset(&handle); + KUNIT_ASSERT_EQ(test, limit, SZ_1M * 7 / 8); + + /* + * |####|####|$$$$$$$$$$|############| + * `tail `head + * `wakeup + * `limit + */ + handle.head =3D SZ_1M * 3 / 4; + handle.size =3D SZ_1M / 2; + handle.wakeup =3D SZ_1M + SZ_1M / 8; + + limit =3D __trbe_normal_offset(&handle); + KUNIT_ASSERT_EQ(test, limit, SZ_1M); + + /* + * |#######|########|$$$$$$$$$$$$$$$$| + * `head `wakeup `>tail + * `limit + */ + handle.head =3D SZ_1M; + handle.wakeup =3D SZ_1M + SZ_1M / 8; + handle.size =3D SZ_1M / 2; + + limit =3D __trbe_normal_offset(&handle); + KUNIT_ASSERT_EQ(test, limit, SZ_1M / 8); + + /* + * |#######|$$$$$$$$$$$$$$$$$|#######| + * `tail `head + * `wakeup + * `limit + */ + handle.head =3D SZ_1M * 3 / 4; + handle.size =3D SZ_1M / 2; + handle.wakeup =3D SZ_1M + SZ_1M / 4; + + limit =3D __trbe_normal_offset(&handle); + KUNIT_ASSERT_EQ(test, limit, SZ_1M); + + /* + * |#######|$$$$$$$$|$$$$$$$$|#######| + * `tail `wakeup `head + * `limit + */ + handle.head =3D SZ_1M * 3 / 4; + handle.size =3D SZ_1M / 2; + handle.wakeup =3D SZ_1M + SZ_1M / 2; + + limit =3D __trbe_normal_offset(&handle); + KUNIT_ASSERT_EQ(test, limit, SZ_1M); + + /* + * |$$$$$$$|########|########|$$$$$$$| + * `head `wakeup `tail + * `limit + */ + handle.head =3D SZ_1M / 4; + handle.size =3D SZ_1M / 2; + handle.wakeup =3D SZ_1M / 2; + + limit =3D __trbe_normal_offset(&handle); + KUNIT_ASSERT_EQ(test, limit, SZ_1M / 2); + + /* + * |$$$$$$$|#################|$$$$$$$| + * `head `tail + * `wakeup + * `limit + */ + handle.head =3D SZ_1M / 4; + handle.size =3D SZ_1M / 2; + handle.wakeup =3D SZ_1M * 3 / 4; + + limit =3D __trbe_normal_offset(&handle); + KUNIT_ASSERT_EQ(test, limit, SZ_1M * 3 / 4); + + /* + * |$$$$$$$|#################|$$$$$$$| + * `wakeup `head `tail + * `limit + */ + handle.head =3D SZ_1M / 4; + handle.size =3D SZ_1M / 2; + handle.wakeup =3D 0; + + limit =3D __trbe_normal_offset(&handle); + KUNIT_ASSERT_EQ(test, limit, SZ_1M * 3 / 4); + + /* + * |$$$$$$|$$$$$$$$$$$$$$$$$$$$$$$$$$| + * `head + * `tail + */ + handle.head =3D SZ_1M / 4; + handle.size =3D 0; + + limit =3D __trbe_normal_offset(&handle); + KUNIT_ASSERT_EQ(test, limit, 0); + + /* + * |$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$|#$| + * `head + * `tail + */ + handle.head =3D SZ_1M - SZ_1K * 2; + handle.size =3D SZ_1K; + handle.wakeup =3D 0; + + limit =3D __trbe_normal_offset(&handle); + KUNIT_ASSERT_EQ(test, limit, 0); +} + +static void test_compute_offset_and_counter(struct kunit *test) +{ + struct perf_output_handle handle =3D { 0 }; + struct trbe_buf buf =3D { 0 }; + struct trbe_cpudata cpudata =3D { .trbe_align =3D PAGE_SIZE }; + unsigned long limit; + u64 count; + + if (static_branch_unlikely(&trbe_trigger_mode_bypass)) + return; + + cpudata.trbe_hw_align =3D 1; + + buf.nr_pages =3D SZ_1M / SZ_4K; + buf.cpudata =3D &cpudata; + + handle.rb =3D (void *)&buf; + + /* + * ### : Free space, $$$ : Filled space + * + * |################|################| + * `head `wakeup `limit + * `tail + * `----- count ----' + */ + handle.head =3D 0; + handle.size =3D SZ_1M; + handle.wakeup =3D SZ_1M / 2; + + limit =3D __trbe_normal_offset(&handle); + buf.trbe_limit =3D limit; + count =3D __trbe_normal_trigger_count(&handle); + + KUNIT_ASSERT_EQ(test, limit, SZ_1M); + KUNIT_ASSERT_EQ(test, count, SZ_1M / 2); + + /* + * |################|################| + * `head `wakeup `tail + * `limit + * `----- count ----' + */ + handle.head =3D 0; + handle.size =3D SZ_1M - 1; + handle.wakeup =3D SZ_1M / 2; + + limit =3D __trbe_normal_offset(&handle); + buf.trbe_limit =3D limit; + count =3D __trbe_normal_trigger_count(&handle); + + KUNIT_ASSERT_EQ(test, limit, SZ_1M - SZ_4K); + KUNIT_ASSERT_EQ(test, count, SZ_1M / 2); + + /* + * |#################################| + * `head `tail + * `wakeup `limit + */ + handle.head =3D 0; + handle.size =3D SZ_1M - 1; + handle.wakeup =3D 0; + + limit =3D __trbe_normal_offset(&handle); + buf.trbe_limit =3D limit; + count =3D __trbe_normal_trigger_count(&handle); + + KUNIT_ASSERT_EQ(test, limit, SZ_1M - SZ_4K); + KUNIT_ASSERT_EQ(test, count, 0); + + /* + * |#################################| + * `head `tail + * `wakeup + * `limit + */ + handle.head =3D 0; + handle.size =3D SZ_1M - 1; + handle.wakeup =3D SZ_1M; + + limit =3D __trbe_normal_offset(&handle); + buf.trbe_limit =3D limit; + count =3D __trbe_normal_trigger_count(&handle); + + KUNIT_ASSERT_EQ(test, limit, SZ_1M - SZ_4K); + KUNIT_ASSERT_EQ(test, count, 0); + + /* + * |$$$$$$$$$$$$$$$$|########|#######| + * `head `tail + * `wakeup + * `limit + * [ count ] + */ + handle.head =3D SZ_1M / 2; + handle.size =3D SZ_1M / 2 - 1; + handle.wakeup =3D SZ_1M * 3 / 4; + + limit =3D __trbe_normal_offset(&handle); + buf.trbe_limit =3D limit; + count =3D __trbe_normal_trigger_count(&handle); + + KUNIT_ASSERT_EQ(test, limit, SZ_1M - SZ_4K); + KUNIT_ASSERT_EQ(test, count, SZ_1M / 4); + + /* + * |$$$$$$$$|$$$$$$$|################| + * `head `tail + * `wakeup + * `limit + */ + handle.head =3D SZ_1M / 2; + handle.size =3D SZ_1M / 2 - 1; + handle.wakeup =3D SZ_1M * 1 / 4; + + limit =3D __trbe_normal_offset(&handle); + buf.trbe_limit =3D limit; + count =3D __trbe_normal_trigger_count(&handle); + + KUNIT_ASSERT_EQ(test, limit, SZ_1M - SZ_4K); + KUNIT_ASSERT_EQ(test, count, 0); + + /* + * |$$$$$$$$$$$$$$$$|################| + * `head `tail + * `wakeup + * `limit + */ + handle.head =3D SZ_1M / 2; + handle.size =3D SZ_1M / 2 - 1; + handle.wakeup =3D SZ_1M - 1; + + limit =3D __trbe_normal_offset(&handle); + buf.trbe_limit =3D limit; + count =3D __trbe_normal_trigger_count(&handle); + + KUNIT_ASSERT_EQ(test, limit, SZ_1M - SZ_4K); + KUNIT_ASSERT_EQ(test, count, 0); + + /* + * |#########|$$$$$$$$$$|########|###| + * `tail `head `wakeup + * `limit + * [ count ] + */ + handle.head =3D SZ_1M * 3 / 4; + handle.size =3D SZ_1M / 2; + handle.wakeup =3D handle.head + SZ_1M / 8; + + limit =3D __trbe_normal_offset(&handle); + buf.trbe_limit =3D limit; + count =3D __trbe_normal_trigger_count(&handle); + + KUNIT_ASSERT_EQ(test, limit, SZ_1M); + KUNIT_ASSERT_EQ(test, count, SZ_1M / 8); + + /* + * |####|####|$$$$$$$$$$|############| + * `tail `head + * `wakeup + * `limit + * [ count >>> + * >>> ] + */ + handle.head =3D SZ_1M * 3 / 4; + handle.size =3D SZ_1M / 2; + handle.wakeup =3D SZ_1M + SZ_1M / 8; + + limit =3D __trbe_normal_offset(&handle); + buf.trbe_limit =3D limit; + count =3D __trbe_normal_trigger_count(&handle); + + KUNIT_ASSERT_EQ(test, limit, SZ_1M); + KUNIT_ASSERT_EQ(test, count, SZ_1M / 2); + + /* + * |#######|########|$$$$$$$$$$$$$$$$| + * `head `wakeup `>tail + * `limit + * [ count ] + */ + handle.head =3D SZ_1M; + handle.wakeup =3D SZ_1M + SZ_1M / 8; + handle.size =3D SZ_1M / 2; + + limit =3D __trbe_normal_offset(&handle); + buf.trbe_limit =3D limit; + count =3D __trbe_normal_trigger_count(&handle); + + KUNIT_ASSERT_EQ(test, limit, SZ_1M / 2); + KUNIT_ASSERT_EQ(test, count, SZ_1M / 8); + + /* + * |#######|$$$$$$$$$$$$$$$$$|#######| + * `tail `head + * `wakeup + * `limit + * [ count > + * >>> ] + */ + handle.head =3D SZ_1M * 3 / 4; + handle.size =3D SZ_1M / 2; + handle.wakeup =3D SZ_1M + SZ_1M / 4; + + limit =3D __trbe_normal_offset(&handle); + buf.trbe_limit =3D limit; + count =3D __trbe_normal_trigger_count(&handle); + + KUNIT_ASSERT_EQ(test, limit, SZ_1M); + KUNIT_ASSERT_EQ(test, count, SZ_1M / 2); + + /* + * |#######|$$$$$$$$|$$$$$$$$|#######| + * `tail `wakeup `head + * `limit + * [ count > + * >>> ] + */ + handle.head =3D SZ_1M * 3 / 4; + handle.size =3D SZ_1M / 2; + handle.wakeup =3D SZ_1M + SZ_1M / 2; + + limit =3D __trbe_normal_offset(&handle); + buf.trbe_limit =3D limit; + count =3D __trbe_normal_trigger_count(&handle); + + KUNIT_ASSERT_EQ(test, limit, SZ_1M); + KUNIT_ASSERT_EQ(test, count, SZ_1M / 2); + + /* + * |$$$$$$$|########|########|$$$$$$$| + * `head `wakeup `tail + * `limit + * [ count ] + */ + handle.head =3D SZ_1M / 4; + handle.size =3D SZ_1M / 2; + handle.wakeup =3D SZ_1M / 2; + + limit =3D __trbe_normal_offset(&handle); + buf.trbe_limit =3D limit; + count =3D __trbe_normal_trigger_count(&handle); + + KUNIT_ASSERT_EQ(test, limit, SZ_1M * 3 / 4); + KUNIT_ASSERT_EQ(test, count, SZ_1M / 4); + + /* + * |$$$$$$$|#################|$$$$$$$| + * `head `tail + * `wakeup + * `limit + */ + handle.head =3D SZ_1M / 4; + handle.size =3D SZ_1M / 2; + handle.wakeup =3D SZ_1M * 3 / 4; + + limit =3D __trbe_normal_offset(&handle); + buf.trbe_limit =3D limit; + count =3D __trbe_normal_trigger_count(&handle); + + KUNIT_ASSERT_EQ(test, limit, SZ_1M * 3 / 4); + KUNIT_ASSERT_EQ(test, count, 0); + + /* + * |$$$$$$$|#################|$$$$$$$| + * `wakeup `head `tail + * `limit + */ + handle.head =3D SZ_1M / 4; + handle.size =3D SZ_1M / 2; + handle.wakeup =3D 0; + + limit =3D __trbe_normal_offset(&handle); + buf.trbe_limit =3D limit; + count =3D __trbe_normal_trigger_count(&handle); + + KUNIT_ASSERT_EQ(test, limit, SZ_1M * 3 / 4); + KUNIT_ASSERT_EQ(test, count, 0); +} + +static struct kunit_case coresight_trbe_testcases[] =3D { + KUNIT_CASE(test_compute_offset), + KUNIT_CASE(test_compute_offset_and_counter), + {} +}; + +static struct kunit_suite coresight_trbe_test_suite =3D { + .name =3D "coresight_trbe_test_suite", + .test_cases =3D coresight_trbe_testcases, +}; + +kunit_test_suites(&coresight_trbe_test_suite); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Leo Yan "); +MODULE_DESCRIPTION("Arm CoreSight TRBE KUnit tests"); diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtraci= ng/coresight/coresight-trbe.c index ee9993d518d2a41f0d709b7d0690b2dfe0bef2d9..25d42683ab74b55efa2e19a2d77= ab8ae2d68d228 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -54,92 +54,12 @@ enum trbe_fault_action { TRBE_FAULT_ACT_FATAL, }; =20 -struct trbe_buf { - /* - * Even though trbe_base represents vmap() - * mapped allocated buffer's start address, - * it's being as unsigned long for various - * arithmetic and comparision operations & - * also to be consistent with trbe_write & - * trbe_limit sibling pointers. - */ - unsigned long trbe_base; - /* The base programmed into the TRBE */ - unsigned long trbe_hw_base; - unsigned long trbe_limit; - unsigned long trbe_write; - unsigned long trbe_count; - int nr_pages; - void **pages; - bool snapshot; - struct trbe_cpudata *cpudata; -}; - -/* - * TRBE erratum list - * - * The errata are defined in arm64 generic cpu_errata framework. - * Since the errata work arounds could be applied individually - * to the affected CPUs inside the TRBE driver, we need to know if - * a given CPU is affected by the erratum. Unlike the other erratum - * work arounds, TRBE driver needs to check multiple times during - * a trace session. Thus we need a quicker access to per-CPU - * errata and not issue costly this_cpu_has_cap() everytime. - * We keep a set of the affected errata in trbe_cpudata, per TRBE. - * - * We rely on the corresponding cpucaps to be defined for a given - * TRBE erratum. We map the given cpucap into a TRBE internal number - * to make the tracking of the errata lean. - * - * This helps in : - * - Not duplicating the detection logic - * - Streamlined detection of erratum across the system - */ -#define TRBE_WORKAROUND_OVERWRITE_FILL_MODE 0 -#define TRBE_WORKAROUND_WRITE_OUT_OF_RANGE 1 -#define TRBE_NEEDS_DRAIN_AFTER_DISABLE 2 -#define TRBE_NEEDS_CTXT_SYNC_AFTER_ENABLE 3 -#define TRBE_IS_BROKEN 4 - -static int trbe_errata_cpucaps[] =3D { - [TRBE_WORKAROUND_OVERWRITE_FILL_MODE] =3D ARM64_WORKAROUND_TRBE_OVERWRITE= _FILL_MODE, - [TRBE_WORKAROUND_WRITE_OUT_OF_RANGE] =3D ARM64_WORKAROUND_TRBE_WRITE_OUT_= OF_RANGE, - [TRBE_NEEDS_DRAIN_AFTER_DISABLE] =3D ARM64_WORKAROUND_2064142, - [TRBE_NEEDS_CTXT_SYNC_AFTER_ENABLE] =3D ARM64_WORKAROUND_2038923, - [TRBE_IS_BROKEN] =3D ARM64_WORKAROUND_1902691, - -1, /* Sentinel, must be the last entry */ -}; - -/* The total number of listed errata in trbe_errata_cpucaps */ -#define TRBE_ERRATA_MAX (ARRAY_SIZE(trbe_errata_cpucaps) - 1) - /* * Safe limit for the number of bytes that may be overwritten * when ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE is triggered. */ #define TRBE_WORKAROUND_OVERWRITE_FILL_MODE_SKIP_BYTES 256 =20 -/* - * struct trbe_cpudata: TRBE instance specific data - * @trbe_flag - TRBE dirty/access flag support - * @trbe_hw_align - Actual TRBE alignment required for TRBPTR_EL1. - * @trbe_align - Software alignment used for the TRBPTR_EL1. - * @cpu - CPU this TRBE belongs to. - * @mode - Mode of current operation. (perf/disabled) - * @drvdata - TRBE specific drvdata - * @errata - Bit map for the errata on this TRBE. - */ -struct trbe_cpudata { - bool trbe_flag; - u64 trbe_hw_align; - u64 trbe_align; - int cpu; - enum cs_mode mode; - struct trbe_buf *buf; - struct trbe_drvdata *drvdata; - DECLARE_BITMAP(errata, TRBE_ERRATA_MAX); -}; - struct trbe_drvdata { struct trbe_cpudata __percpu *cpudata; struct perf_output_handle * __percpu *handle; @@ -150,7 +70,8 @@ struct trbe_drvdata { struct platform_device *pdev; }; =20 -DEFINE_STATIC_KEY_FALSE(trbe_trigger_mode_bypass); +VISIBLE_IF_KUNIT DEFINE_STATIC_KEY_FALSE(trbe_trigger_mode_bypass); +EXPORT_SYMBOL_IF_KUNIT(trbe_trigger_mode_bypass); =20 #define trbe_trigger_mode_need_bypass(cpudata) \ (trbe_may_overwrite_in_fill_mode((cpudata)) || \ @@ -333,8 +254,17 @@ static void __trbe_pad_buf(struct trbe_buf *buf, u64 o= ffset, int len) =20 static void trbe_pad_buf(struct perf_output_handle *handle, int len) { - struct trbe_buf *buf =3D etm_perf_sink_config(handle); - u64 head =3D PERF_IDX2OFF(handle->head, buf); + struct trbe_buf *buf; + u64 head; + + if (kunit_get_current_test()) { + handle->head +=3D len; + handle->size -=3D len; + return; + } + + buf =3D etm_perf_sink_config(handle); + head =3D PERF_IDX2OFF(handle->head, buf); =20 __trbe_pad_buf(buf, head, len); if (!buf->snapshot) @@ -383,9 +313,11 @@ static u64 trbe_min_trace_buf_size(struct perf_output_= handle *handle) * %%%% - Free area, disabled, trace will not be written * =3D=3D=3D=3D - Free area, padded with ETE_IGNORE_PACKET, trace will be = skipped */ -static unsigned long __trbe_normal_offset(struct perf_output_handle *handl= e) +VISIBLE_IF_KUNIT +unsigned long __trbe_normal_offset(struct perf_output_handle *handle) { - struct trbe_buf *buf =3D etm_perf_sink_config(handle); + struct trbe_buf *buf =3D + kunit_get_current_test() ? handle->rb : etm_perf_sink_config(handle); struct trbe_cpudata *cpudata =3D buf->cpudata; const u64 bufsize =3D buf->nr_pages * PAGE_SIZE; u64 limit =3D bufsize; @@ -525,9 +457,13 @@ static unsigned long __trbe_normal_offset(struct perf_= output_handle *handle) return 0; } =20 -static u64 __trbe_normal_trigger_count(struct perf_output_handle *handle) +EXPORT_SYMBOL_IF_KUNIT(__trbe_normal_offset); + +VISIBLE_IF_KUNIT +u64 __trbe_normal_trigger_count(struct perf_output_handle *handle) { - struct trbe_buf *buf =3D etm_perf_sink_config(handle); + struct trbe_buf *buf =3D + kunit_get_current_test() ? handle->rb : etm_perf_sink_config(handle); struct trbe_cpudata *cpudata =3D buf->cpudata; u64 limit, head, wakeup; u64 count =3D 0; @@ -558,6 +494,8 @@ static u64 __trbe_normal_trigger_count(struct perf_outp= ut_handle *handle) return count; } =20 +EXPORT_SYMBOL_IF_KUNIT(__trbe_normal_trigger_count); + static int trbe_normal_offset(struct perf_output_handle *handle) { struct trbe_buf *buf =3D etm_perf_sink_config(handle); diff --git a/drivers/hwtracing/coresight/coresight-trbe.h b/drivers/hwtraci= ng/coresight/coresight-trbe.h index 4c65d164a946ec9860825e7564196745b60d730b..8f90836b5f71d44213699ec1915= d59864863a4db 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.h +++ b/drivers/hwtracing/coresight/coresight-trbe.h @@ -17,8 +17,91 @@ #include #include =20 +#include +#include + #include "coresight-etm-perf.h" =20 +struct trbe_buf { + /* + * Even though trbe_base represents vmap() + * mapped allocated buffer's start address, + * it's being as unsigned long for various + * arithmetic and comparision operations & + * also to be consistent with trbe_write & + * trbe_limit sibling pointers. + */ + unsigned long trbe_base; + /* The base programmed into the TRBE */ + unsigned long trbe_hw_base; + unsigned long trbe_limit; + unsigned long trbe_write; + unsigned long trbe_count; + int nr_pages; + void **pages; + bool snapshot; + struct trbe_cpudata *cpudata; +}; + +/* + * TRBE erratum list + * + * The errata are defined in arm64 generic cpu_errata framework. + * Since the errata work arounds could be applied individually + * to the affected CPUs inside the TRBE driver, we need to know if + * a given CPU is affected by the erratum. Unlike the other erratum + * work arounds, TRBE driver needs to check multiple times during + * a trace session. Thus we need a quicker access to per-CPU + * errata and not issue costly this_cpu_has_cap() everytime. + * We keep a set of the affected errata in trbe_cpudata, per TRBE. + * + * We rely on the corresponding cpucaps to be defined for a given + * TRBE erratum. We map the given cpucap into a TRBE internal number + * to make the tracking of the errata lean. + * + * This helps in : + * - Not duplicating the detection logic + * - Streamlined detection of erratum across the system + */ +#define TRBE_WORKAROUND_OVERWRITE_FILL_MODE 0 +#define TRBE_WORKAROUND_WRITE_OUT_OF_RANGE 1 +#define TRBE_NEEDS_DRAIN_AFTER_DISABLE 2 +#define TRBE_NEEDS_CTXT_SYNC_AFTER_ENABLE 3 +#define TRBE_IS_BROKEN 4 + +static int trbe_errata_cpucaps[] =3D { + [TRBE_WORKAROUND_OVERWRITE_FILL_MODE] =3D ARM64_WORKAROUND_TRBE_OVERWRITE= _FILL_MODE, + [TRBE_WORKAROUND_WRITE_OUT_OF_RANGE] =3D ARM64_WORKAROUND_TRBE_WRITE_OUT_= OF_RANGE, + [TRBE_NEEDS_DRAIN_AFTER_DISABLE] =3D ARM64_WORKAROUND_2064142, + [TRBE_NEEDS_CTXT_SYNC_AFTER_ENABLE] =3D ARM64_WORKAROUND_2038923, + [TRBE_IS_BROKEN] =3D ARM64_WORKAROUND_1902691, + -1, /* Sentinel, must be the last entry */ +}; + +/* The total number of listed errata in trbe_errata_cpucaps */ +#define TRBE_ERRATA_MAX (ARRAY_SIZE(trbe_errata_cpucaps) - 1) + +/* + * struct trbe_cpudata: TRBE instance specific data + * @trbe_flag - TRBE dirty/access flag support + * @trbe_hw_align - Actual TRBE alignment required for TRBPTR_EL1. + * @trbe_align - Software alignment used for the TRBPTR_EL1. + * @cpu - CPU this TRBE belongs to. + * @mode - Mode of current operation. (perf/disabled) + * @drvdata - TRBE specific drvdata + * @errata - Bit map for the errata on this TRBE. + */ +struct trbe_cpudata { + bool trbe_flag; + u64 trbe_hw_align; + u64 trbe_align; + int cpu; + enum cs_mode mode; + struct trbe_buf *buf; + struct trbe_drvdata *drvdata; + DECLARE_BITMAP(errata, TRBE_ERRATA_MAX); +}; + static inline bool is_trbe_available(void) { u64 aa64dfr0 =3D read_sysreg_s(SYS_ID_AA64DFR0_EL1); @@ -153,3 +236,9 @@ static inline void set_trbe_base_pointer(unsigned long = addr) WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE)); write_sysreg_s(addr, SYS_TRBBASER_EL1); } + +#if IS_ENABLED(CONFIG_KUNIT) +DECLARE_STATIC_KEY_FALSE(trbe_trigger_mode_bypass); +unsigned long __trbe_normal_offset(struct perf_output_handle *handle); +u64 __trbe_normal_trigger_count(struct perf_output_handle *handle); +#endif --=20 2.34.1 From nobody Mon Dec 1 21:30:54 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3DBD630EF7A; Mon, 1 Dec 2025 11:23:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588184; cv=none; b=sKcdOawW8ijkTTVT2XdIfNErMmYHgAeyOAx4PSb4BtmBLY7xWApg2FMzsDn0TmnJKstqQPj+6daZGa51dEhXBV9RYEeEqpJxUlrfsrviIAzq7ENOICMjpH9GdBF8f8yXjTpGsN5/fg+9lVlRTEH4qm51DRUQ+k78iANPErvxauw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764588184; c=relaxed/simple; bh=CnLBhlCtv3ztxvAipwj7G3XfegrAX9IB1iFyGNaXBw4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=oq8hzY/KISFCTGVAb8RW1ML2BCmmsrgj6AsloTwjnaQGoWuecUtbeu211a0u7XmXfJGX2HF2LnzQbv9Sq6QUQq7ll9bd6/ajwlEpvAsWc5krHslutpH5HoZj7oA13egI+SJzRZGltxyPTligkFWJ3JJO1kMBK+D0Q7xgw6ZiZsI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 48F431595; Mon, 1 Dec 2025 03:22:54 -0800 (PST) Received: from e132581.arm.com (e132581.arm.com [10.1.196.87]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 28E3E3F59E; Mon, 1 Dec 2025 03:22:59 -0800 (PST) From: Leo Yan Date: Mon, 01 Dec 2025 11:22:09 +0000 Subject: [PATCH 19/19] perf: cs-etm: Set watermark for AUX trace Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251201-trbe_buffer_refactor_v1-1-v1-19-7da32b076b28@arm.com> References: <20251201-trbe_buffer_refactor_v1-1-v1-0-7da32b076b28@arm.com> In-Reply-To: <20251201-trbe_buffer_refactor_v1-1-v1-0-7da32b076b28@arm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Anshuman Khandual , Yeoreum Yun , Will Deacon , Mark Rutland , Tamas Petz , Tamas Zsoldos , Arnaldo Carvalho de Melo , Namhyung Kim , Jiri Olsa , Ian Rogers , Adrian Hunter Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Leo Yan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764588125; l=1279; i=leo.yan@arm.com; s=20250604; h=from:subject:message-id; bh=CnLBhlCtv3ztxvAipwj7G3XfegrAX9IB1iFyGNaXBw4=; b=JCZvKgPoppyGZi9uQ3L79JfnjD3WKDxqWgyj3lepFbASg8s6jT6fcDbvQWEeQja+YC/BoKXNE m0yvrnCCStzDA76g5U7+URc7obMXrMG0frUfWc8f9+16Mg8axWh8mAu X-Developer-Key: i=leo.yan@arm.com; a=ed25519; pk=k4BaDbvkCXzBFA7Nw184KHGP5thju8lKqJYIrOWxDhI= The default watermark is half of the total buffer size. In many cases, the tool can not be notified with sufficient free space, especially when profiling with small AUX buffer (e.g., 64KiB). Setting watermark to quarter of the buffer to notifies the tool to read data earlier and prevents the data loss. Signed-off-by: Leo Yan --- tools/perf/arch/arm/util/cs-etm.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/tools/perf/arch/arm/util/cs-etm.c b/tools/perf/arch/arm/util/c= s-etm.c index ea891d12f8f40beebf8dee1d3db71cad701f5666..649b8b0d0f92b4af45fb97db9da= 3c5ccf24a978b 100644 --- a/tools/perf/arch/arm/util/cs-etm.c +++ b/tools/perf/arch/arm/util/cs-etm.c @@ -424,6 +424,13 @@ static int cs_etm_recording_options(struct auxtrace_re= cord *itr, pr_debug2("%s snapshot size: %zu\n", CORESIGHT_ETM_PMU_NAME, opts->auxtrace_snapshot_size); =20 + if (!opts->auxtrace_snapshot_mode && !opts->auxtrace_sample_mode) { + size_t aw =3D opts->auxtrace_mmap_pages * (size_t)page_size / 4; + u32 aux_watermark =3D aw > UINT_MAX ? UINT_MAX : aw; + + cs_etm_evsel->core.attr.aux_watermark =3D aux_watermark; + } + /* * To obtain the auxtrace buffer file descriptor, the auxtrace * event must come first. --=20 2.34.1