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[79.32.234.137]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-64751035c3bsm12862898a12.19.2025.12.01.10.14.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Dec 2025 10:14:54 -0800 (PST) From: Anna Maniscalco Date: Mon, 01 Dec 2025 19:14:36 +0100 Subject: [PATCH v3] drm/msm: Fix a7xx per pipe register programming Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251201-gras_nc_mode_fix-v3-1-92a8a10d91d0@gmail.com> X-B4-Tracking: v=1; b=H4sIAAvbLWkC/23N0QqCMBTG8VeJc91iZ+q0rnqPCFnzqAfSxRajE N+9KQRFXf4/OL8zQSDPFOCwmcBT5MBuTJFtN2B7M3YkuEkNSqoCUWnReRPq0daDa6hu+SFKpXK iQmqT7SGd3TyleSVP59Q9h7vzz/VDxGV9Y+UvFlGgKKy0rUadS2yP3WD4urNugAWL6hOo/gAqA TrLbWPKS4XyC5jn+QW7QeGQ8QAAAA== X-Change-ID: 20251126-gras_nc_mode_fix-7224ee506a39 To: Rob Clark , Sean Paul , Konrad Dybcio , Akhil P Oommen , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Antonino Maniscalco Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org, Anna Maniscalco X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764612893; l=8104; i=anna.maniscalco2000@gmail.com; s=20240815; h=from:subject:message-id; bh=L1+oJOb+t8duMnbQpmbgUlKeEuct+2pj/S1LXw+5x4E=; b=Xl5ZhQaztNVoSbuE9N0LIYwINJ6SjcbjDSYO2J0ofPyETSCi9Q78mb1C/B0E5oNJod7c1jCep Zhmx/UODO3+CU25Zelwvnh7sFHl0c0M8X2rAhSb6+tE98T7NKVR5wSW X-Developer-Key: i=anna.maniscalco2000@gmail.com; a=ed25519; pk=0zicFb38tVla+iHRo4kWpOMsmtUrpGBEa7LkFF81lyY= GEN7_GRAS_NC_MODE_CNTL was only programmed for BR and not for BV pipe but it needs to be programmed for both. Program both pipes in hw_init and introducea separate reglist for it in order to add this register to the dynamic reglist which supports restoring registers per pipe. Fixes: 91389b4e3263 ("drm/msm/a6xx: Add a pwrup_list field to a6xx_info") Cc: stable@vger.kernel.org Reviewed-by: Akhil P Oommen Signed-off-by: Anna Maniscalco --- Changes in v3: - Collected Rb tags - Went back to using PIPE_{BR, BV, NONE} enum values - Link to v2: https://lore.kernel.org/r/20251128-gras_nc_mode_fix-v2-1-634c= da7b810f@gmail.com Changes in v2: - Added missing Cc: stable to commit - Added pipe_regs to all 7xx gens - Null check pipe_regs in a7xx_patch_pwrup_reglist - Added parentheses around bitwise and in a7xx_patch_pwrup_reglist - Use A7XX_PIPE_{BR, BV, NONE} enum values - Link to v1: https://lore.kernel.org/r/20251127-gras_nc_mode_fix-v1-1-5c0c= f616401f@gmail.com --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 12 ++++++++++- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 34 +++++++++++++++++++++++++++= ---- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + drivers/gpu/drm/msm/adreno/adreno_gpu.h | 13 ++++++++++++ 4 files changed, 55 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/ms= m/adreno/a6xx_catalog.c index 29107b362346..c749448e75be 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -1376,7 +1376,6 @@ static const uint32_t a7xx_pwrup_reglist_regs[] =3D { REG_A6XX_UCHE_MODE_CNTL, REG_A6XX_RB_NC_MODE_CNTL, REG_A6XX_RB_CMP_DBG_ECO_CNTL, - REG_A7XX_GRAS_NC_MODE_CNTL, REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, REG_A6XX_UCHE_GBIF_GX_CONFIG, REG_A6XX_UCHE_CLIENT_PF, @@ -1448,6 +1447,12 @@ static const u32 a750_ifpc_reglist_regs[] =3D { =20 DECLARE_ADRENO_REGLIST_LIST(a750_ifpc_reglist); =20 +static const struct adreno_reglist_pipe a7xx_dyn_pwrup_reglist_regs[] =3D { + { REG_A7XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, +}; + +DECLARE_ADRENO_REGLIST_PIPE_LIST(a7xx_dyn_pwrup_reglist); + static const struct adreno_info a7xx_gpus[] =3D { { .chip_ids =3D ADRENO_CHIP_IDS(0x07000200), @@ -1491,6 +1496,7 @@ static const struct adreno_info a7xx_gpus[] =3D { .hwcg =3D a730_hwcg, .protect =3D &a730_protect, .pwrup_reglist =3D &a7xx_pwrup_reglist, + .dyn_pwrup_reglist =3D &a7xx_dyn_pwrup_reglist, .gbif_cx =3D a640_gbif, .gmu_cgc_mode =3D 0x00020000, }, @@ -1513,6 +1519,7 @@ static const struct adreno_info a7xx_gpus[] =3D { .hwcg =3D a740_hwcg, .protect =3D &a730_protect, .pwrup_reglist =3D &a7xx_pwrup_reglist, + .dyn_pwrup_reglist =3D &a7xx_dyn_pwrup_reglist, .gbif_cx =3D a640_gbif, .gmu_chipid =3D 0x7020100, .gmu_cgc_mode =3D 0x00020202, @@ -1547,6 +1554,7 @@ static const struct adreno_info a7xx_gpus[] =3D { .hwcg =3D a740_hwcg, .protect =3D &a730_protect, .pwrup_reglist =3D &a7xx_pwrup_reglist, + .dyn_pwrup_reglist =3D &a7xx_dyn_pwrup_reglist, .ifpc_reglist =3D &a750_ifpc_reglist, .gbif_cx =3D a640_gbif, .gmu_chipid =3D 0x7050001, @@ -1589,6 +1597,7 @@ static const struct adreno_info a7xx_gpus[] =3D { .a6xx =3D &(const struct a6xx_info) { .protect =3D &a730_protect, .pwrup_reglist =3D &a7xx_pwrup_reglist, + .dyn_pwrup_reglist =3D &a7xx_dyn_pwrup_reglist, .ifpc_reglist =3D &a750_ifpc_reglist, .gbif_cx =3D a640_gbif, .gmu_chipid =3D 0x7090100, @@ -1623,6 +1632,7 @@ static const struct adreno_info a7xx_gpus[] =3D { .hwcg =3D a740_hwcg, .protect =3D &a730_protect, .pwrup_reglist =3D &a7xx_pwrup_reglist, + .dyn_pwrup_reglist =3D &a7xx_dyn_pwrup_reglist, .gbif_cx =3D a640_gbif, .gmu_chipid =3D 0x70f0000, .gmu_cgc_mode =3D 0x00020222, diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 0200a7e71cdf..afde8867e260 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -849,9 +849,16 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) min_acc_len_64b << 3 | hbb_lo << 1 | ubwc_mode); =20 - if (adreno_is_a7xx(adreno_gpu)) - gpu_write(gpu, REG_A7XX_GRAS_NC_MODE_CNTL, - FIELD_PREP(GENMASK(8, 5), hbb_lo)); + if (adreno_is_a7xx(adreno_gpu)) { + for (u32 pipe_id =3D PIPE_BR; pipe_id <=3D PIPE_BV; pipe_id++) { + gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST, + A7XX_CP_APERTURE_CNTL_HOST_PIPE(pipe_id)); + gpu_write(gpu, REG_A7XX_GRAS_NC_MODE_CNTL, + FIELD_PREP(GENMASK(8, 5), hbb_lo)); + } + gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST, + A7XX_CP_APERTURE_CNTL_HOST_PIPE(PIPE_NONE)); + } =20 gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, min_acc_len_64b << 23 | hbb_lo << 21); @@ -865,9 +872,11 @@ static void a7xx_patch_pwrup_reglist(struct msm_gpu *g= pu) struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); const struct adreno_reglist_list *reglist; + const struct adreno_reglist_pipe_list *dyn_pwrup_reglist; void *ptr =3D a6xx_gpu->pwrup_reglist_ptr; struct cpu_gpu_lock *lock =3D ptr; u32 *dest =3D (u32 *)&lock->regs[0]; + u32 dyn_pwrup_reglist_count =3D 0; int i; =20 lock->gpu_req =3D lock->cpu_req =3D lock->turn =3D 0; @@ -907,7 +916,24 @@ static void a7xx_patch_pwrup_reglist(struct msm_gpu *g= pu) * (
), and the length is * stored as number for triplets in dynamic_list_len. */ - lock->dynamic_list_len =3D 0; + dyn_pwrup_reglist =3D adreno_gpu->info->a6xx->dyn_pwrup_reglist; + if (dyn_pwrup_reglist) { + for (u32 pipe_id =3D PIPE_BR; pipe_id <=3D PIPE_BV; pipe_id++) { + gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST, + A7XX_CP_APERTURE_CNTL_HOST_PIPE(pipe_id)); + for (i =3D 0; i < dyn_pwrup_reglist->count; i++) { + if ((dyn_pwrup_reglist->regs[i].pipe & BIT(pipe_id)) =3D=3D 0) + continue; + *dest++ =3D A7XX_CP_APERTURE_CNTL_HOST_PIPE(pipe_id); + *dest++ =3D dyn_pwrup_reglist->regs[i].offset; + *dest++ =3D gpu_read(gpu, dyn_pwrup_reglist->regs[i].offset); + dyn_pwrup_reglist_count++; + } + } + gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST, + A7XX_CP_APERTURE_CNTL_HOST_PIPE(PIPE_NONE)); + } + lock->dynamic_list_len =3D dyn_pwrup_reglist_count; } =20 static int a7xx_preempt_start(struct msm_gpu *gpu) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.h index 6820216ec5fc..4eaa04711246 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -45,6 +45,7 @@ struct a6xx_info { const struct adreno_reglist *hwcg; const struct adreno_protect *protect; const struct adreno_reglist_list *pwrup_reglist; + const struct adreno_reglist_pipe_list *dyn_pwrup_reglist; const struct adreno_reglist_list *ifpc_reglist; const struct adreno_reglist *gbif_cx; const struct adreno_reglist_pipe *nonctxt_reglist; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index 0f8d3de97636..1d0145f8b3ec 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -188,6 +188,19 @@ static const struct adreno_reglist_list name =3D { \ .count =3D ARRAY_SIZE(name ## _regs), \ }; =20 +struct adreno_reglist_pipe_list { + /** @reg: List of register **/ + const struct adreno_reglist_pipe *regs; + /** @count: Number of registers in the list **/ + u32 count; +}; + +#define DECLARE_ADRENO_REGLIST_PIPE_LIST(name) \ +static const struct adreno_reglist_pipe_list name =3D { \ + .regs =3D name ## _regs, \ + .count =3D ARRAY_SIZE(name ## _regs), \ +}; + struct adreno_gpu { struct msm_gpu base; const struct adreno_info *info; --- base-commit: 7bc29d5fb6faff2f547323c9ee8d3a0790cd2530 change-id: 20251126-gras_nc_mode_fix-7224ee506a39 Best regards, --=20 Anna Maniscalco