From nobody Mon Dec 1 21:30:48 2025 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 464B93054F2 for ; Mon, 1 Dec 2025 12:37:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764592680; cv=none; b=JKkNU9WCcLavd6WEUi8I3wZBtUQMc1MRh822N9DKr2R7kqcavy6dmmddiNmFkfFMcm+5i1oPzycaJhG0eeGPefNE8Mo8CEY23Nntt7KOPKhzySeqMRxtzJaM7Jfmw5rI6QmJX7qAqeHO5CrSO62LZ+5JddI+V6gFP4edYabDDNw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764592680; c=relaxed/simple; bh=3Vvq8LPwxXKHOKoZ+a6kHlkt56selPRWjocT3g952Go=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:To:Cc; b=DXYxYFve26RjaE77G/VwZYEjlK8G51o8Y9pSqKsH2K+lWDYUBquOsbajEmPyOez0SPPJ1F24RL0ADKBotx5QXzvARv30P/g4eP08Wx5v/34k9tdRr5F2vPfheCNIb1A1GQIZg6AQb+JGdGW5lzkpimhHK3NEHjltSc1GWccRB8Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=REck/zTJ; arc=none smtp.client-ip=209.85.128.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="REck/zTJ" Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-47790b080e4so20014535e9.3 for ; Mon, 01 Dec 2025 04:37:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1764592675; x=1765197475; darn=vger.kernel.org; h=cc:to:message-id:content-transfer-encoding:mime-version:subject :date:from:from:to:cc:subject:date:message-id:reply-to; bh=Th9QIGTGx5TubvrIKd4rYbZwHElm6Jjolg9pSmpCDxM=; b=REck/zTJqePa188rPcS/rLzyNHcL9vCzxPW0T8s60NuOLmFZNzxl4YlH84iJ+Byid4 6MYR0h3OV0XAapcmguQs2CneqqgjqfWejEXhezEKoT/NspxU/sCQJEh+EO8VRVwzy7Ai shUvSjyVLLWWeNyXDy8cwUxA0jN9MM9ND5O8eN9NIRaMhmV6yEc9GbbM/5FlivIljJ8w nU6s8qgLF+Lce5FYDJH9Q1rKNBqKvNlN9FUgceQv+Wtci6zmRr+RWbbjETxh/S0GvGyy ed1dqWOjyeaMU8wmLq5JH8usi/viCFQ6VFLV6tOXw1SY96ty1rUbqeHbPQJAMNXQUUhp J1tA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764592675; x=1765197475; h=cc:to:message-id:content-transfer-encoding:mime-version:subject :date:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=Th9QIGTGx5TubvrIKd4rYbZwHElm6Jjolg9pSmpCDxM=; b=XWSrH8E+BGElTlfXK92yjhGpzWc8m29XdLFl3/I1uJ/4zN5q91IB6LDQyNX2WDeOYP sokmoRkDzXk1mr4oYk8bNhbTE7KePEkXsJoLftGyB4PKexxuJ3fr4zesCkFEiIXruQie Jgs23Eql11+uUUWuYQYlos+atHCy2AwwgxlLkMUrmZGfRRnwWUsY11Yu38oLyvEweI2c a5fV93WSQnHVnbY1bc7ZSgjD3Yy3UjKK9ublN05VXfWZkgR+MCBroTQ+cim9PcwBmNO0 nUI1RKNyUpYaFAa2pHCwDs4MIe55+V5QKp7+HxLIR1F1irAaedon6tp8OpdT5cnf6YPc cE9g== X-Forwarded-Encrypted: i=1; AJvYcCXP4u2VqdHHAnRT1uloaMJtTbNCpUG/fOFjvcYoSK8bpEXJ/2ZLcc0FKTYc/87Drolu+dvGwK0C0alegaM=@vger.kernel.org X-Gm-Message-State: AOJu0Yyf6t6yJp6dgY0i97fH+KHyUbAzHmn+RWCBhCbcHrvRQ79UTJ++ r2u6Y+WnSZlmUarvUNfcc7c2HbsAp4/Lw7zp3T3IDJey7tbI0Dmb8+VO X-Gm-Gg: ASbGncs3ou5+2f1Bplaj2fosVti72cyqGj1Rd684ovds9ALW2ilqQqBoOeq5SB3wPvq 57CZ9X3iCCzp/SZoEUy/szI+8RTpKu4s+YI1/Vb2h4gpj/hmM6Xcvj+p3Dh3L3f3wdvq5EmccB6 v3Werggg4HRm+1Ft6F+dxXnePKiBU3qX5bCASyQlmImmQgRvB83PZQBFe5EldWOsS/8T0AiVVwW 1ElyBMpo2zrhFu/GpOaypbSX//aSpPWh0xP+4UIPd/QDci/T0IIobe3TT/0lqq4sQe7Ej+nYVPp AxrzHOAVmNfqAmUJHb+NVjpEp/U6GMsBaJlfFe77niX9r5AGGsH5eFrFZcndGmS0JyTu6eazOU9 CrEo4vfpFy2guy/jxCrbyGpI7izxaBBfqpfUexXLtajrbrMEiCX2sJbwO10zViQ7yDDp7SZYqew Ra68sC5QnpSDR0nLHusrXDrSPf09jAUZ4cxk0Rb3FHMzCV6rHUouqW+fUt1AN/ya6YKROxKdUki g== X-Google-Smtp-Source: AGHT+IHuS7ih0/r1wtiTtCRYhrtbZkOYclnmpf83ik6Tv1jMFCB/iqtIuG69FulsayoBVRSfhmATZA== X-Received: by 2002:a05:600c:198e:b0:46e:33b2:c8da with SMTP id 5b1f17b1804b1-477c1133927mr378893455e9.32.1764592675414; Mon, 01 Dec 2025 04:37:55 -0800 (PST) Received: from alchark-surface.localdomain (bba-92-99-175-128.alshamil.net.ae. [92.99.175.128]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42e1cac4fd7sm26232131f8f.42.2025.12.01.04.37.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Dec 2025 04:37:54 -0800 (PST) From: Alexey Charkov Date: Mon, 01 Dec 2025 16:37:54 +0400 Subject: [PATCH] arm64: dts: rockchip: Add overlay for the PCIe slot on RK3576 EVB1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251201-evb1-pcie1-v1-1-c62bba5c1167@gmail.com> X-B4-Tracking: v=1; b=H4sIACGMLWkC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDI1NDQyML3dSyJEPdguTMVEPdxJRUYwvLRJMUU0sDJaCGgqLUtMwKsGHRsbW 1AFzmF8ZcAAAA X-Change-ID: 20251128-evb1-pcie1-ade389a4d590 To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Alexey Charkov X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2800; i=alchark@gmail.com; h=from:subject:message-id; bh=3Vvq8LPwxXKHOKoZ+a6kHlkt56selPRWjocT3g952Go=; b=owGbwMvMwCW2adGNfoHIK0sZT6slMWTq9qjM+691ivHks9cl6irvd3S+X5b8yzb0c/Wbn8kXV J+fCNi0t6OUhUGMi0FWTJFl7rcltlON+Gbt8vD4CjOHlQlkCAMXpwBMZIEsw1+5Xs2myvIjZp5G Zg+Mzn3R+X2u4btNSYuWg5DLtMXMx2cxMjzIdo88aLhfr3Zr9D1l2f+H4948v7/RWLmP55WDrXb xOUYA X-Developer-Key: i=alchark@gmail.com; a=openpgp; fpr=9DF6A43D95320E9ABA4848F5B2A2D88F1059D4A5 Rockchip RK3576 EVB1 has an onboard PCIe slot (PCIe 2.1, x4 mechanically, x1 electrically), but it shares pins and PHY with the only USB3 Type-A port. There is a physical switch next to the slot to transfer respective pins connection from the USB3 port to the PCIe slot, but apart from flipping the switch one must also disable the USB3 host controller to prevent it from claiming the PHY before the PCIe slot can become usable. Add an overlay to disable the USB3 host port and instead enable the PCIe slot, along with its pin configs. The physical switch must still be flipped to the "ON - PCIe1" position for this to work. Signed-off-by: Alexey Charkov --- arch/arm64/boot/dts/rockchip/Makefile | 4 +++ .../boot/dts/rockchip/rk3576-evb1-v10-pcie1.dtso | 31 ++++++++++++++++++= ++++ 2 files changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index ad684e3831bc..63198a618a2b 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -252,6 +252,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3576-armsom-sige5-v= 1.2-wifibt.dtb rk3576-armsom-sige5-v1.2-wifibt-dtbs :=3D rk3576-armsom-sige5.dtb \ rk3576-armsom-sige5-v1.2-wifibt.dtbo =20 +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3576-evb1-v10-pcie1.dtb +rk3576-evb1-v10-pcie1-dtbs :=3D rk3576-evb1-v10.dtb \ + rk3576-evb1-v10-pcie1.dtbo + dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-edgeble-neu6a-wifi.dtb rk3588-edgeble-neu6a-wifi-dtbs :=3D rk3588-edgeble-neu6a-io.dtb \ rk3588-edgeble-neu6a-wifi.dtbo diff --git a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10-pcie1.dtso b/arch= /arm64/boot/dts/rockchip/rk3576-evb1-v10-pcie1.dtso new file mode 100644 index 000000000000..dccf4a5debdb --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10-pcie1.dtso @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * DT-overlay to enable the onboard PCIe x1 slot, which shares pins and th= e PHY + * with the USB3 host port. + * To use the PCIe slot, apply this overlay and flip the Dial_Switch_1 rig= ht + * next to the PCIe slot to low state (labeled "ON - PCIe1"). USB3 host po= rt + * will be unusable (not even in 2.0 mode) + */ + +/dts-v1/; +/plugin/; + +#include + +&pcie1 { + pinctrl-0 =3D <&pcie1m0_pins &pcie1_rst>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&pinctrl { + pcie1 { + pcie1_rst: pcie1-rst { + rockchip,pins =3D <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&usb_drd1_dwc3 { + status =3D "disabled"; +}; --- base-commit: 7d0a66e4bb9081d75c82ec4957c50034cb0ea449 change-id: 20251128-evb1-pcie1-ade389a4d590 Best regards, --=20 Alexey Charkov