From nobody Mon Dec 1 22:37:13 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7EF0B277035 for ; Sun, 30 Nov 2025 14:41:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764513679; cv=none; b=PQmSnsaNdbU+vgbsWy+htz+scNKAbCFSJ5HNftXwzDgf7ke2I5Hk3iWztylp/nu/0jyPRfWfQneR49W4FZzboB+kGZCmVnAQDGQXkA0IuHDvFW2cD1PqxwJT0eMypVhCqppu63XZqngbfT2yUQCdVU3FYGhFFSY6JS8UkrRnV20= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764513679; c=relaxed/simple; bh=LePUQ8ME3FKvLmh/muRRq0EuwzJxHLZEsiBmHc85nx0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Uq3nGxFT/+WNVXSDuiaqzwPQhWxjsMSygDlLhnN0GZizyIUwnXsJFadWeeNzWIYCV/Y0mmbjEp93Cpiwr/ALKl/3XmPzjrTmJKnEJmuoDf4/B7vav1q9XcQgkRdQsplOln68IAS2F34fMzONYzAFSjWVQtgFxyPYMJuJi+36xck= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=o5bO2n2L; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=GwYhC7jU; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="o5bO2n2L"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="GwYhC7jU" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5AUECGR01169944 for ; Sun, 30 Nov 2025 14:41:17 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 6F5kQGXL7oxe+UU3twPOQhhoKB8f5LIFPh3+J/gy88k=; b=o5bO2n2LVIz3c1Cf LG+sLkh0zLi9qTy+HTvf1tlaKdemN2Glr7qV5O14uiozkf92PGP1fSGtAmctDUHk xBndE1Tx/rv2uOCaPvjna7yf4/nB553bPH4D8MgLk2AUraqqvZaNUIOgDr2+jMPx 1snIjysa8pwh3PR0b9rRFxNbRpMkFjhjdqpFzHanea6otVd8+chX8Ad7XzoPdX1I ZnHwFX8UDAswN2O08nGQ8IG+C+ai0fofCeAqGnRL8tj/to+t1zz4/jnBRLmE+FOA gu+gCq+in4/5zE+M8UXR2vtmOyroYAo3L/ztNx5Uafb+pYtT9xaqtg2pbYEb8PFI pH3ddw== Received: from mail-pf1-f200.google.com (mail-pf1-f200.google.com [209.85.210.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4aqt46a7m2-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Sun, 30 Nov 2025 14:41:16 +0000 (GMT) Received: by mail-pf1-f200.google.com with SMTP id d2e1a72fcca58-7ba9c366057so8993991b3a.1 for ; Sun, 30 Nov 2025 06:41:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1764513676; x=1765118476; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=6F5kQGXL7oxe+UU3twPOQhhoKB8f5LIFPh3+J/gy88k=; b=GwYhC7jUntP1K/mUBMFmQqi8HZ5hqUAxYpZK/S11Fa2GoYN3i03PozqGjqzuxS0s2C A91Uf/f7g9ndLFG8rK3DPFjBrG2usxI54OWH+j+bAOfYAYArerdLKs+OBoTLVknQ1AOa m/J4Xp02FHEr6e5yZrYLdq2T6VglRia3+PmouMkNXjaibHcyclbVlIRJeXDezvFhjGrD jNe32iGPTqo61rRsw0qh0t7XCMK3sgsmVD3roYJ0FwEFuc4Qd9iogCewKcMiXpvbiin+ gy9PQfU2udE4J3bbOscyhW70MntExI8JtqLlD/giw16A+VTQ9Jty3REC5hgBNsdW7evC 2tWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764513676; x=1765118476; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=6F5kQGXL7oxe+UU3twPOQhhoKB8f5LIFPh3+J/gy88k=; b=N14kwUT2kizg7+UXqbvf/jsu/6Xk+21YClPtz+3WufaB8GKDmPqHKxxvLGHW+RzjYp J8E8Q1tPij2x89x0zuWorkAJr9BURuS1bbMEd9NWEtEXH3Kh0MXtbtzfosTq6bALH+ET hlVHqsVcXcySX6QIvzdOREdRyDXqDQATg8/4QKZCg3CJmJ19kKotXOFj3tLa12ZM9H/o 0jdhab1Kc+8kgvIBrm4fqHXv/+jhw0CPti4VplBsCKS5XQ5rmHpBrApjOwP5w6BFWmoE 2YnmZSApeUBDINPQK2cwdML6Rox04n4jmMJa2uH2Q9bGYzNyqpTamRHIELD5ArsLpwJh wljA== X-Forwarded-Encrypted: i=1; AJvYcCXjSHnin4SjPrpURlhr8m6XQ8B1LsiDTUVu9cfkCxg/OBTTo4qHcJOzqUZmTTdLDNro0dXf6+mOTvVxraU=@vger.kernel.org X-Gm-Message-State: AOJu0YyQl/T59emXc9X+Qsmt0Pn/P3Berpi+hfyRbMUR/Pazi5J4rauj IyFXdbEMGaI/feZs4MGuGLQpp6mkyVKd+1PxyrmgzBx7TDkk4VcTBvVI1Y3x/BC65Wq4T+g+O5m LjWAdxGPfv9UeQNOFlnymQJfe/cLkkVtV8sVisMxiqizFRSNrAaFMWv+BvJCY5IvGx+E= X-Gm-Gg: ASbGncvCBP+g4bPLDqOxHJ/KTpyJ69je2inDUxSpSH84Tp9oG6SA8OemQtOjE+lzLPh VrWv2O9BfBxJIbbj0zspnJwH15KH2wckew7X382fKGL7r+PhB8c9K2JhtbIAoq9ff9o8KijrIVR 9sZq+HSLrb3aJHYClA9qSaZHsIiaoJNOdanpBjvF5tTSLHFTreiFmRpctSIaEfpkzWW0BsaZBeO r5vPmLOrvvh3UR5xIfyS03XqfFILsdGAAIXECRfII8RUgmPv+w8sjTTyk46L4OobaGIvsxeSlZT RgN6JVkvqJBuZiJniEiRrTDMHjQ/BeNt3WPEvx/bsM+LtCs0ixd7AnZ/MIt1DYBtpM/Yz7wKDWJ zeJwBSeafBVy2r0T69L0rMlQ1v7jxOkDmU7MuegHRw8rHtg== X-Received: by 2002:a05:6a00:a05:b0:7ac:edc4:fb92 with SMTP id d2e1a72fcca58-7ca87dd5677mr21596741b3a.11.1764513676167; Sun, 30 Nov 2025 06:41:16 -0800 (PST) X-Google-Smtp-Source: AGHT+IGOFcQtjx9M7v8B2u+sHSL8EvcAHDdy5PUWxM6DZRnU39bp8nnScYEhw+pTWRpeevkOgCmO0g== X-Received: by 2002:a05:6a00:a05:b0:7ac:edc4:fb92 with SMTP id d2e1a72fcca58-7ca87dd5677mr21596718b3a.11.1764513675650; Sun, 30 Nov 2025 06:41:15 -0800 (PST) Received: from hu-spratap-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7d54b003177sm5240065b3a.14.2025.11.30.06.41.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Nov 2025 06:41:15 -0800 (PST) From: Shivendra Pratap Date: Sun, 30 Nov 2025 20:11:03 +0530 Subject: [PATCH v10 2/3] firmware: qcom_scm: Support multiple waitq contexts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251130-multi_waitq_scm-v10-2-5a5f2f05a417@oss.qualcomm.com> References: <20251130-multi_waitq_scm-v10-0-5a5f2f05a417@oss.qualcomm.com> In-Reply-To: <20251130-multi_waitq_scm-v10-0-5a5f2f05a417@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Unnathi Chalicheemala , Shivendra Pratap , Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764513668; l=5981; i=shivendra.pratap@oss.qualcomm.com; s=20250710; h=from:subject:message-id; bh=/M4m1BOaVqqodTh3sK6zER8MxMbwYfx/S4aiwEEilzc=; b=bZHvyh5+IT64WwAGI/CtcDzrIdRUCBOhFeB/N7m5g9F6bYRq1VNX0+PHfmIJuYDXk1A6mwdb2 NxNcH4fML2PBlCDJCZXFJwemWpmUIpqU/TMm212XNyMBofdVlMSbXF3 X-Developer-Key: i=shivendra.pratap@oss.qualcomm.com; a=ed25519; pk=CpsuL7yZ8NReDPhGgq6Xn/SRoa59mAvzWOW0QZoo4gw= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTMwMDEyNiBTYWx0ZWRfX2jU/HB9B7eCS /mR7dG5VN8rFZXabrQ2Ace8KoY8wRB+5uPA6mBvL2i8FlKSDc0/nAHVl5ma6MouocrtcXFa6Z9b uFXPOtjUicsIZ9pf1aUlU+O2/P8UWKHz99K/H7nacZC9MzDHHwJ7R07rdsh1+jGc0sUE4Mj1FBR kWj+0iub3W0RojxIoQOuws1pXcBEpd1tglaICT51c1McLXokpby+5/bge1oMCo2l0RNTM54Oq+c 8Rh82BHCsen70joKWRd8d07UNhV/Beu1+J78eS0bePPrvGgYeAR3c8g5gCI35AYwFuDKCQSXkj1 wkVQdwEH/zhcRo4k0ln8upuRByPKej6lM8qPseWz7HI9F/3ojetm2NMWZ1+d6Fhq2h9+87/yk0L efbEzf4Z7fqleTI/yzwNy9FmfZ7k7A== X-Proofpoint-ORIG-GUID: PZdALkgtZhJC1yFQaPF_96nDCkQ-q-Tf X-Authority-Analysis: v=2.4 cv=aO79aL9m c=1 sm=1 tr=0 ts=692c578c cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=QwukUx79tW4PgYOutgUA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: PZdALkgtZhJC1yFQaPF_96nDCkQ-q-Tf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-28_08,2025-11-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 suspectscore=0 spamscore=0 priorityscore=1501 bulkscore=0 phishscore=0 malwarescore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511300126 From: Unnathi Chalicheemala Currently, only a single waitqueue context exists in the driver. Multi-waitqueue mechanism is added in firmware to support the case, when multiple VMs make SMC calls or single VM making multiple calls on same CPU. Enhance the driver to support multiple waitqueue when support is present in the firmware. When VMs make a SMC call, firmware allocates a waitqueue context, assuming the SMC call to be a blocking call. The SMC calls that cannot acquire resources, while execution in firmware, are returned to sleep in the calling VM. When the resource becomes available in the firmware, the VM gets notified to wake the sleeping thread and resume SMC call. The current qcom_scm driver supports single waitqueue as the old firmwares support only single waitqueue with waitqueue id zero. Multi-waitqueue mechanism is added in firmware starting SM8650 to support the case when multiple VMs make SMC calls or single VM making multiple calls on same CPU. To enable this support in qcom_scm driver, add support for handling multiple waitqueues. For instance, SM8650 firmware can allocate two such waitq contexts, so the driver needs to implement two waitqueue contexts. For a generalized approach, the number of supported waitqueues can be queried from the firmware using a SMC call. Introduce qcom_scm_query_waitq_count to get the number of waitqueue contexts supported by the firmware and allocate =E2=80=9CN=E2=80=9D unique = waitqueue contexts with a dynamic sized array where each unique wq_ctx is associated with a struct completion variable for easy lookup. Older targets which support only a single waitqueue, may return an error for qcom_scm_query_waitq_count, set the wq_cnt to one for such failures. Reviewed-by: Bartosz Golaszewski Signed-off-by: Unnathi Chalicheemala Signed-off-by: Shivendra Pratap --- drivers/firmware/qcom/qcom_scm.c | 74 ++++++++++++++++++++++++++++--------= ---- 1 file changed, 52 insertions(+), 22 deletions(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_= scm.c index 79ab1707f71b0157835deaea6309f33016e3de8c..ef3d81a5340512a79c252430db5= f09cd8c253173 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -47,7 +47,7 @@ struct qcom_scm { struct clk *iface_clk; struct clk *bus_clk; struct icc_path *path; - struct completion waitq_comp; + struct completion *waitq_comps; struct reset_controller_dev reset; =20 /* control access to the interconnect path */ @@ -57,6 +57,7 @@ struct qcom_scm { u64 dload_mode_addr; =20 struct qcom_tzmem_pool *mempool; + unsigned int wq_cnt; }; =20 struct qcom_scm_current_perm_info { @@ -2247,6 +2248,23 @@ static int qcom_scm_fill_irq_fwspec_params(struct ir= q_fwspec *fwspec, u32 hwirq) return 0; } =20 +static int qcom_scm_query_waitq_count(struct qcom_scm *scm) +{ + int ret; + struct qcom_scm_desc desc =3D { + .svc =3D QCOM_SCM_SVC_WAITQ, + .cmd =3D QCOM_SCM_WAITQ_GET_INFO, + .owner =3D ARM_SMCCC_OWNER_SIP + }; + struct qcom_scm_res res; + + ret =3D qcom_scm_call_atomic(scm->dev, &desc, &res); + if (ret) + return ret; + + return res.result[0] & GENMASK(7, 0); +} + static int qcom_scm_get_waitq_irq(struct qcom_scm *scm) { struct device_node *parent_irq_node; @@ -2278,42 +2296,40 @@ static int qcom_scm_get_waitq_irq(struct qcom_scm *= scm) return irq_create_fwspec_mapping(&fwspec); } =20 -static int qcom_scm_assert_valid_wq_ctx(u32 wq_ctx) +static struct completion *qcom_scm_get_completion(u32 wq_ctx) { - /* FW currently only supports a single wq_ctx (zero). - * TODO: Update this logic to include dynamic allocation and lookup of - * completion structs when FW supports more wq_ctx values. - */ - if (wq_ctx !=3D 0) { - dev_err(__scm->dev, "Firmware unexpectedly passed non-zero wq_ctx\n"); - return -EINVAL; - } + struct completion *wq; =20 - return 0; + if (WARN_ON_ONCE(wq_ctx >=3D __scm->wq_cnt)) + return ERR_PTR(-EINVAL); + + wq =3D &__scm->waitq_comps[wq_ctx]; + + return wq; } =20 int qcom_scm_wait_for_wq_completion(u32 wq_ctx) { - int ret; + struct completion *wq; =20 - ret =3D qcom_scm_assert_valid_wq_ctx(wq_ctx); - if (ret) - return ret; + wq =3D qcom_scm_get_completion(wq_ctx); + if (IS_ERR(wq)) + return PTR_ERR(wq); =20 - wait_for_completion(&__scm->waitq_comp); + wait_for_completion(wq); =20 return 0; } =20 static int qcom_scm_waitq_wakeup(unsigned int wq_ctx) { - int ret; + struct completion *wq; =20 - ret =3D qcom_scm_assert_valid_wq_ctx(wq_ctx); - if (ret) - return ret; + wq =3D qcom_scm_get_completion(wq_ctx); + if (IS_ERR(wq)) + return PTR_ERR(wq); =20 - complete(&__scm->waitq_comp); + complete(wq); =20 return 0; } @@ -2389,6 +2405,7 @@ static int qcom_scm_probe(struct platform_device *pde= v) struct qcom_tzmem_pool_config pool_config; struct qcom_scm *scm; int irq, ret; + int i; =20 scm =3D devm_kzalloc(&pdev->dev, sizeof(*scm), GFP_KERNEL); if (!scm) @@ -2399,7 +2416,6 @@ static int qcom_scm_probe(struct platform_device *pde= v) if (ret < 0) return ret; =20 - init_completion(&scm->waitq_comp); mutex_init(&scm->scm_bw_lock); =20 scm->path =3D devm_of_icc_get(&pdev->dev, NULL); @@ -2451,6 +2467,20 @@ static int qcom_scm_probe(struct platform_device *pd= ev) return dev_err_probe(scm->dev, PTR_ERR(scm->mempool), "Failed to create the SCM memory pool\n"); =20 + ret =3D qcom_scm_query_waitq_count(scm); + if (ret < 0) + scm->wq_cnt =3D 1; + else + scm->wq_cnt =3D ret; + + scm->waitq_comps =3D devm_kcalloc(&pdev->dev, scm->wq_cnt, sizeof(*scm->w= aitq_comps), + GFP_KERNEL); + if (!scm->waitq_comps) + return -ENOMEM; + + for (i =3D 0; i < scm->wq_cnt; i++) + init_completion(&scm->waitq_comps[i]); + irq =3D qcom_scm_get_waitq_irq(scm); if (irq < 0) irq =3D platform_get_irq_optional(pdev, 0); --=20 2.34.1