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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2a96560986csm62713689eec.2.2025.11.30.22.30.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Nov 2025 22:30:47 -0800 (PST) From: Hangxiang Ma Date: Sun, 30 Nov 2025 22:30:43 -0800 Subject: [PATCH v8 4/5] media: qcom: camss: csid: Add support for CSID gen4 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251130-add-support-for-camss-on-kaanapali-v8-4-143a8265e6e8@oss.qualcomm.com> References: <20251130-add-support-for-camss-on-kaanapali-v8-0-143a8265e6e8@oss.qualcomm.com> In-Reply-To: <20251130-add-support-for-camss-on-kaanapali-v8-0-143a8265e6e8@oss.qualcomm.com> To: Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Todor Tomov , Vladimir Zapolskiy , Mauro Carvalho Chehab , Bryan O'Donoghue Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, aiqun.yu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com, Jingyi Wang , Atiya Kailany , Hangxiang Ma X-Mailer: b4 0.14.3 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjAxMDA1MSBTYWx0ZWRfX7SVbnKUvgtgQ b9MRs4GYa3JHKfWNO2P/PjW1IjSA4NhSfCCsGHBAY5Yb7h8bI0Ov0wVeYR5QI71SFODaYj+R/3V XAS3GNbdNA+KFFdVVkMKfdKYvHc+bQx/85DrfYsrN6QhfNkZsMTz6prV0wF9Of7bLNNFYKMBSF9 trsfk01lD+NSHRFFNEfMRH6FPpXFxtKVWnS6vxCm77W3KSY3ll2woCxIJpcqrV9u4bb2hCOB3Ke Mp/fCK3S4yv4SJzmse7p/v7EmIhOdrv2l21FboR/NB+Z+oY0DP2uhhzd8HQZTrnPIXd/OQrt2Jc ejCWEqht5rA7t+MPLyUm8dd6ESu/AQBLjSL8LLZW7PkhfoSOZh47D3iyUjmTm2U9FCr5ZmJGWxr u+vmZOt2f9PyRQ0qIYq+u2uBtq4/TQ== X-Proofpoint-ORIG-GUID: cmm8qhrIuOhOAkyIPt-CcMpWw2Ki20Ej X-Authority-Analysis: v=2.4 cv=WONyn3sR c=1 sm=1 tr=0 ts=692d3619 cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=FsTJpaSC_kWcQGXz8SoA:9 a=4Q4zU7iZy6iiv8wZ:21 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-GUID: cmm8qhrIuOhOAkyIPt-CcMpWw2Ki20Ej X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-28_08,2025-11-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 malwarescore=0 clxscore=1015 lowpriorityscore=0 bulkscore=0 suspectscore=0 impostorscore=0 spamscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512010051 Add more detailed resource information for CSID devices along with the driver for CSID gen4 that is responsible for CSID register configuration, module reset and IRQ handling for BUF_DONE events. And aggregate a common definition 'CSI2_RX_CFG0_PHY_SEL_BASE_IDX' into csid header file. In this CSID version, RUP and AUP update values are split into two registers along with a SET register. Accordingly, enhance the CSID interface to accommodate both the legacy combined reg_update and the split RUP and AUP updates. Co-developed-by: Atiya Kailany Signed-off-by: Atiya Kailany Signed-off-by: Hangxiang Ma --- drivers/media/platform/qcom/camss/Makefile | 1 + drivers/media/platform/qcom/camss/camss-csid-680.c | 1 - .../media/platform/qcom/camss/camss-csid-gen3.c | 1 - .../media/platform/qcom/camss/camss-csid-gen4.c | 376 +++++++++++++++++= ++++ drivers/media/platform/qcom/camss/camss-csid.h | 11 +- drivers/media/platform/qcom/camss/camss.c | 80 +++++ 6 files changed, 467 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/pla= tform/qcom/camss/Makefile index 23960d02877d..738d57214056 100644 --- a/drivers/media/platform/qcom/camss/Makefile +++ b/drivers/media/platform/qcom/camss/Makefile @@ -10,6 +10,7 @@ qcom-camss-objs +=3D \ camss-csid-680.o \ camss-csid-gen2.o \ camss-csid-gen3.o \ + camss-csid-gen4.o \ camss-csiphy-2ph-1-0.o \ camss-csiphy-3ph-1-0.o \ camss-csiphy.o \ diff --git a/drivers/media/platform/qcom/camss/camss-csid-680.c b/drivers/m= edia/platform/qcom/camss/camss-csid-680.c index 3ad3a174bcfb..86134a23cd4e 100644 --- a/drivers/media/platform/qcom/camss/camss-csid-680.c +++ b/drivers/media/platform/qcom/camss/camss-csid-680.c @@ -101,7 +101,6 @@ #define CSI2_RX_CFG0_DL2_INPUT_SEL 12 #define CSI2_RX_CFG0_DL3_INPUT_SEL 16 #define CSI2_RX_CFG0_PHY_NUM_SEL 20 -#define CSI2_RX_CFG0_PHY_SEL_BASE_IDX 1 #define CSI2_RX_CFG0_PHY_TYPE_SEL 24 =20 #define CSID_CSI2_RX_CFG1 0x204 diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen3.c b/drivers/= media/platform/qcom/camss/camss-csid-gen3.c index 664245cf6eb0..f09b5575572a 100644 --- a/drivers/media/platform/qcom/camss/camss-csid-gen3.c +++ b/drivers/media/platform/qcom/camss/camss-csid-gen3.c @@ -103,7 +103,6 @@ #define CSID_RDI_IRQ_SUBSAMPLE_PERIOD(rdi) (csid_is_lite(csid) && IS_CSID_= 690(csid) ?\ (0x34C + 0x100 * (rdi)) :\ (0x54C + 0x100 * (rdi))) -#define CSI2_RX_CFG0_PHY_SEL_BASE_IDX 1 =20 static void __csid_configure_rx(struct csid_device *csid, struct csid_phy_config *phy, int vc) diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen4.c b/drivers/= media/platform/qcom/camss/camss-csid-gen4.c new file mode 100644 index 000000000000..b000bd3e9c2e --- /dev/null +++ b/drivers/media/platform/qcom/camss/camss-csid-gen4.c @@ -0,0 +1,376 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * camss-csid-gen4.c + * + * Qualcomm MSM Camera Subsystem - CSID (CSI Decoder) Module + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +#include +#include +#include +#include +#include +#include + +#include "camss.h" +#include "camss-csid.h" +#include "camss-csid-gen3.h" + +/* Reset and Command Registers */ +#define CSID_RST_CFG 0x108 +#define RST_MODE BIT(0) +#define RST_LOCATION BIT(4) + +/* Reset and Command Registers */ +#define CSID_RST_CMD 0x10C +#define SELECT_HW_RST BIT(0) +#define SELECT_IRQ_RST BIT(2) +#define CSID_IRQ_CMD 0x110 +#define IRQ_CMD_CLEAR BIT(0) + +/* Register Update Commands, RUP/AUP */ +#define CSID_RUP_CMD 0x114 +#define CSID_AUP_CMD 0x118 +#define CSID_RUP_AUP_RDI(rdi) (BIT(8) << (rdi)) +#define CSID_RUP_AUP_CMD 0x11C +#define RUP_SET BIT(0) +#define MUP BIT(4) + +/* Top level interrupt registers */ +#define CSID_TOP_IRQ_STATUS 0x180 +#define CSID_TOP_IRQ_MASK 0x184 +#define CSID_TOP_IRQ_CLEAR 0x188 +#define INFO_RST_DONE BIT(0) +#define CSI2_RX_IRQ_STATUS BIT(2) +#define BUF_DONE_IRQ_STATUS BIT(3) + +/* Buffer done interrupt registers */ +#define CSID_BUF_DONE_IRQ_STATUS 0x1A0 +#define BUF_DONE_IRQ_STATUS_RDI_OFFSET 16 +#define CSID_BUF_DONE_IRQ_MASK 0x1A4 +#define CSID_BUF_DONE_IRQ_CLEAR 0x1A8 +#define CSID_BUF_DONE_IRQ_SET 0x1AC + +/* CSI2 RX interrupt registers */ +#define CSID_CSI2_RX_IRQ_STATUS 0x1B0 +#define CSID_CSI2_RX_IRQ_MASK 0x1B4 +#define CSID_CSI2_RX_IRQ_CLEAR 0x1B8 +#define CSID_CSI2_RX_IRQ_SET 0x1BC + +/* CSI2 RX Configuration */ +#define CSID_CSI2_RX_CFG0 0x880 +#define CSI2_RX_CFG0_NUM_ACTIVE_LANES 0 +#define CSI2_RX_CFG0_DL0_INPUT_SEL 4 +#define CSI2_RX_CFG0_PHY_NUM_SEL 20 +#define CSID_CSI2_RX_CFG1 0x884 +#define CSI2_RX_CFG1_ECC_CORRECTION_EN BIT(0) +#define CSI2_RX_CFG1_VC_MODE BIT(2) + +#define MSM_CSID_MAX_SRC_STREAMS_GEN4 (csid_is_lite(csid) ? 4 : 5) + +/* RDI Configuration */ +#define CSID_RDI_CFG0(rdi) \ + ((csid_is_lite(csid) ? 0x3080 : 0x5480) + 0x200 * (rdi)) +#define RDI_CFG0_RETIME_BS BIT(5) +#define RDI_CFG0_TIMESTAMP_EN BIT(6) +#define RDI_CFG0_TIMESTAMP_STB_SEL BIT(8) +#define RDI_CFG0_DECODE_FORMAT 12 +#define RDI_CFG0_DT 16 +#define RDI_CFG0_VC 22 +#define RDI_CFG0_EN BIT(31) + +/* RDI Control and Configuration */ +#define CSID_RDI_CTRL(rdi) \ + ((csid_is_lite(csid) ? 0x3088 : 0x5488) + 0x200 * (rdi)) +#define RDI_CTRL_START_CMD BIT(0) + +#define CSID_RDI_CFG1(rdi) \ + ((csid_is_lite(csid) ? 0x3094 : 0x5494) + 0x200 * (rdi)) +#define RDI_CFG1_DROP_H_EN BIT(5) +#define RDI_CFG1_DROP_V_EN BIT(6) +#define RDI_CFG1_CROP_H_EN BIT(7) +#define RDI_CFG1_CROP_V_EN BIT(8) +#define RDI_CFG1_PACKING_FORMAT_MIPI BIT(15) + +/* RDI Pixel Store Configuration */ +#define CSID_RDI_PIX_STORE_CFG0(rdi) (0x5498 + 0x200 * (rdi)) +#define RDI_PIX_STORE_CFG0_EN BIT(0) +#define RDI_PIX_STORE_CFG0_MIN_HBI 1 + +/* RDI IRQ Status in wrapper */ +#define CSID_CSI2_RDIN_IRQ_STATUS(rdi) (0x224 + (0x10 * (rdi))) +#define CSID_CSI2_RDIN_IRQ_MASK(rdi) (0x228 + (0x10 * (rdi))) +#define CSID_CSI2_RDIN_IRQ_CLEAR(rdi) (0x22C + (0x10 * (rdi))) +#define INFO_RUP_DONE BIT(23) + +static void __csid_aup_rup_trigger(struct csid_device *csid) +{ + /* trigger SET in combined register */ + writel(RUP_SET, csid->base + CSID_RUP_AUP_CMD); +} + +static void __csid_aup_rup_clear(struct csid_device *csid, int port_id) +{ + /* Hardware clears the registers upon consuming the settings */ + csid->aup_update &=3D ~CSID_RUP_AUP_RDI(port_id); + csid->rup_update &=3D ~CSID_RUP_AUP_RDI(port_id); +} + +static void __csid_aup_update(struct csid_device *csid, int port_id) +{ + csid->aup_update |=3D CSID_RUP_AUP_RDI(port_id); + writel(csid->aup_update, csid->base + CSID_AUP_CMD); + + __csid_aup_rup_trigger(csid); +} + +static void __csid_reg_update(struct csid_device *csid, int port_id) +{ + csid->rup_update |=3D CSID_RUP_AUP_RDI(port_id); + writel(csid->rup_update, csid->base + CSID_RUP_CMD); + + __csid_aup_rup_trigger(csid); +} + +static void __csid_configure_rx(struct csid_device *csid, + struct csid_phy_config *phy) +{ + int val; + + val =3D (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES; + val |=3D phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL; + val |=3D (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX) + << CSI2_RX_CFG0_PHY_NUM_SEL; + writel(val, csid->base + CSID_CSI2_RX_CFG0); + + val =3D CSI2_RX_CFG1_ECC_CORRECTION_EN; + writel(val, csid->base + CSID_CSI2_RX_CFG1); +} + +static void __csid_configure_rx_vc(struct csid_device *csid, int vc) +{ + int val; + + if (vc > 3) { + val =3D readl(csid->base + CSID_CSI2_RX_CFG1); + val |=3D CSI2_RX_CFG1_VC_MODE; + writel(val, csid->base + CSID_CSI2_RX_CFG1); + } +} + +static void __csid_ctrl_rdi(struct csid_device *csid, int enable, u8 rdi) +{ + int val =3D 0; + + if (enable) + val =3D RDI_CTRL_START_CMD; + + writel(val, csid->base + CSID_RDI_CTRL(rdi)); +} + +static void __csid_configure_rdi_pix_store(struct csid_device *csid, u8 rd= i) +{ + u32 val; + + /* Configure pixel store to allow absorption of hblanking or idle time. + * This helps with horizontal crop and prevents line buffer conflicts. + * Reset state is 0x8 which has MIN_HBI=3D4, we keep the default MIN_HBI + * and just enable the pixel store functionality. + */ + val =3D (4 << RDI_PIX_STORE_CFG0_MIN_HBI) | RDI_PIX_STORE_CFG0_EN; + writel(val, csid->base + CSID_RDI_PIX_STORE_CFG0(rdi)); +} + +static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enabl= e, u8 vc) +{ + u32 val; + u8 lane_cnt =3D csid->phy.lane_cnt; + + /* Source pads matching RDI channels on hardware. + * E.g. Pad 1 -> RDI0, Pad 2 -> RDI1, etc. + */ + struct v4l2_mbus_framefmt *input_format =3D &csid->fmt[MSM_CSID_PAD_FIRST= _SRC + vc]; + const struct csid_format_info *format =3D csid_get_fmt_entry(csid->res->f= ormats->formats, + csid->res->formats->nformats, + input_format->code); + + if (!lane_cnt) + lane_cnt =3D 4; + + val =3D RDI_CFG0_TIMESTAMP_EN; + val |=3D RDI_CFG0_TIMESTAMP_STB_SEL; + val |=3D RDI_CFG0_RETIME_BS; + + /* note: for non-RDI path, this should be format->decode_format */ + val |=3D DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT; + val |=3D vc << RDI_CFG0_VC; + val |=3D format->data_type << RDI_CFG0_DT; + writel(val, csid->base + CSID_RDI_CFG0(vc)); + + val =3D RDI_CFG1_PACKING_FORMAT_MIPI; + writel(val, csid->base + CSID_RDI_CFG1(vc)); + + /* Configure pixel store using dedicated register in gen4 */ + if (!csid_is_lite(csid)) + __csid_configure_rdi_pix_store(csid, vc); + + val =3D 0; + writel(val, csid->base + CSID_RDI_CTRL(vc)); + + val =3D readl(csid->base + CSID_RDI_CFG0(vc)); + + if (enable) + val |=3D RDI_CFG0_EN; + + writel(val, csid->base + CSID_RDI_CFG0(vc)); +} + +static void csid_configure_stream(struct csid_device *csid, u8 enable) +{ + u8 i; + u8 vc; + + __csid_configure_rx(csid, &csid->phy); + + for (vc =3D 0; vc < MSM_CSID_MAX_SRC_STREAMS_GEN4; vc++) { + if (csid->phy.en_vc & BIT(vc)) { + __csid_configure_rdi_stream(csid, enable, vc); + __csid_configure_rx_vc(csid, vc); + + for (i =3D 0; i < CAMSS_INIT_BUF_COUNT; i++) + __csid_aup_update(csid, vc); + + __csid_reg_update(csid, vc); + + __csid_ctrl_rdi(csid, enable, vc); + } + } +} + +static int csid_configure_testgen_pattern(struct csid_device *csid, s32 va= l) +{ + return 0; +} + +static void csid_subdev_reg_update(struct csid_device *csid, int port_id, + bool clear) +{ + if (clear) + __csid_aup_rup_clear(csid, port_id); + else + __csid_aup_update(csid, port_id); +} + +/** + * csid_isr - CSID module interrupt service routine + * @irq: Interrupt line + * @dev: CSID device + * + * Return IRQ_HANDLED on success + */ +static irqreturn_t csid_isr(int irq, void *dev) +{ + struct csid_device *csid =3D dev; + u32 val, buf_done_val; + u8 reset_done; + int i; + + val =3D readl(csid->base + CSID_TOP_IRQ_STATUS); + writel(val, csid->base + CSID_TOP_IRQ_CLEAR); + + reset_done =3D val & INFO_RST_DONE; + + buf_done_val =3D readl(csid->base + CSID_BUF_DONE_IRQ_STATUS); + writel(buf_done_val, csid->base + CSID_BUF_DONE_IRQ_CLEAR); + + for (i =3D 0; i < MSM_CSID_MAX_SRC_STREAMS_GEN4; i++) { + if (csid->phy.en_vc & BIT(i)) { + val =3D readl(csid->base + CSID_CSI2_RDIN_IRQ_STATUS(i)); + writel(val, csid->base + CSID_CSI2_RDIN_IRQ_CLEAR(i)); + + if (val & INFO_RUP_DONE) + csid_subdev_reg_update(csid, i, true); + + if (buf_done_val & BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i)) + camss_buf_done(csid->camss, csid->id, i); + } + } + + val =3D IRQ_CMD_CLEAR; + writel(val, csid->base + CSID_IRQ_CMD); + + if (reset_done) + complete(&csid->reset_complete); + + return IRQ_HANDLED; +} + +/** + * csid_reset - Trigger reset on CSID module and wait to complete + * @csid: CSID device + * + * Return 0 on success or a negative error code otherwise + */ +static int csid_reset(struct csid_device *csid) +{ + unsigned long time; + u32 val; + int i; + + reinit_completion(&csid->reset_complete); + + val =3D INFO_RST_DONE | BUF_DONE_IRQ_STATUS; + writel(val, csid->base + CSID_TOP_IRQ_CLEAR); + writel(val, csid->base + CSID_TOP_IRQ_MASK); + + val =3D 0; + for (i =3D 0; i < MSM_CSID_MAX_SRC_STREAMS_GEN4; i++) { + if (csid->phy.en_vc & BIT(i)) { + /* + * Only need to clear buf done IRQ status here, + * RUP done IRQ status will be cleared once isr + * strobe generated by CSID_RST_CMD + */ + val |=3D BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i); + } + } + writel(val, csid->base + CSID_BUF_DONE_IRQ_CLEAR); + writel(val, csid->base + CSID_BUF_DONE_IRQ_MASK); + + /* Clear all IRQ status with CLEAR bits set */ + val =3D IRQ_CMD_CLEAR; + writel(val, csid->base + CSID_IRQ_CMD); + + val =3D RST_LOCATION | RST_MODE; + writel(val, csid->base + CSID_RST_CFG); + + val =3D SELECT_HW_RST | SELECT_IRQ_RST; + writel(val, csid->base + CSID_RST_CMD); + + time =3D wait_for_completion_timeout(&csid->reset_complete, + msecs_to_jiffies(CSID_RESET_TIMEOUT_MS)); + + if (!time) { + dev_err(csid->camss->dev, "CSID reset timeout\n"); + return -EIO; + } + + return 0; +} + +static void csid_subdev_init(struct csid_device *csid) +{ + csid->testgen.nmodes =3D CSID_PAYLOAD_MODE_DISABLED; +} + +const struct csid_hw_ops csid_ops_gen4 =3D { + .configure_stream =3D csid_configure_stream, + .configure_testgen_pattern =3D csid_configure_testgen_pattern, + .hw_version =3D csid_hw_version, + .isr =3D csid_isr, + .reset =3D csid_reset, + .src_pad_code =3D csid_src_pad_code, + .subdev_init =3D csid_subdev_init, + .reg_update =3D csid_subdev_reg_update, +}; diff --git a/drivers/media/platform/qcom/camss/camss-csid.h b/drivers/media= /platform/qcom/camss/camss-csid.h index aedc96ed84b2..75a113050eb1 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.h +++ b/drivers/media/platform/qcom/camss/camss-csid.h @@ -27,6 +27,8 @@ /* CSID hardware can demultiplex up to 4 outputs */ #define MSM_CSID_MAX_SRC_STREAMS 4 =20 +/* CSIPHY to hardware PHY selector mapping */ +#define CSI2_RX_CFG0_PHY_SEL_BASE_IDX 1 #define CSID_RESET_TIMEOUT_MS 500 =20 enum csid_testgen_mode { @@ -154,7 +156,13 @@ struct csid_device { void __iomem *base; u32 irq; char irq_name[30]; - u32 reg_update; + union { + u32 reg_update; + struct { + u32 rup_update; + u32 aup_update; + }; + }; struct camss_clock *clock; int nclocks; struct regulator_bulk_data *supplies; @@ -217,6 +225,7 @@ extern const struct csid_hw_ops csid_ops_340; extern const struct csid_hw_ops csid_ops_680; extern const struct csid_hw_ops csid_ops_gen2; extern const struct csid_hw_ops csid_ops_gen3; +extern const struct csid_hw_ops csid_ops_gen4; =20 /* * csid_is_lite - Check if CSID is CSID lite. diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index b12e79e40e97..6e763a79cd0b 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -139,6 +139,84 @@ static const struct camss_subdev_resources csiphy_res_= kaanapali[] =3D { }, }; =20 +static const struct camss_subdev_resources csid_res_kaanapali[] =3D { + /* CSID0 */ + { + .regulators =3D {}, + .clock =3D { "csid", "csid_csiphy_rx" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg =3D { "csid0" }, + .interrupt =3D { "csid0" }, + .csid =3D { + .is_lite =3D false, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .hw_ops =3D &csid_ops_gen4, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID1 */ + { + .regulators =3D {}, + .clock =3D { "csid", "csid_csiphy_rx" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg =3D { "csid1" }, + .interrupt =3D { "csid1" }, + .csid =3D { + .is_lite =3D false, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .hw_ops =3D &csid_ops_gen4, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID2 */ + { + .regulators =3D {}, + .clock =3D { "csid", "csid_csiphy_rx" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg =3D { "csid2" }, + .interrupt =3D { "csid2" }, + .csid =3D { + .is_lite =3D false, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .hw_ops =3D &csid_ops_gen4, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID_LITE0 */ + { + .regulators =3D {}, + .clock =3D { "vfe_lite_csid", "vfe_lite_cphy_rx" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg =3D { "csid_lite0" }, + .interrupt =3D { "csid_lite0" }, + .csid =3D { + .is_lite =3D true, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .hw_ops =3D &csid_ops_gen4, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID_LITE1 */ + { + .regulators =3D {}, + .clock =3D { "vfe_lite_csid", "vfe_lite_cphy_rx" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg =3D { "csid_lite1" }, + .interrupt =3D { "csid_lite1" }, + .csid =3D { + .is_lite =3D true, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .hw_ops =3D &csid_ops_gen4, + .formats =3D &csid_formats_gen2 + } + } +}; + static const struct resources_icc icc_res_kaanapali[] =3D { { .name =3D "ahb", @@ -4414,9 +4492,11 @@ static const struct camss_resources kaanapali_resour= ces =3D { .version =3D CAMSS_KAANAPALI, .pd_name =3D "top", .csiphy_res =3D csiphy_res_kaanapali, + .csid_res =3D csid_res_kaanapali, .icc_res =3D icc_res_kaanapali, .icc_path_num =3D ARRAY_SIZE(icc_res_kaanapali), .csiphy_num =3D ARRAY_SIZE(csiphy_res_kaanapali), + .csid_num =3D ARRAY_SIZE(csid_res_kaanapali), }; =20 static const struct camss_resources msm8916_resources =3D { --=20 2.34.1