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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2a96560986csm62713689eec.2.2025.11.30.22.30.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Nov 2025 22:30:44 -0800 (PST) From: Hangxiang Ma Date: Sun, 30 Nov 2025 22:30:40 -0800 Subject: [PATCH v8 1/5] media: dt-bindings: Add CAMSS device for Kaanapali Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251130-add-support-for-camss-on-kaanapali-v8-1-143a8265e6e8@oss.qualcomm.com> References: <20251130-add-support-for-camss-on-kaanapali-v8-0-143a8265e6e8@oss.qualcomm.com> In-Reply-To: <20251130-add-support-for-camss-on-kaanapali-v8-0-143a8265e6e8@oss.qualcomm.com> To: Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Todor Tomov , Vladimir Zapolskiy , Mauro Carvalho Chehab , Bryan O'Donoghue Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, aiqun.yu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com, Jingyi Wang , Atiya Kailany , Hangxiang Ma , Krzysztof Kozlowski X-Mailer: b4 0.14.3 X-Authority-Analysis: v=2.4 cv=X7Nf6WTe c=1 sm=1 tr=0 ts=692d3616 cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=gEfo2CItAAAA:8 a=KKAkSRfTAAAA:8 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=78032wgmgAfrEkmTq9UA:9 a=QEXdDO2ut3YA:10 a=3WC7DwWrALyhR5TkjVHa:22 a=sptkURWiP4Gy88Gu7hUp:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: -gCs0VSqqW12wFPAGDVNYSGGW3b8sNw9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjAxMDA1MSBTYWx0ZWRfX8wEvjMWq/c+/ DYJge9GbKBTdvITbUp3/Gqt+FMBBMi8hJ9vvHnNixOnvECO/7+0s70aIGgqL+RhV9w/EqKW52Fh IZuowDKwX7fV6nsd4E42ewn1hWO1m6Qxw/MIv+HQtWHIGzCEFAY4QVp3ulGLdxoNMjFrTzKvyf3 bSO1XQnHDHOSLTSLYSzW199cMgOpAku1wORaP/F9C2EsCf0qvWB83ga5opJnHzQPhmIiBkHEHkb e7z2obkwXsCn5+XCQEPq5Vd+Gt3y74HoXBTPnnKXOxoz19yB1sizcS+RgtzYDppnWasLI6VkEGu 7lguw8rXGe/9RNsWLwwMbUxDT4ZPJrpC1UcSmcGo0dcXvhMBIQRrnFx8jLLylM0wwBBFqDbvdFQ 4hcE/UK+GD88M3Yw7RIX0dJ9eqEy1w== X-Proofpoint-ORIG-GUID: -gCs0VSqqW12wFPAGDVNYSGGW3b8sNw9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-28_08,2025-11-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 bulkscore=0 phishscore=0 priorityscore=1501 malwarescore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512010051 Add the compatible string "qcom,kaanapali-camss" to describe the Camera Subsystem (CAMSS) on the Qualcomm Kaanapali platform. The Kaanapali platform provides: - 3 x VFE, 5 RDI per VFE - 2 x VFE Lite, 4 RDI per VFE Lite - 3 x CSID - 2 x CSID Lite - 6 x CSIPHY - 2 x ICP - 1 x IPE - 2 x JPEG DMA & Downscaler - 2 x JPEG Encoder - 1 x OFE - 5 x RT CDM - 3 x TPG Reviewed-by: Bryan O'Donoghue Reviewed-by: Krzysztof Kozlowski Signed-off-by: Hangxiang Ma --- .../bindings/media/qcom,kaanapali-camss.yaml | 647 +++++++++++++++++= ++++ 1 file changed, 647 insertions(+) diff --git a/Documentation/devicetree/bindings/media/qcom,kaanapali-camss.y= aml b/Documentation/devicetree/bindings/media/qcom,kaanapali-camss.yaml new file mode 100644 index 000000000000..094287c01a79 --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,kaanapali-camss.yaml @@ -0,0 +1,647 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,kaanapali-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Kaanapali Camera Subsystem (CAMSS) + +maintainers: + - Hangxiang Ma + +description: + This binding describes the camera subsystem hardware found on Kaanapali + Qualcomm SoCs. It includes submodules such as CSIPHY (CSI Physical layer) + and CSID (CSI Decoder), which comply with the MIPI CSI2 protocol. + + The subsystem also integrates a set of real-time image processing engines + and their associated configuration modules, as well as non-real-time eng= ines. + + Additionally, it encompasses a test pattern generator (TPG) submodule. + +properties: + compatible: + const: qcom,kaanapali-camss + + reg: + items: + - description: Registers for CSID 0 + - description: Registers for CSID 1 + - description: Registers for CSID 2 + - description: Registers for CSID Lite 0 + - description: Registers for CSID Lite 1 + - description: Registers for CSIPHY 0 + - description: Registers for CSIPHY 1 + - description: Registers for CSIPHY 2 + - description: Registers for CSIPHY 3 + - description: Registers for CSIPHY 4 + - description: Registers for CSIPHY 5 + - description: Registers for VFE (Video Front End) 0 + - description: Registers for VFE 1 + - description: Registers for VFE 2 + - description: Registers for VFE Lite 0 + - description: Registers for VFE Lite 1 + - description: Registers for ICP (Imaging Control Processor) 0 + - description: Registers for ICP 0 SYS + - description: Registers for ICP 1 + - description: Registers for ICP 1 SYS + - description: Registers for IPE (Image Processing Engine) + - description: Registers for JPEG DMA & Downscaler + - description: Registers for JPEG Encoder + - description: Registers for OFE (Offline Front End) + - description: Registers for RT CDM (Camera Data Mover) 0 + - description: Registers for RT CDM 1 + - description: Registers for RT CDM 2 + - description: Registers for RT CDM 3 + - description: Registers for RT CDM 4 + - description: Registers for TPG 0 + - description: Registers for TPG 1 + - description: Registers for TPG 2 + + reg-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: csiphy4 + - const: csiphy5 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite0 + - const: vfe_lite1 + - const: icp0 + - const: icp0_sys + - const: icp1 + - const: icp1_sys + - const: ipe + - const: jpeg_dma + - const: jpeg_enc + - const: ofe + - const: rt_cdm0 + - const: rt_cdm1 + - const: rt_cdm2 + - const: rt_cdm3 + - const: rt_cdm4 + - const: tpg0 + - const: tpg1 + - const: tpg2 + + clocks: + maxItems: 60 + + clock-names: + items: + - const: camnoc_nrt_axi + - const: camnoc_rt_axi + - const: camnoc_rt_vfe0 + - const: camnoc_rt_vfe1 + - const: camnoc_rt_vfe2 + - const: camnoc_rt_vfe_lite + - const: cam_top_ahb + - const: cam_top_fast_ahb + - const: csid + - const: csid_csiphy_rx + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy1 + - const: csiphy1_timer + - const: csiphy2 + - const: csiphy2_timer + - const: csiphy3 + - const: csiphy3_timer + - const: csiphy4 + - const: csiphy4_timer + - const: csiphy5 + - const: csiphy5_timer + - const: gcc_hf_axi + - const: vfe0 + - const: vfe0_fast_ahb + - const: vfe1 + - const: vfe1_fast_ahb + - const: vfe2 + - const: vfe2_fast_ahb + - const: vfe_lite + - const: vfe_lite_ahb + - const: vfe_lite_cphy_rx + - const: vfe_lite_csid + - const: qdss_debug_xo + - const: camnoc_ipe_nps + - const: camnoc_ofe + - const: gcc_sf_axi + - const: icp0 + - const: icp0_ahb + - const: icp1 + - const: icp1_ahb + - const: ipe_nps + - const: ipe_nps_ahb + - const: ipe_nps_fast_ahb + - const: ipe_pps + - const: ipe_pps_fast_ahb + - const: jpeg + - const: ofe_ahb + - const: ofe_anchor + - const: ofe_anchor_fast_ahb + - const: ofe_hdr + - const: ofe_hdr_fast_ahb + - const: ofe_main + - const: ofe_main_fast_ahb + - const: vfe0_bayer + - const: vfe0_bayer_fast_ahb + - const: vfe1_bayer + - const: vfe1_bayer_fast_ahb + - const: vfe2_bayer + - const: vfe2_bayer_fast_ahb + + interrupts: + maxItems: 30 + + interrupt-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: csiphy4 + - const: csiphy5 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite0 + - const: vfe_lite1 + - const: camnoc_nrt + - const: camnoc_rt + - const: icp0 + - const: icp1 + - const: jpeg_dma + - const: jpeg_enc + - const: rt_cdm0 + - const: rt_cdm1 + - const: rt_cdm2 + - const: rt_cdm3 + - const: rt_cdm4 + - const: tpg0 + - const: tpg1 + - const: tpg2 + + interconnects: + maxItems: 4 + + interconnect-names: + items: + - const: ahb + - const: hf_mnoc + - const: sf_icp_mnoc + - const: sf_mnoc + + iommus: + items: + - description: VFE non-protected stream + - description: ICP0 shared stream + - description: ICP1 shared stream + - description: IPE CDM non-protected stream + - description: IPE non-protected stream + - description: JPEG non-protected stream + - description: OFE CDM non-protected stream + - description: OFE non-protected stream + - description: VFE / VFE Lite CDM non-protected stream + + power-domains: + items: + - description: + VFE0 GDSC - Global Distributed Switch Controller for VFE0. + - description: + VFE1 GDSC - Global Distributed Switch Controller for VFE1. + - description: + VFE2 GDSC - Global Distributed Switch Controller for VFE2. + - description: + Titan GDSC - Global Distributed Switch Controller for the entire= camss. + - description: + IPE GDSC - Global Distributed Switch Controller for IPE. + - description: + OFE GDSC - Block Global Distributed Switch Controller for OFE. + + power-domain-names: + items: + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: top + - const: ipe + - const: ofe + + vdd-csiphy0-0p8-supply: + description: + Phandle to a 0.8V regulator supply to CSIPHY0 core block. + + vdd-csiphy0-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY0 pll block. + + vdd-csiphy1-0p8-supply: + description: + Phandle to a 0.8V regulator supply to CSIPHY1 core block. + + vdd-csiphy1-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY1 pll block. + + vdd-csiphy2-0p8-supply: + description: + Phandle to a 0.8V regulator supply to CSIPHY2 core block. + + vdd-csiphy2-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY2 pll block. + + vdd-csiphy3-0p8-supply: + description: + Phandle to a 0.8V regulator supply to CSIPHY3 core block. + + vdd-csiphy3-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY3 pll block. + + vdd-csiphy4-0p8-supply: + description: + Phandle to a 0.8V regulator supply to CSIPHY4 core block. + + vdd-csiphy4-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY4 pll block. + + vdd-csiphy5-0p8-supply: + description: + Phandle to a 0.8V regulator supply to CSIPHY5 core block. + + vdd-csiphy5-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY5 pll block. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + +patternProperties: + "^port@[0-5]$": + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input ports for receiving CSI data on CSIPHY 0-5. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - data-lanes + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + - interconnects + - interconnect-names + - iommus + - power-domains + - power-domain-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + isp@9253000 { + compatible =3D "qcom,kaanapali-camss"; + + reg =3D <0x0 0x09253000 0x0 0x5e80>, + <0x0 0x09263000 0x0 0x5e80>, + <0x0 0x09273000 0x0 0x5e80>, + <0x0 0x092d3000 0x0 0x3880>, + <0x0 0x092e7000 0x0 0x3880>, + <0x0 0x09523000 0x0 0x2000>, + <0x0 0x09525000 0x0 0x2000>, + <0x0 0x09527000 0x0 0x2000>, + <0x0 0x09529000 0x0 0x2000>, + <0x0 0x0952b000 0x0 0x2000>, + <0x0 0x0952d000 0x0 0x2000>, + <0x0 0x09151000 0x0 0x20000>, + <0x0 0x09171000 0x0 0x20000>, + <0x0 0x09191000 0x0 0x20000>, + <0x0 0x092dc000 0x0 0x1300>, + <0x0 0x092f0000 0x0 0x1300>, + <0x0 0x0900e000 0x0 0x1000>, + <0x0 0x0900d000 0x0 0x1000>, + <0x0 0x0902e000 0x0 0x1000>, + <0x0 0x0902d000 0x0 0x1000>, + <0x0 0x090d7000 0x0 0x20000>, + <0x0 0x0904e000 0x0 0x1000>, + <0x0 0x0904d000 0x0 0x1000>, + <0x0 0x09057000 0x0 0x40000>, + <0x0 0x09147000 0x0 0x580>, + <0x0 0x09148000 0x0 0x580>, + <0x0 0x09149000 0x0 0x580>, + <0x0 0x0914a000 0x0 0x580>, + <0x0 0x0914b000 0x0 0x580>, + <0x0 0x093fd000 0x0 0x400>, + <0x0 0x093fe000 0x0 0x400>, + <0x0 0x093ff000 0x0 0x400>; + reg-names =3D "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1", + "icp0", + "icp0_sys", + "icp1", + "icp1_sys", + "ipe", + "jpeg_dma", + "jpeg_enc", + "ofe", + "rt_cdm0", + "rt_cdm1", + "rt_cdm2", + "rt_cdm3", + "rt_cdm4", + "tpg0", + "tpg1", + "tpg2"; + + clocks =3D <&camcc_cam_cc_camnoc_nrt_axi_clk>, + <&camcc_cam_cc_camnoc_rt_axi_clk>, + <&camcc_cam_cc_camnoc_rt_vfe_0_main_clk>, + <&camcc_cam_cc_camnoc_rt_vfe_1_main_clk>, + <&camcc_cam_cc_camnoc_rt_vfe_2_main_clk>, + <&camcc_cam_cc_camnoc_rt_vfe_lite_clk>, + <&camcc_cam_cc_cam_top_ahb_clk>, + <&camcc_cam_cc_cam_top_fast_ahb_clk>, + <&camcc_cam_cc_csid_clk>, + <&camcc_cam_cc_csid_csiphy_rx_clk>, + <&camcc_cam_cc_csiphy0_clk>, + <&camcc_cam_cc_csi0phytimer_clk>, + <&camcc_cam_cc_csiphy1_clk>, + <&camcc_cam_cc_csi1phytimer_clk>, + <&camcc_cam_cc_csiphy2_clk>, + <&camcc_cam_cc_csi2phytimer_clk>, + <&camcc_cam_cc_csiphy3_clk>, + <&camcc_cam_cc_csi3phytimer_clk>, + <&camcc_cam_cc_csiphy4_clk>, + <&camcc_cam_cc_csi4phytimer_clk>, + <&camcc_cam_cc_csiphy5_clk>, + <&camcc_cam_cc_csi5phytimer_clk>, + <&gcc_gcc_camera_hf_axi_clk>, + <&camcc_cam_cc_vfe_0_main_clk>, + <&camcc_cam_cc_vfe_0_main_fast_ahb_clk>, + <&camcc_cam_cc_vfe_1_main_clk>, + <&camcc_cam_cc_vfe_1_main_fast_ahb_clk>, + <&camcc_cam_cc_vfe_2_main_clk>, + <&camcc_cam_cc_vfe_2_main_fast_ahb_clk>, + <&camcc_cam_cc_vfe_lite_clk>, + <&camcc_cam_cc_vfe_lite_ahb_clk>, + <&camcc_cam_cc_vfe_lite_cphy_rx_clk>, + <&camcc_cam_cc_vfe_lite_csid_clk>, + <&camcc_cam_cc_qdss_debug_xo_clk>, + <&camcc_cam_cc_camnoc_nrt_ipe_nps_clk>, + <&camcc_cam_cc_camnoc_nrt_ofe_main_clk>, + <&gcc_gcc_camera_sf_axi_clk>, + <&camcc_cam_cc_icp_0_clk>, + <&camcc_cam_cc_icp_0_ahb_clk>, + <&camcc_cam_cc_icp_1_clk>, + <&camcc_cam_cc_icp_1_ahb_clk>, + <&camcc_cam_cc_ipe_nps_clk>, + <&camcc_cam_cc_ipe_nps_ahb_clk>, + <&camcc_cam_cc_ipe_nps_fast_ahb_clk>, + <&camcc_cam_cc_ipe_pps_clk>, + <&camcc_cam_cc_ipe_pps_fast_ahb_clk>, + <&camcc_cam_cc_jpeg_clk>, + <&camcc_cam_cc_ofe_ahb_clk>, + <&camcc_cam_cc_ofe_anchor_clk>, + <&camcc_cam_cc_ofe_anchor_fast_ahb_clk>, + <&camcc_cam_cc_ofe_hdr_clk>, + <&camcc_cam_cc_ofe_hdr_fast_ahb_clk>, + <&camcc_cam_cc_ofe_main_clk>, + <&camcc_cam_cc_ofe_main_fast_ahb_clk>, + <&camcc_cam_cc_vfe_0_bayer_clk>, + <&camcc_cam_cc_vfe_0_bayer_fast_ahb_clk>, + <&camcc_cam_cc_vfe_1_bayer_clk>, + <&camcc_cam_cc_vfe_1_bayer_fast_ahb_clk>, + <&camcc_cam_cc_vfe_2_bayer_clk>, + <&camcc_cam_cc_vfe_2_bayer_fast_ahb_clk>; + clock-names =3D "camnoc_nrt_axi", + "camnoc_rt_axi", + "camnoc_rt_vfe0", + "camnoc_rt_vfe1", + "camnoc_rt_vfe2", + "camnoc_rt_vfe_lite", + "cam_top_ahb", + "cam_top_fast_ahb", + "csid", + "csid_csiphy_rx", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "csiphy4", + "csiphy4_timer", + "csiphy5", + "csiphy5_timer", + "gcc_hf_axi", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe2", + "vfe2_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid", + "qdss_debug_xo", + "camnoc_ipe_nps", + "camnoc_ofe", + "gcc_sf_axi", + "icp0", + "icp0_ahb", + "icp1", + "icp1_ahb", + "ipe_nps", + "ipe_nps_ahb", + "ipe_nps_fast_ahb", + "ipe_pps", + "ipe_pps_fast_ahb", + "jpeg", + "ofe_ahb", + "ofe_anchor", + "ofe_anchor_fast_ahb", + "ofe_hdr", + "ofe_hdr_fast_ahb", + "ofe_main", + "ofe_main_fast_ahb", + "vfe0_bayer", + "vfe0_bayer_fast_ahb", + "vfe1_bayer", + "vfe1_bayer_fast_ahb", + "vfe2_bayer", + "vfe2_bayer_fast_ahb"; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1", + "camnoc_nrt", + "camnoc_rt", + "icp0", + "icp1", + "jpeg_dma", + "jpeg_enc", + "rt_cdm0", + "rt_cdm1", + "rt_cdm2", + "rt_cdm3", + "rt_cdm4", + "tpg0", + "tpg1", + "tpg2"; + + interconnects =3D <&gem_noc_master_appss_proc QCOM_ICC_TAG_ACT= IVE_ONLY + &config_noc_slave_camera_cfg QCOM_ICC_TAG_ACT= IVE_ONLY>, + <&mmss_noc_master_camnoc_hf QCOM_ICC_TAG_ALWAYS + &mc_virt_slave_ebi1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc_master_camnoc_sf_icp QCOM_ICC_TAG_A= LWAYS + &mc_virt_slave_ebi1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc_master_camnoc_sf QCOM_ICC_TAG_ALWAYS + &mc_virt_slave_ebi1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "ahb", + "hf_mnoc", + "sf_icp_mnoc", + "sf_mnoc"; + + iommus =3D <&apps_smmu 0x1c00 0x00>, + <&apps_smmu 0x18c0 0x00>, + <&apps_smmu 0x1980 0x00>, + <&apps_smmu 0x1840 0x00>, + <&apps_smmu 0x1800 0x00>, + <&apps_smmu 0x18a0 0x00>, + <&apps_smmu 0x1880 0x00>, + <&apps_smmu 0x1820 0x00>, + <&apps_smmu 0x1860 0x00>; + + power-domains =3D <&camcc_cam_cc_vfe_0_gdsc>, + <&camcc_cam_cc_vfe_1_gdsc>, + <&camcc_cam_cc_vfe_2_gdsc>, + <&camcc_cam_cc_titan_top_gdsc>, + <&camcc_cam_cc_ipe_gdsc>, + <&camcc_cam_cc_ofe_gdsc>; + power-domain-names =3D "vfe0", + "vfe1", + "vfe2", + "top", + "ipe", + "ofe"; + + vdd-csiphy0-0p8-supply =3D <&vreg_0p8_supply>; + vdd-csiphy0-1p2-supply =3D <&vreg_1p2_supply>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + csiphy_ep0: endpoint { + data-lanes =3D <0 1>; + remote-endpoint =3D <&sensor_ep>; + }; + }; + }; + }; + }; --=20 2.34.1