From nobody Mon Dec 1 22:38:28 2025 Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C9DBC25392C for ; Sat, 29 Nov 2025 18:52:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764442331; cv=none; b=OR9U8n0s2XJGcHUBDVG9htYzA3WRoNe0knvskVLC+xMFV/mgDhHdElFTC07ps+3ca0/gWIoM0kFMYQJHoCF5qO76AU3qU33rzJKiDV7Mxbw0zD912NJRskCdVCupDgcMd0QTscNmf4L6MZrahmikbfIfYzU7P5SEh7IKYZNn+Ik= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764442331; c=relaxed/simple; bh=eGV43zXNZwLcVcE6qLhrYD3w4h0RrIYzFcW/RThrSwE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Sb+ZkQCXo2dYn+rmMnUMzDU155tWmPIN8pzPScuMNzNJ/c8fhHMN5QDmHz54y3QLU2GzYNV4hklLfqfK/tKm6Bf83hWQcQjU64iJRvXPjGMwNKXYYrU+bEja2cU4nuygqTO4fxb/itpyj+8WnwLZqdkw5d4j/tS4gQFzZKnrp/M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=np6Ld+VP; arc=none smtp.client-ip=209.85.221.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="np6Ld+VP" Received: by mail-wr1-f44.google.com with SMTP id ffacd0b85a97d-42b3669ca3dso1217143f8f.0 for ; Sat, 29 Nov 2025 10:52:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1764442328; x=1765047128; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2K73nwpTtZLJt98+4WIYLIupevL2M6bireyDzJbZ3Ug=; b=np6Ld+VPGSUpkMUnizuVtgOCVT3MAROiRBnaxqa3LU6zu9JGcVIdetPwmLkKQYDOMF SG8X+i/PPhSOYH2iqR88y+2E64VulkNws+p5Y9w9fcqd+DwIl+VUrKs8HJZtOCO77q2h JzldL3DtyA2OxybAwAuKNbJJx4TKzKsScw2V+eXKRPTrUhDFQ0aj0pGzHXlcZh160NAj 2b89ARv1M69Uy6K8hziYenN4uzlb3/rFJZExI1r2xMDdujy89Uda9YfiZ7D7KvLl/8i2 qY5UanIa71PDf+6B5tCpYfwoDzaRPO9qlJLM7AeNnN7Squ1ZAxxDDRvzgyVm3HgZTQu3 Dmfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764442328; x=1765047128; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=2K73nwpTtZLJt98+4WIYLIupevL2M6bireyDzJbZ3Ug=; b=rw11VfAqAQYLckLKW4DhxLu5WvxQ7H1aeU1vPMKjUaJS5KGWD+Je5hH+d2wdysoS/H 41uGhujLdjvzOG0uusFYVxNxbBTRiRUrBVZbCw9m0nlBRPH7FA6Z9R7GGipJO9mnu8QF inEPBzRbxd+6Gta/tUZZVzwmSLaYI2skSHaxY3N9l4jmp5ryB0azQ8SWqRYgk2VOzOj5 q5qiNQ/oFlLqdoCcmrx/tBu/gdiqH+NEJ1TqS2S8Eq8UqtyJ95LWSKyQo4P/EOYWHM/g cpb/vphAVgXX65GoiUC0Yf8pQODjjeR6E1OEB0sHAS2bG1zcDt77ilUB9+CIeq1SX0Gi 76oQ== X-Forwarded-Encrypted: i=1; AJvYcCWeDsXVm9dMoq1P9Kpiz/LHR8Z0vLGrEWT35aTzinbL6l+fbPPIwIIMH9V5JYmRV+vNAllRD4mrzZSuvvU=@vger.kernel.org X-Gm-Message-State: AOJu0Yw0YT0NkFVm5uCEu7hkZmzj0NKAgTTvLfpLSUslw009dlTq4V4e Iiq43XQTBnTnh9oCOK7pgRVkdozXkhscIyHKIcVawmNXD60CheyRCccd X-Gm-Gg: ASbGnct92cc7hnphMVSSj2QhqqC4R73TmMokWdpyREFEKhevjJWpUVOUonjHqikBHYb F5ZZIOWCn7QknY9HAFYoP/S4KZDFeZ9njkDzZowyr2T/CjLa12TlwiJX2qjtrTds1VqWKZmdj4Y /usiTL6y6kVxjDcWT1soobzKmgL6o/Prl0ByyB4Msexn7mj+vRPy8TEFYTTCxLOSh+PYT6cu8eg aR62s1Y199WMNbVFChhUrRBd+ENpz1kbY0bXzBhatAsBQBsvGma0wNsINb6lc9XI8Lt413urlzV /a2frva9DmsRA5lS8vmXz6Gvu1qvR1MyNpRtTTPCGyd6XKsbIptOsnwIlWI+d67ZXYd5CuQVnkI F/OWD8eZERmUVe/3PxTCmQkZ0w/B8qHAegLjoz2FlAl/+qmEjodCKCq6LbibRfdX98PpXIVNnFo ekDTnknjITYunA3ggw8dBeJ0MFzmfAi7Ch9x+5GHq3EKwdAVuhc3l39zlbRf6H/01zmCAiZTEaN 6EHAPU1dUyvJlxE X-Google-Smtp-Source: AGHT+IFSSRU9nZJg5slEDozvAjxyejJ7ZTFz1HkUkQ1jF7r+FT16cfOI8lRbu19eL7jLdf5EECfspg== X-Received: by 2002:a5d:604b:0:b0:42b:43cc:982e with SMTP id ffacd0b85a97d-42cc1d0cf55mr27087914f8f.36.1764442327972; Sat, 29 Nov 2025 10:52:07 -0800 (PST) Received: from localhost.localdomain (host86-162-200-138.range86-162.btcentralplus.com. [86.162.200.138]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42e1c5d613esm17442067f8f.11.2025.11.29.10.52.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 Nov 2025 10:52:07 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 3/4] arm64: dts: renesas: r9a09g047e57-smarc: Enable rsci{2,4,9} nodes Date: Sat, 29 Nov 2025 18:51:58 +0000 Message-ID: <20251129185203.380002-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251129185203.380002-1-biju.das.jz@bp.renesas.com> References: <20251129185203.380002-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Enable device rsci{2,4,9} nodes for the RZ/G3E SMARC EVK. Signed-off-by: Biju Das --- v1->v2: * Rearranged pincrl entries order by port number. * Updated the comments to reflect the board signals. * Added missing pins CTS4N and RTS4N. * rsci2 is guarded by macros SW_SER2_EN and SW_SER0_PMOD. * rsci4 is guarded by macros SW_LCD_EN and SW_SER0_PMOD. * rsci9 is guarded by macro SW_LCD_EN. * Added uart-has-rtscts to rsci4. * Dropped rsci{2,4,9} nodes from renesas-smarc2.dtsi as RZ/G3S does not have RSCI interfaces. --- .../boot/dts/renesas/r9a09g047e57-smarc.dts | 58 +++++++++++++++++++ .../boot/dts/renesas/renesas-smarc2.dtsi | 7 +++ .../boot/dts/renesas/rzg3e-smarc-som.dtsi | 4 ++ 3 files changed, 69 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm6= 4/boot/dts/renesas/r9a09g047e57-smarc.dts index 50e075745474..696903dc7a63 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts @@ -12,6 +12,8 @@ #define SW_GPIO9_CAN1_STB 0 #define SW_LCD_EN 0 #define SW_PDM_EN 0 +#define SW_SER0_PMOD 1 +#define SW_SER2_EN 1 #define SW_SD0_DEV_SEL 0 #define SW_SDIO_M2E 0 =20 @@ -37,6 +39,9 @@ / { =20 aliases { i2c0 =3D &i2c0; + serial0 =3D &rsci4; + serial1 =3D &rsci9; + serial2 =3D &rsci2; serial3 =3D &scif0; mmc1 =3D &sdhi1; }; @@ -140,6 +145,28 @@ nmi_pins: nmi { input-schmitt-enable; }; =20 + rsci2_pins: rsci2 { + pinmux =3D , /* RXD2 */ + , /* TXD2 */ + , /* CTS2N */ + ; /* RTS2N */ + bias-pull-up; + }; + + rsci4_pins: rsci4 { + pinmux =3D , /* RXD4 */ + , /* TXD4 */ + , /* CTS4N */ + ; /* RTS4N */ + bias-pull-up; + }; + + rsci9_pins: rsci9 { + pinmux =3D , /* RXD9 */ + ; /* TXD9 */ + bias-pull-up; + }; + scif_pins: scif { pins =3D "SCIF_TXD", "SCIF_RXD"; renesas,output-impedance =3D <1>; @@ -176,6 +203,37 @@ usb3_pins: usb3 { }; }; =20 +#if SW_SER0_PMOD && SW_SER2_EN +&rsci2 { + pinctrl-0 =3D <&rsci2_pins>; + pinctrl-names =3D "default"; + + uart-has-rtscts; + + status =3D "okay"; +}; +#endif + +#if (!SW_LCD_EN) && (SW_SER0_PMOD) +&rsci4 { + pinctrl-0 =3D <&rsci4_pins>; + pinctrl-names =3D "default"; + + uart-has-rtscts; + + status =3D "okay"; +}; +#endif + +#if (!SW_LCD_EN) +&rsci9 { + pinctrl-0 =3D <&rsci9_pins>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; +#endif + &scif0 { pinctrl-0 =3D <&scif_pins>; pinctrl-names =3D "default"; diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi b/arch/arm64/b= oot/dts/renesas/renesas-smarc2.dtsi index a6e8eb730096..b607b5d6c259 100644 --- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi +++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi @@ -13,6 +13,13 @@ * 0 - SMARC SDIO signal is connected to uSD1 * 1 - SMARC SDIO signal is connected to M.2 Key E connector * + * Please set the switch position SW_OPT_MUX.4 on the carrier board and the + * corresponding macro SW_SER0_PMOD on the board DTS: + * + * SW_SER0_PMOD: + * 0 - SER0 signals connect to M.2 Key-E, SER2 signals are unconnected + * 1 - SER0 signals connect to PMOD, SER2 signals connect to M.2 Key-E + * * Please set the switch position SW_GPIO_CAN_PMOD on the carrier board an= d the * corresponding macro SW_GPIO8_CAN0_STB/SW_GPIO8_CAN0_STB on the board DT= S: * diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/= boot/dts/renesas/rzg3e-smarc-som.dtsi index 7faa44510d98..eb0de21d6716 100644 --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi @@ -13,6 +13,10 @@ * 0 - SD0 is connected to eMMC (default) * 1 - SD0 is connected to uSD0 card * + * Switch position SYS.4, Macro SW_SER2_EN: + * 0 - Select Module DSI connector(GPIO) + * 1 - Select SER2 + * * Switch position SYS.5, Macro SW_LCD_EN: * 0 - Select Misc. Signals routing * 1 - Select LCD --=20 2.43.0