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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42e1ca4078csm15970060f8f.29.2025.11.29.08.43.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 Nov 2025 08:43:29 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Wolfram Sang , Lad Prabhakar , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das Subject: [PATCH v5 01/17] dt-bindings: serial: renesas,rsci: Document RZ/G3E support Date: Sat, 29 Nov 2025 16:42:57 +0000 Message-ID: <20251129164325.209213-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251129164325.209213-1-biju.das.jz@bp.renesas.com> References: <20251129164325.209213-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add documentation for the serial communication interface (RSCI) found on the Renesas RZ/G3E (R9A09G047) SoC. The RSCI IP on this SoC is identical to that on the RZ/T2H (R9A09G077) SoC, but it has a 32-stage FIFO compared to 16 on RZ/T2H. It supports both FIFO and non-FIFO mode operation. RZ/G3E has 6 clocks(5 module clocks + 1 external clock) compared to 3 clocks (2 module clocks + 1 external clock) on RZ/T2H, and it has multiple resets. It has 6 interrupts compared to 4 on RZ/T2H. Signed-off-by: Biju Das --- v4->v5: * Updated commit description related to IRQ difference * Added aed and bfd irqs for RZ/G3E. * Moved reset: false to RZ/T2H SoC and dropped the else part for RZ/G3E. * Updated conditional schema with interrupts and interrupts-names. * Dropped the tag as there are new changes. v3->v4: * Dropped separate compatible for non-FIFO mode and instead using single compatible "renesas,r9a09g047-rsci" as non-FIFO mode can be achieved by software configuration. * Renamed clock-names bus->pclk * Rearranged clock-names tclk{4, 16, 64} * Retained the tag as the changes are trivial. v2->v3: * Dropped 1st and 3rd items from clk-names and added minItems for the range. * Added minItems for clk and clk-names for RZ/T2H as the range is 2-3 * Added maxItems for clk and clk-names for RZ/G3E as the range is 5-6 * Retained the tag as it is trivial change. v1->v2: * Updated commit message * Added resets:false for non RZ/G3E SoCs. --- .../bindings/serial/renesas,rsci.yaml | 99 ++++++++++++++++--- 1 file changed, 88 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml b/D= ocumentation/devicetree/bindings/serial/renesas,rsci.yaml index 6b1f827a335b..1f8cee8171de 100644 --- a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml @@ -10,46 +10,72 @@ maintainers: - Geert Uytterhoeven - Lad Prabhakar =20 -allOf: - - $ref: serial.yaml# - properties: compatible: oneOf: - - items: - - const: renesas,r9a09g087-rsci # RZ/N2H - - const: renesas,r9a09g077-rsci # RZ/T2H + - enum: + - renesas,r9a09g047-rsci # RZ/G3E + - renesas,r9a09g077-rsci # RZ/T2H =20 - items: + - const: renesas,r9a09g087-rsci # RZ/N2H - const: renesas,r9a09g077-rsci # RZ/T2H =20 reg: maxItems: 1 =20 interrupts: + minItems: 4 items: - description: Error interrupt - description: Receive buffer full interrupt - description: Transmit buffer empty interrupt - description: Transmit end interrupt + - description: Active edge detection interrupt + - description: Break field detection interrupt =20 interrupt-names: + minItems: 4 items: - const: eri - const: rxi - const: txi - const: tei + - const: aed + - const: bfd =20 clocks: minItems: 2 - maxItems: 3 + maxItems: 6 =20 clock-names: - minItems: 2 + oneOf: + - items: + - const: operation + - const: bus + - const: sck # optional external clock input + + minItems: 2 + + - items: + - const: pclk + - const: tclk + - const: tclk_div4 + - const: tclk_div16 + - const: tclk_div64 + - const: sck # optional external clock input + + minItems: 5 + + resets: items: - - const: operation - - const: bus - - const: sck # optional external clock input + - description: Input for resetting the APB clock + - description: Input for resetting TCLK + + reset-names: + items: + - const: presetn + - const: tresetn =20 power-domains: maxItems: 1 @@ -62,6 +88,57 @@ required: - clock-names - power-domains =20 +allOf: + - $ref: serial.yaml# + + - if: + properties: + compatible: + contains: + const: renesas,r9a09g077-rsci + then: + properties: + interrupts: + maxItems: 4 + + interrupt-names: + maxItems: 4 + + clocks: + minItems: 2 + maxItems: 3 + + clock-names: + minItems: 2 + maxItems: 3 + + resets: false + + - if: + properties: + compatible: + contains: + const: renesas,r9a09g047-rsci + then: + properties: + interrupts: + minItems: 6 + + interrupt-names: + minItems: 6 + + clocks: + minItems: 5 + maxItems: 6 + + clock-names: + minItems: 5 + maxItems: 6 + + required: + - resets + - reset-names + unevaluatedProperties: false =20 examples: --=20 2.43.0 From nobody Mon Dec 1 22:07:24 2025 Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E522B30F538 for ; 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42e1ca4078csm15970060f8f.29.2025.11.29.08.43.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 Nov 2025 08:43:29 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Wolfram Sang , Lad Prabhakar , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das Subject: [PATCH v5 02/17] serial: sh-sci: Update rx_trigger size for RZ/T2H RSCI Date: Sat, 29 Nov 2025 16:42:58 +0000 Message-ID: <20251129164325.209213-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251129164325.209213-1-biju.das.jz@bp.renesas.com> References: <20251129164325.209213-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The RZ/T2H RSCI has 16-stage FIFO. Like other SoCs, set the default rx_trigger as the fifosize. Signed-off-by: Biju Das --- v4->v5: * Updated commit description. v4: * New patch. --- drivers/tty/serial/sh-sci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index 53edbf1d8963..28d665a9861a 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -3330,7 +3330,7 @@ static int sci_init_single(struct platform_device *de= v, sci_port->rx_trigger =3D 8; break; case SCI_PORT_RSCI: - sci_port->rx_trigger =3D 15; + sci_port->rx_trigger =3D 16; break; default: sci_port->rx_trigger =3D 1; --=20 2.43.0 From nobody Mon Dec 1 22:07:24 2025 Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6867330F80A for ; Sat, 29 Nov 2025 16:43:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764434614; cv=none; b=AyUF38fO/oRkqaisJvWIu7cxevBvG/sVvSbSzWj5lYl1l14DLaYBTc7Pk93lG5JqiKzTbaHWrt8Ry/BHIp1ZRliCzOIjhJszUIIi26Fe8M77flP5mw8YGpVcYlxSL5Wwgp+MEFPt6q9FV9bTErBbK9oYM2xLnzk/615ZMsvEqC0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764434614; c=relaxed/simple; bh=7Gt1YgAJEEGKJpT8m2zJjrNGSESqnzyY5pcLamcAVl8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=E3qnBlhCunc/2bcZP6G9AvhO6Gx2p/wZpKenjQYTTysdcT61C5JzRJyLE0Xx9CzaNkdTbp83VmmqmMqvTmXiHueawaED2KZ0EmmLCpZsTlM1F1z+qPgTXtLV4jsORj6RAsnAaoIaVKTJllhbGREdcM0cCLkiv9HiNLeC2LL3V3g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=dNsTJgl2; arc=none smtp.client-ip=209.85.221.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="dNsTJgl2" Received: by mail-wr1-f45.google.com with SMTP id ffacd0b85a97d-42e2d5e119fso60156f8f.2 for ; Sat, 29 Nov 2025 08:43:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1764434611; x=1765039411; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=C0GL9llKMJnY7Y99yoS1OtzGt53dvO/rcRpUYrh4ZOU=; b=dNsTJgl2gQcLyP2NMhqyEPOUB4/8Xj0OPLHMzeig5M9x6xzHFagHM/P7e5EIVeaWfs uQr6KaYSNdshiTGSeccOxTPGer8jc3IUbJly6UIKNE9DY7NwxYNQS1whXBHQjtYmFxN/ FtTxrlLPUs0XI5XymM5ZoQqtC99I6kYKRV5opb3vS2rHOKGd+ADbLvT7q1FX2VaL2Ndw 9ar+0IIZt0whfz/+Mr0SMV6QlvqIT7+0ZPUYWR4xiYrKv/eyDE950GWDxu9jwc2OGeRn kKo2iKY2SIhngtQB2MFGURlbBHxdas5EZJvMPnPrwqbYEP96CflgtfBhsTfMiBBYcKMs 1SJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764434611; x=1765039411; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=C0GL9llKMJnY7Y99yoS1OtzGt53dvO/rcRpUYrh4ZOU=; b=gtadCcHhfPQkVHuzUowJjVkj5v0OIkTaB8RigosK2EsdB27nVWl6T5juXUo+kziZVe 4FvFMLauWH5q/tk4jeexCg7Do1lEtuJLyxcjiUl4fNJFxVt6Esbi8ZOW7O8+JE9U3d7R aKNaZAKp3KfcmFQadMX8iT7B0LiIwzXNYhJTVHJk+MIhSXP2PMhbOQaDF1v9hQeFGelT CJHJzDJ/zqGA2zyK/+I+iWSWOgvlZQbrPZdxueoczVGpW/dUbevjzNtSyZQsspdWFwf8 c+2uFL+tx7PSiRgpyLQ+dCxbWU1+5RW22fLGGIMcTiEzqOvJITxbEv8EvGMd1jLApd1i M4mA== X-Forwarded-Encrypted: i=1; AJvYcCWWQCX6AajkGBuZZ7A1IMe2w5mSSN09bxzIA5kBco5ZYWB9++vdQ2eB4UeYAIc+1T9m2ZHvZ1XdyNNVF/4=@vger.kernel.org X-Gm-Message-State: AOJu0YwSnBFKZQOi4HZ3heRPDB1AJP+u7I1Mfso9Kh4OhfATD659p7wz SSSSp4vi6JGMli8jTXqBGY43GJ7+8vahlqOBDVVtLWgCXaCrilm4BdLe X-Gm-Gg: ASbGncsmwh6fIndbr2aaY5A3X7FJ6hBTr+ZFzFZtHY2Y93iKWkPwRZUn32NCB2WaboQ z8KFofp4RcA3y7pMlwvrUiexWWtP/6GYWtHjABXWa1nv2EKMq+2pHESJ+Xzl17McfErlXmEe6tg 5PdtNxclSEh3uM8TEJO0fQiwkobSEnuCO6TiG6HG/B33ZRKAxV4y7lG4dl0mgY98zG+qzRz6iI2 pxL4zDkq+sOhLJjtFG/pxBq+V/4cipwdADpK19ac3uPdCl2dldn1BFGHkZ9xL5T1S4Vqpz1hn9s zoW6yXYX2dJs6JcfkO97UGPsCnmV6zFu0ppWsHcKSB2bc985aFhXCO7CobzjWtFDM+E3cul8xCz s99+HdZ4083yhRCrPwF26hQpVHb5nK2OE6c6WrKCUpbXXQLruL3aVlCYhP4j98xpOq/KTkjx32G xdGTmAJ56TaFZj/z39THTvdOcykLqih6eeKgSK1qDSHf7YbJbGmAipzNAhe2zHHiqvOWKCASKzz JIE54TBXHDkfqO+ X-Google-Smtp-Source: AGHT+IGFqwL4XFsyw/yn7ECVh094qGGx5ZT2W+oo9SwUYcceC9Ev9EXxvf1Vzo7j4HTu73o/KVJ4vw== X-Received: by 2002:a5d:5d86:0:b0:3ea:80ec:8552 with SMTP id ffacd0b85a97d-42cc1d196b5mr34934825f8f.57.1764434610612; Sat, 29 Nov 2025 08:43:30 -0800 (PST) Received: from localhost.localdomain (host86-162-200-138.range86-162.btcentralplus.com. [86.162.200.138]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42e1ca4078csm15970060f8f.29.2025.11.29.08.43.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 Nov 2025 08:43:30 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Wolfram Sang , Lad Prabhakar , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das Subject: [PATCH v5 03/17] serial: rsci: Add set_rtrg() callback Date: Sat, 29 Nov 2025 16:42:59 +0000 Message-ID: <20251129164325.209213-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251129164325.209213-1-biju.das.jz@bp.renesas.com> References: <20251129164325.209213-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The rtrg variable is populated in sci_init_single() for RZ/T2H. Add set_rtrg() callback for setting the rtrg value. Signed-off-by: Biju Das --- v5: * New patch. --- drivers/tty/serial/rsci.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/tty/serial/rsci.c b/drivers/tty/serial/rsci.c index b3c48dc1e07d..0533a4bb1d03 100644 --- a/drivers/tty/serial/rsci.c +++ b/drivers/tty/serial/rsci.c @@ -151,6 +151,22 @@ static void rsci_start_rx(struct uart_port *port) rsci_serial_out(port, CCR0, ctrl); } =20 +static int rsci_scif_set_rtrg(struct uart_port *port, int rx_trig) +{ + u32 fcr =3D rsci_serial_in(port, FCR); + + if (rx_trig >=3D port->fifosize) + rx_trig =3D port->fifosize - 1; + else if (rx_trig < 1) + rx_trig =3D 0; + + fcr &=3D ~FCR_RTRG4_0; + fcr |=3D field_prep(FCR_RTRG4_0, rx_trig); + rsci_serial_out(port, FCR, fcr); + + return rx_trig; +} + static void rsci_set_termios(struct uart_port *port, struct ktermios *term= ios, const struct ktermios *old) { @@ -454,6 +470,7 @@ static const struct sci_port_ops rsci_port_ops =3D { .poll_put_char =3D rsci_poll_put_char, .prepare_console_write =3D rsci_prepare_console_write, .suspend_regs_size =3D rsci_suspend_regs_size, + .set_rtrg =3D rsci_scif_set_rtrg, .shutdown_complete =3D rsci_shutdown_complete, }; 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42e1ca4078csm15970060f8f.29.2025.11.29.08.43.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 Nov 2025 08:43:30 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Wolfram Sang , Lad Prabhakar , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das Subject: [PATCH v5 04/17] serial: sh-sci: Drop checking port type for device file{create, remove} Date: Sat, 29 Nov 2025 16:43:00 +0000 Message-ID: <20251129164325.209213-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251129164325.209213-1-biju.das.jz@bp.renesas.com> References: <20251129164325.209213-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Ports that support FIFO has fifosize > 1. Replace checking the port type with fifosize for device file{create, remove}. Signed-off-by: Biju Das --- v4->v5: * Dropped checking port type for device file{create, remove} and instead started checking the fifosize. * Dropped sci_is_fifo_type() helper. * Updated commit header and description. v4: * New patch. --- drivers/tty/serial/sh-sci.c | 15 ++++----------- 1 file changed, 4 insertions(+), 11 deletions(-) diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index 28d665a9861a..ff5459c449fb 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -3549,16 +3549,14 @@ static struct uart_driver sci_uart_driver =3D { static void sci_remove(struct platform_device *dev) { struct sci_port *s =3D platform_get_drvdata(dev); - unsigned int type =3D s->type; /* uart_remove_... clears it */ =20 sci_ports_in_use &=3D ~BIT(s->port.line); uart_remove_one_port(&sci_uart_driver, &s->port); =20 - if (s->port.fifosize > 1) + if (s->port.fifosize > 1) { device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger); - if (type =3D=3D PORT_SCIFA || type =3D=3D PORT_SCIFB || type =3D=3D PORT_= HSCIF || - type =3D=3D SCI_PORT_RSCI) device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout); + } } =20 static const struct sci_of_data of_sci_scif_sh2 =3D { @@ -3917,15 +3915,10 @@ static int sci_probe(struct platform_device *dev) ret =3D device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger); if (ret) return ret; - } - if (sp->type =3D=3D PORT_SCIFA || sp->type =3D=3D PORT_SCIFB || - sp->type =3D=3D PORT_HSCIF || sp->type =3D=3D SCI_PORT_RSCI) { + ret =3D device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout); if (ret) { - if (sp->port.fifosize > 1) { - device_remove_file(&dev->dev, - &dev_attr_rx_fifo_trigger); - } + device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger); return ret; } } --=20 2.43.0 From nobody Mon Dec 1 22:07:24 2025 Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4201B30FC17 for ; Sat, 29 Nov 2025 16:43:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42e1ca4078csm15970060f8f.29.2025.11.29.08.43.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 Nov 2025 08:43:31 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Wolfram Sang , Lad Prabhakar , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das Subject: [PATCH v5 05/17] serial: rsci: Drop rsci_clear_SCxSR() Date: Sat, 29 Nov 2025 16:43:01 +0000 Message-ID: <20251129164325.209213-6-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251129164325.209213-1-biju.das.jz@bp.renesas.com> References: <20251129164325.209213-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Drop rsci_clear_SCxSR by reusing rsci_clear_CFC() as the contents of both functions are the same. Reviewed-by: Geert Uytterhoeven Signed-off-by: Biju Das --- v4->v5: * No change. v3->v4: * Collected tag * Updated commit header and description * Dropped rsci_clear_SCxSR() instead of rsci_clear_CFC() as it clears the CFCLR register. v2->v3: * No change. v1->v2: * No change. --- drivers/tty/serial/rsci.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/tty/serial/rsci.c b/drivers/tty/serial/rsci.c index 0533a4bb1d03..158173077c2f 100644 --- a/drivers/tty/serial/rsci.c +++ b/drivers/tty/serial/rsci.c @@ -137,10 +137,6 @@ static void rsci_clear_DRxC(struct uart_port *port) rsci_serial_out(port, FFCLR, FFCLR_DRC); } =20 -static void rsci_clear_SCxSR(struct uart_port *port, unsigned int mask) -{ - rsci_serial_out(port, CFCLR, mask); -} =20 static void rsci_start_rx(struct uart_port *port) { @@ -391,7 +387,7 @@ static void rsci_poll_put_char(struct uart_port *port, = unsigned char c) } rsci_serial_out(port, TDR, c); done: - rsci_clear_SCxSR(port, CFCLR_TDREC); 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42e1ca4078csm15970060f8f.29.2025.11.29.08.43.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 Nov 2025 08:43:32 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Wolfram Sang , Lad Prabhakar , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das Subject: [PATCH v5 06/17] serial: sh-sci: Drop extra lines Date: Sat, 29 Nov 2025 16:43:02 +0000 Message-ID: <20251129164325.209213-7-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251129164325.209213-1-biju.das.jz@bp.renesas.com> References: <20251129164325.209213-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Shorten the number lines in sci_init_clocks() by fitting the error messages within an 100-character length limit. Reviewed-by: Geert Uytterhoeven Signed-off-by: Biju Das --- v4->v5: * No change. v3->v4: * Collected tag. v2->v3: * Updated dev_err_probe() in sci_init_clocks() as it fits in 100-column limit. v1->v2: * Updated commit message 80-character->100-character. * Increased line limit for error messages to 100-column limit. --- drivers/tty/serial/sh-sci.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index ff5459c449fb..7ca94fa84a40 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -3186,11 +3186,8 @@ static int sci_init_clocks(struct sci_port *sci_port= , struct device *dev) return PTR_ERR(clk); =20 if (!clk && sci_port->type =3D=3D SCI_PORT_RSCI && - (i =3D=3D SCI_FCK || i =3D=3D SCI_BRG_INT)) { - return dev_err_probe(dev, -ENODEV, - "failed to get %s\n", - name); - } + (i =3D=3D SCI_FCK || i =3D=3D SCI_BRG_INT)) + return dev_err_probe(dev, -ENODEV, "failed to get %s\n", name); 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Reviewed-by: Geert Uytterhoeven Signed-off-by: Biju Das --- v4->v5: * No change. v3->v4: * Collected tag. v2->v3: * No change. v1->v2: * No change. --- drivers/tty/serial/rsci.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/tty/serial/rsci.c b/drivers/tty/serial/rsci.c index 158173077c2f..15ed6cf5c6c5 100644 --- a/drivers/tty/serial/rsci.c +++ b/drivers/tty/serial/rsci.c @@ -24,7 +24,6 @@ MODULE_IMPORT_NS("SH_SCI"); #define CCR3 0x14 #define CCR4 0x18 #define FCR 0x24 -#define DCR 0x30 #define CSR 0x48 #define FRSR 0x50 #define FTSR 0x54 @@ -119,8 +118,6 @@ MODULE_IMPORT_NS("SH_SCI"); /* FFCLR (FIFO Flag CLear Register) */ #define FFCLR_DRC BIT(0) /* DR Clear */ =20 -#define DCR_DEPOL BIT(0) - static u32 rsci_serial_in(struct uart_port *p, int offset) { return readl(p->membase + offset); --=20 2.43.0 From nobody Mon Dec 1 22:07:24 2025 Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A4DAA3101B8 for ; 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42e1ca4078csm15970060f8f.29.2025.11.29.08.43.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 Nov 2025 08:43:33 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Wolfram Sang , Lad Prabhakar , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das Subject: [PATCH v5 08/17] serial: rsci: Drop unused TDR register Date: Sat, 29 Nov 2025 16:43:04 +0000 Message-ID: <20251129164325.209213-9-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251129164325.209213-1-biju.das.jz@bp.renesas.com> References: <20251129164325.209213-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Drop the unused TDR register-related macros. Reviewed-by: Geert Uytterhoeven Signed-off-by: Biju Das --- v4->v5: * No change. v3->v4: * Collected tag. v2->v3: * No change. v1->v2: * No change. --- drivers/tty/serial/rsci.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/tty/serial/rsci.c b/drivers/tty/serial/rsci.c index 15ed6cf5c6c5..5a58c783fe8c 100644 --- a/drivers/tty/serial/rsci.c +++ b/drivers/tty/serial/rsci.c @@ -35,12 +35,6 @@ MODULE_IMPORT_NS("SH_SCI"); #define RDR_FPER BIT(11) /* FIFO Parity Error */ #define RDR_RDAT_MSK GENMASK(8, 0) =20 -/* TDR (Transmit Data Register) */ -#define TDR_MPBT BIT(9) /* Multiprocessor Transfer */ -#define TDR_TDAT_9BIT_LSHIFT 0 -#define TDR_TDAT_9BIT_VAL 0x1FF -#define TDR_TDAT_9BIT_MSK (TDR_TDAT_9BIT_VAL << TDR_TDAT_9BIT_LSHIFT) - /* CCR0 (Common Control Register 0) */ #define CCR0_SSE BIT(24) /* SSn# Pin Function Enable */ #define CCR0_TEIE BIT(21) /* Transmit End Interrupt Enable */ --=20 2.43.0 From nobody Mon Dec 1 22:07:24 2025 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A1EFF14A4CC for ; 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42e1ca4078csm15970060f8f.29.2025.11.29.08.43.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 Nov 2025 08:43:34 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Wolfram Sang , Lad Prabhakar , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das Subject: [PATCH v5 09/17] serial: sh-sci: Use devm_reset_control_array_get_exclusive() Date: Sat, 29 Nov 2025 16:43:05 +0000 Message-ID: <20251129164325.209213-10-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251129164325.209213-1-biju.das.jz@bp.renesas.com> References: <20251129164325.209213-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Replace devm_*_get_exclusive()->devm_*_array_get_exclusive() to support existing SoCs along with RZ/G3E as RZ/G3E has 2 resets. Reviewed-by: Geert Uytterhoeven Signed-off-by: Biju Das --- v4->v5: * No change. v3->v4: * Collected tag. v2->v3: * No change. v1->v2: * No change. --- drivers/tty/serial/sh-sci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index 7ca94fa84a40..704f175b14e4 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -3708,7 +3708,7 @@ static struct plat_sci_port *sci_parse_dt(struct plat= form_device *pdev, =20 data =3D of_device_get_match_data(&pdev->dev); =20 - rstc =3D devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); + rstc =3D devm_reset_control_array_get_optional_exclusive(&pdev->dev); if (IS_ERR(rstc)) return ERR_PTR(dev_err_probe(&pdev->dev, PTR_ERR(rstc), "failed to get reset ctrl\n")); --=20 2.43.0 From nobody Mon Dec 1 22:07:24 2025 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 682D330F818 for ; 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42e1ca4078csm15970060f8f.29.2025.11.29.08.43.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 Nov 2025 08:43:34 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Wolfram Sang , Lad Prabhakar , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das Subject: [PATCH v5 10/17] serial: sh-sci: Add sci_is_rsci_type() Date: Sat, 29 Nov 2025 16:43:06 +0000 Message-ID: <20251129164325.209213-11-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251129164325.209213-1-biju.das.jz@bp.renesas.com> References: <20251129164325.209213-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add sci_is_rsci_type() for RSCI port type. This will simplify the code when the support added for RSCI_PORT_SCIF32 private PORT type. Reviewed-by: Geert Uytterhoeven Signed-off-by: Biju Das --- v4->v5: * No change. v3->v4: * Collected tag. * Updated commit description. v2->v3: * No change. v1->v2: * No change. --- drivers/tty/serial/sh-sci.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index 704f175b14e4..b7fef518a2b8 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -1182,6 +1182,11 @@ static int sci_handle_errors(struct uart_port *port) return copied; } =20 +static bool sci_is_rsci_type(u8 type) +{ + return (type =3D=3D SCI_PORT_RSCI); +} + static int sci_handle_fifo_overrun(struct uart_port *port) { struct tty_port *tport =3D &port->state->port; @@ -1190,7 +1195,7 @@ static int sci_handle_fifo_overrun(struct uart_port *= port) int copied =3D 0; u32 status; =20 - if (s->type !=3D SCI_PORT_RSCI) { + if (!sci_is_rsci_type(s->type)) { reg =3D sci_getreg(port, s->params->overrun_reg); if (!reg->size) return 0; @@ -1198,7 +1203,7 @@ static int sci_handle_fifo_overrun(struct uart_port *= port) =20 status =3D s->ops->read_reg(port, s->params->overrun_reg); if (status & s->params->overrun_mask) { - if (s->type =3D=3D SCI_PORT_RSCI) { + if (sci_is_rsci_type(s->type)) { /* * All of the CFCLR_*C clearing bits match the corresponding * CSR_*status bits. So, reuse the overrun mask for clearing. @@ -2015,7 +2020,7 @@ static irqreturn_t sci_tx_end_interrupt(int irq, void= *ptr) unsigned long flags; u32 ctrl; =20 - if (s->type !=3D PORT_SCI && s->type !=3D SCI_PORT_RSCI) + if (s->type !=3D PORT_SCI && !sci_is_rsci_type(s->type)) return sci_tx_interrupt(irq, ptr); =20 uart_port_lock_irqsave(port, &flags); @@ -3289,7 +3294,7 @@ static int sci_init_single(struct platform_device *de= v, * The fourth interrupt on SCI and RSCI port is transmit end interrupt, so * shuffle the interrupts. */ - if (p->type =3D=3D PORT_SCI || p->type =3D=3D SCI_PORT_RSCI) + if (p->type =3D=3D PORT_SCI || sci_is_rsci_type(p->type)) swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]); =20 /* The SCI generates several interrupts. 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42e1ca4078csm15970060f8f.29.2025.11.29.08.43.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 Nov 2025 08:43:35 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Wolfram Sang , Lad Prabhakar , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das Subject: [PATCH v5 11/17] serial: sh-sci: Rename port SCI_PORT_RSCI->RSCI_PORT_SCIF16 Date: Sat, 29 Nov 2025 16:43:07 +0000 Message-ID: <20251129164325.209213-12-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251129164325.209213-1-biju.das.jz@bp.renesas.com> References: <20251129164325.209213-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Rename port SCI_PORT_RSCI->RSCI_PORT_SCIF16 to differentiate it from RZ/G3E port that has 32-stage FIFO. Signed-off-by: Biju Das --- v4->v5: * No change. v4: * New patch. --- drivers/tty/serial/rsci.c | 2 +- drivers/tty/serial/sh-sci-common.h | 2 +- drivers/tty/serial/sh-sci.c | 8 ++++---- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/tty/serial/rsci.c b/drivers/tty/serial/rsci.c index 5a58c783fe8c..7f4cb04daeeb 100644 --- a/drivers/tty/serial/rsci.c +++ b/drivers/tty/serial/rsci.c @@ -462,7 +462,7 @@ static const struct sci_port_ops rsci_port_ops =3D { }; =20 struct sci_of_data of_sci_rsci_data =3D { - .type =3D SCI_PORT_RSCI, + .type =3D RSCI_PORT_SCIF16, .ops =3D &rsci_port_ops, .uart_ops =3D &rsci_uart_ops, .params =3D &rsci_port_params, diff --git a/drivers/tty/serial/sh-sci-common.h b/drivers/tty/serial/sh-sci= -common.h index e3c028df14f1..1b9480c7f4cb 100644 --- a/drivers/tty/serial/sh-sci-common.h +++ b/drivers/tty/serial/sh-sci-common.h @@ -7,7 +7,7 @@ =20 /* Private port IDs */ enum SCI_PORT_TYPE { - SCI_PORT_RSCI =3D BIT(7) | 0, + RSCI_PORT_SCIF16 =3D BIT(7) | 0, }; =20 enum SCI_CLKS { diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index b7fef518a2b8..624ef41701f2 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -1184,7 +1184,7 @@ static int sci_handle_errors(struct uart_port *port) =20 static bool sci_is_rsci_type(u8 type) { - return (type =3D=3D SCI_PORT_RSCI); + return (type =3D=3D RSCI_PORT_SCIF16); } =20 static int sci_handle_fifo_overrun(struct uart_port *port) @@ -3178,7 +3178,7 @@ static int sci_init_clocks(struct sci_port *sci_port,= struct device *dev) =20 if (sci_port->type =3D=3D PORT_HSCIF) { clk_names[SCI_SCK] =3D "hsck"; - } else if (sci_port->type =3D=3D SCI_PORT_RSCI) { + } else if (sci_port->type =3D=3D RSCI_PORT_SCIF16) { clk_names[SCI_FCK] =3D "operation"; clk_names[SCI_BRG_INT] =3D "bus"; } @@ -3190,7 +3190,7 @@ static int sci_init_clocks(struct sci_port *sci_port,= struct device *dev) if (IS_ERR(clk)) return PTR_ERR(clk); =20 - if (!clk && sci_port->type =3D=3D SCI_PORT_RSCI && + if (!clk && sci_port->type =3D=3D RSCI_PORT_SCIF16 && (i =3D=3D SCI_FCK || i =3D=3D SCI_BRG_INT)) return dev_err_probe(dev, -ENODEV, "failed to get %s\n", name); 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42e1ca4078csm15970060f8f.29.2025.11.29.08.43.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 Nov 2025 08:43:36 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Wolfram Sang , Lad Prabhakar , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das Subject: [PATCH v5 12/17] serial: sh-sci: Add RSCI_PORT_SCIF32 port ID Date: Sat, 29 Nov 2025 16:43:08 +0000 Message-ID: <20251129164325.209213-13-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251129164325.209213-1-biju.das.jz@bp.renesas.com> References: <20251129164325.209213-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The RZ/G3E RSCI IP has 32-stage FIFO compared to 16-stage FIFO on RZ/T2H. Add RSCI_PORT_SCIF32 port ID to differentiate it from RZ/T2H RSCI and update sci_is_rsci_type() and sci_is_fifo_type() Signed-off-by: Biju Das --- v4->v5: * No change. v3->v4: * Dropped enum RSCI_PORT_SCI * Replaced the enum RSCI_PORT_SCIF->RSCI_PORT_SCIF32 * Moved rx_trigger update to later patch. v2->v3: * No change. v1->v2: * No change. --- drivers/tty/serial/sh-sci-common.h | 1 + drivers/tty/serial/sh-sci.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/sh-sci-common.h b/drivers/tty/serial/sh-sci= -common.h index 1b9480c7f4cb..abcd5bcc7c36 100644 --- a/drivers/tty/serial/sh-sci-common.h +++ b/drivers/tty/serial/sh-sci-common.h @@ -8,6 +8,7 @@ /* Private port IDs */ enum SCI_PORT_TYPE { RSCI_PORT_SCIF16 =3D BIT(7) | 0, + RSCI_PORT_SCIF32 =3D BIT(7) | 1, }; =20 enum SCI_CLKS { diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index 624ef41701f2..a63370f22574 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -1184,7 +1184,7 @@ static int sci_handle_errors(struct uart_port *port) =20 static bool sci_is_rsci_type(u8 type) { - return (type =3D=3D RSCI_PORT_SCIF16); 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42e1ca4078csm15970060f8f.29.2025.11.29.08.43.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 Nov 2025 08:43:37 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Wolfram Sang , Lad Prabhakar , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das Subject: [PATCH v5 13/17] serial: sh-sci: Add support for RZ/G3E RSCI clks Date: Sat, 29 Nov 2025 16:43:09 +0000 Message-ID: <20251129164325.209213-14-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251129164325.209213-1-biju.das.jz@bp.renesas.com> References: <20251129164325.209213-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das RZ/G3E RSCI has 6 clocks (5 module clocks + 1 external clock). Add support for the module clocks. Signed-off-by: Biju Das --- v4->v5: * No change. v3->v4: * Replaced clock name of RZ/G3E from bus->pclk * Rearranged clocks tclk{4,16,64}. * Reduced the checks in sci_init_clocks() by avoid looking up clocks that are not relevant for the port. v2->v3: * No change. v1->v2: * Updated commit description. --- drivers/tty/serial/sh-sci-common.h | 3 +++ drivers/tty/serial/sh-sci.c | 10 ++++++++++ 2 files changed, 13 insertions(+) diff --git a/drivers/tty/serial/sh-sci-common.h b/drivers/tty/serial/sh-sci= -common.h index abcd5bcc7c36..5d30771278b4 100644 --- a/drivers/tty/serial/sh-sci-common.h +++ b/drivers/tty/serial/sh-sci-common.h @@ -16,6 +16,9 @@ enum SCI_CLKS { SCI_SCK, /* Optional External Clock */ SCI_BRG_INT, /* Optional BRG Internal Clock Source */ SCI_SCIF_CLK, /* Optional BRG External Clock Source */ + SCI_FCK_DIV4, /* Optional Functional Clock frequency-divided by 4 */ + SCI_FCK_DIV16, /* Optional Functional Clock frequency-divided by 16 */ + SCI_FCK_DIV64, /* Optional Functional Clock frequency-divided by 64 */ SCI_NUM_CLKS }; =20 diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index a63370f22574..5d7e78f95c70 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -3172,6 +3172,9 @@ static int sci_init_clocks(struct sci_port *sci_port,= struct device *dev) [SCI_SCK] =3D "sck", [SCI_BRG_INT] =3D "brg_int", [SCI_SCIF_CLK] =3D "scif_clk", + [SCI_FCK_DIV4] =3D "tclk_div4", + [SCI_FCK_DIV16] =3D "tclk_div16", + [SCI_FCK_DIV64] =3D "tclk_div64", }; struct clk *clk; unsigned int i; @@ -3181,6 +3184,9 @@ static int sci_init_clocks(struct sci_port *sci_port,= struct device *dev) } else if (sci_port->type =3D=3D RSCI_PORT_SCIF16) { clk_names[SCI_FCK] =3D "operation"; clk_names[SCI_BRG_INT] =3D "bus"; + } else if (sci_port->type =3D=3D RSCI_PORT_SCIF32) { + clk_names[SCI_FCK] =3D "tclk"; + clk_names[SCI_BRG_INT] =3D "pclk"; } =20 for (i =3D 0; i < SCI_NUM_CLKS; i++) { @@ -3194,6 +3200,10 @@ static int sci_init_clocks(struct sci_port *sci_port= , struct device *dev) (i =3D=3D SCI_FCK || i =3D=3D SCI_BRG_INT)) return dev_err_probe(dev, -ENODEV, "failed to get %s\n", name); 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42e1ca4078csm15970060f8f.29.2025.11.29.08.43.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 Nov 2025 08:43:37 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Wolfram Sang , Lad Prabhakar , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das Subject: [PATCH v5 14/17] serial: sh-sci: Make sci_scbrr_calc() public Date: Sat, 29 Nov 2025 16:43:10 +0000 Message-ID: <20251129164325.209213-15-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251129164325.209213-1-biju.das.jz@bp.renesas.com> References: <20251129164325.209213-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Make the function sci_scbrr_calc() public for code reuse to support RZ/G3E RSCI IP. Reviewed-by: Geert Uytterhoeven Signed-off-by: Biju Das --- v4->v5: * No change. v3->v4: * Collected tag. v2->v3: * No change. v1->v2: * No change. --- drivers/tty/serial/sh-sci-common.h | 3 +++ drivers/tty/serial/sh-sci.c | 6 +++--- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/tty/serial/sh-sci-common.h b/drivers/tty/serial/sh-sci= -common.h index 5d30771278b4..976e394ab968 100644 --- a/drivers/tty/serial/sh-sci-common.h +++ b/drivers/tty/serial/sh-sci-common.h @@ -169,6 +169,9 @@ void sci_port_enable(struct sci_port *sci_port); int sci_startup(struct uart_port *port); void sci_shutdown(struct uart_port *port); =20 +int sci_scbrr_calc(struct sci_port *s, unsigned int bps, unsigned int *brr, + unsigned int *srr, unsigned int *cks); + #define min_sr(_port) ffs((_port)->sampling_rate_mask) #define max_sr(_port) fls((_port)->sampling_rate_mask) =20 diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index 5d7e78f95c70..e2ba752f9c16 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -2573,9 +2573,8 @@ static int sci_brg_calc(struct sci_port *s, unsigned = int bps, } =20 /* calculate sample rate, BRR, and clock select */ -static int sci_scbrr_calc(struct sci_port *s, unsigned int bps, - unsigned int *brr, unsigned int *srr, - unsigned int *cks) +int sci_scbrr_calc(struct sci_port *s, unsigned int bps, unsigned int *brr, + unsigned int *srr, unsigned int *cks) { unsigned long freq =3D s->clk_rates[SCI_FCK]; unsigned int sr, br, prediv, scrate, c; @@ -2639,6 +2638,7 @@ static int sci_scbrr_calc(struct sci_port *s, unsigne= d int bps, min_err, *brr, *srr + 1, *cks); return min_err; } +EXPORT_SYMBOL_NS_GPL(sci_scbrr_calc, "SH_SCI"); =20 static void sci_reset(struct uart_port *port) { --=20 2.43.0 From nobody Mon Dec 1 22:07:24 2025 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 338A03101D2 for ; Sat, 29 Nov 2025 16:43:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764434624; cv=none; b=N7SlI3qCj9bcjrM6fpwhnkrdZzf+oSytbVJ75GiENnFOzCR1TVDHE4kEUHNZeDKtR/kNfAqsBFbRVMGHv12YFK4SmDDPuLyqD8W5E2WWUWwti8J1QS4NfvSqzSyGeQYQ7vMBW0l/p2SEBHYY5+3rOVyfW7cFJsvd0rqplr0fFVw= ARC-Message-Signature: i=1; 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42e1ca4078csm15970060f8f.29.2025.11.29.08.43.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 Nov 2025 08:43:38 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Wolfram Sang , Lad Prabhakar , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das Subject: [PATCH v5 15/17] serial: sh-sci: Add finish_console_write() callback Date: Sat, 29 Nov 2025 16:43:11 +0000 Message-ID: <20251129164325.209213-16-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251129164325.209213-1-biju.das.jz@bp.renesas.com> References: <20251129164325.209213-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add finish_console_write() callback as RZ/G3E RSCI IP needs special handling compared to other SoCs. Signed-off-by: Biju Das --- v4->v5: * No change. v3->v4: * No change. v2->v3: * No change. v1->v2: * No change. --- drivers/tty/serial/sh-sci-common.h | 1 + drivers/tty/serial/sh-sci.c | 5 ++++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/sh-sci-common.h b/drivers/tty/serial/sh-sci= -common.h index 976e394ab968..f363a659c46a 100644 --- a/drivers/tty/serial/sh-sci-common.h +++ b/drivers/tty/serial/sh-sci-common.h @@ -93,6 +93,7 @@ struct sci_port_ops { void (*shutdown_complete)(struct uart_port *port); =20 void (*prepare_console_write)(struct uart_port *port, u32 ctrl); + void (*finish_console_write)(struct uart_port *port, u32 ctrl); void (*console_save)(struct uart_port *port); void (*console_restore)(struct uart_port *port); size_t (*suspend_regs_size)(void); diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index e2ba752f9c16..8f3314b258d6 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -3431,7 +3431,10 @@ static void serial_console_write(struct console *co,= const char *s, cpu_relax(); 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42e1ca4078csm15970060f8f.29.2025.11.29.08.43.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 Nov 2025 08:43:38 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Wolfram Sang , Lad Prabhakar , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das Subject: [PATCH v5 16/17] serial: rsci: Rename early_console data, port_params and callback() names Date: Sat, 29 Nov 2025 16:43:12 +0000 Message-ID: <20251129164325.209213-17-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251129164325.209213-1-biju.das.jz@bp.renesas.com> References: <20251129164325.209213-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Rename rsci_early_console_setup()->rsci_rzt2h_early_console_setup(), the early_console data of_sci_rsci_data->of_rsci_rzt2h_data and the port_params rsci_port_params->rsci_rzt2h_port_params to support RZ/G3E RSCI that uses different data and callback(). Signed-off-by: Biju Das --- v4->v5: * Update commit header and description. * Renamed rsci_port_params->rsci_rzt2h_port_params. v4: * New patch. --- drivers/tty/serial/rsci.c | 14 +++++++------- drivers/tty/serial/rsci.h | 2 +- drivers/tty/serial/sh-sci.c | 2 +- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/tty/serial/rsci.c b/drivers/tty/serial/rsci.c index 7f4cb04daeeb..70ff81fdc027 100644 --- a/drivers/tty/serial/rsci.c +++ b/drivers/tty/serial/rsci.c @@ -419,7 +419,7 @@ static const struct sci_port_params_bits rsci_port_para= m_bits =3D { .poll_sent_bits =3D CSR_TDRE | CSR_TEND, }; =20 -static const struct sci_port_params rsci_port_params =3D { +static const struct sci_port_params rsci_rzt2h_port_params =3D { .fifosize =3D 16, .overrun_reg =3D CSR, .overrun_mask =3D CSR_ORER, @@ -461,22 +461,22 @@ static const struct sci_port_ops rsci_port_ops =3D { .shutdown_complete =3D rsci_shutdown_complete, }; =20 -struct sci_of_data of_sci_rsci_data =3D { +struct sci_of_data of_rsci_rzt2h_data =3D { .type =3D RSCI_PORT_SCIF16, .ops =3D &rsci_port_ops, .uart_ops =3D &rsci_uart_ops, - .params =3D &rsci_port_params, + .params =3D &rsci_rzt2h_port_params, }; =20 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON =20 -static int __init rsci_early_console_setup(struct earlycon_device *device, - const char *opt) +static int __init rsci_rzt2h_early_console_setup(struct earlycon_device *d= evice, + const char *opt) { - return scix_early_console_setup(device, &of_sci_rsci_data); + return scix_early_console_setup(device, &of_rsci_rzt2h_data); } =20 -OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g077-rsci", rsci_early_console_set= up); +OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g077-rsci", rsci_rzt2h_early_conso= le_setup); =20 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */ =20 diff --git a/drivers/tty/serial/rsci.h b/drivers/tty/serial/rsci.h index 2af3f28b465a..9547148e8bd1 100644 --- a/drivers/tty/serial/rsci.h +++ b/drivers/tty/serial/rsci.h @@ -5,6 +5,6 @@ =20 #include "sh-sci-common.h" =20 -extern struct sci_of_data of_sci_rsci_data; +extern struct sci_of_data of_rsci_rzt2h_data; =20 #endif /* __RSCI_H__ */ diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index 8f3314b258d6..677293115f1e 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -3664,7 +3664,7 @@ static const struct of_device_id of_sci_match[] __may= be_unused =3D { #ifdef CONFIG_SERIAL_RSCI { .compatible =3D "renesas,r9a09g077-rsci", - .data =3D &of_sci_rsci_data, + .data =3D &of_rsci_rzt2h_data, }, #endif /* CONFIG_SERIAL_RSCI */ /* Family-specific types */ --=20 2.43.0 From nobody Mon Dec 1 22:07:24 2025 Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A69F53126A9 for ; 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42e1ca4078csm15970060f8f.29.2025.11.29.08.43.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 Nov 2025 08:43:39 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Wolfram Sang , Lad Prabhakar , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das Subject: [PATCH v5 17/17] serial: sh-sci: Add support for RZ/G3E RSCI Date: Sat, 29 Nov 2025 16:43:13 +0000 Message-ID: <20251129164325.209213-18-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251129164325.209213-1-biju.das.jz@bp.renesas.com> References: <20251129164325.209213-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add support for RZ/G3E RSCI. RSCI IP found on the RZ/G3E SoC is similar to RZ/T2H, but it has a 32-stage FIFO. It has 6 clocks(5 module clocks + 1 external clock) instead of 3 clocks(2 module clocks + 1 external clock) on T2H, has 6 irqs compared to 4 on RZ/T2H and has multiple resets. Add support for the hardware flow control. Signed-off-by: Biju Das --- v4->v5: * Updated commit description. * Renamed rsci_rzg3e_scif_port_params->rsci_rzg3e_port_params. v3->v4: * Updated commit description and header * Updated rsci_type() to drop "scif" type instead use "rsci" * Replaced the compatible "renesas,r9a09g047-rscif" with "renesas,r9a09g047-rsci" * Renamed the port enum from RSCI_PORT_SCIF->RSCI_PORT_SCIF32. * Renamed of_rsci_scif_data->of_rsci_rzg3e_data * Renamed the funvtion rsci_rzg3e_scif_early_console_setup() with rsci_rzg3e_early_console_setup(). v2->v3: * Dropped cpu_relax() from rsci_finish_console_write() and added a comment. * Added sci_is_rsci_fifo_type() helper for reuse in probe() and remove(). v1->v2: * Updated commit description. * Updated multiline comment to fit into single line. * Updated set_termios() for getting baud_rate() --- drivers/tty/serial/rsci.c | 260 ++++++++++++++++++++++++++++++++++-- drivers/tty/serial/rsci.h | 1 + drivers/tty/serial/sh-sci.c | 5 + 3 files changed, 257 insertions(+), 9 deletions(-) diff --git a/drivers/tty/serial/rsci.c b/drivers/tty/serial/rsci.c index 70ff81fdc027..1ef7c6d61707 100644 --- a/drivers/tty/serial/rsci.c +++ b/drivers/tty/serial/rsci.c @@ -11,6 +11,8 @@ #include #include #include + +#include "serial_mctrl_gpio.h" #include "rsci.h" =20 MODULE_IMPORT_NS("SH_SCI"); @@ -59,6 +61,41 @@ MODULE_IMPORT_NS("SH_SCI"); #define CCR1_CTSPEN BIT(1) /* CTS External Pin Enable */ #define CCR1_CTSE BIT(0) /* CTS Enable */ =20 +/* CCR2 (Common Control Register 2) */ +#define CCR2_INIT 0xFF000004 +#define CCR2_CKS_TCLK (0) /* TCLK clock */ +#define CCR2_CKS_TCLK_DIV4 BIT(20) /* TCLK/4 clock */ +#define CCR2_CKS_TCLK_DIV16 BIT(21) /* TCLK16 clock */ +#define CCR2_CKS_TCLK_DIV64 (BIT(21) | BIT(20)) /* TCLK/64 clock */ +#define CCR2_BRME BIT(16) /* Bitrate Modulation Enable */ +#define CCR2_ABCSE BIT(6) /* Asynchronous Mode Extended Base Clock Selec= t */ +#define CCR2_ABCS BIT(5) /* Asynchronous Mode Base Clock Select */ +#define CCR2_BGDM BIT(4) /* Baud Rate Generator Double-Speed Mode Select= */ + +/* CCR3 (Common Control Register 3) */ +#define CCR3_INIT 0x1203 +#define CCR3_BLK BIT(29) /* Block Transfer Mode */ +#define CCR3_GM BIT(28) /* GSM Mode */ +#define CCR3_CKE1 BIT(25) /* Clock Enable 1 */ +#define CCR3_CKE0 BIT(24) /* Clock Enable 0 */ +#define CCR3_DEN BIT(21) /* Driver Enabled */ +#define CCR3_FM BIT(20) /* FIFO Mode Select */ +#define CCR3_MP BIT(19) /* Multi-Processor Mode */ +#define CCR3_MOD_ASYNC 0 /* Asynchronous mode (Multi-processor mode) */ +#define CCR3_MOD_IRDA BIT(16) /* Smart card interface mode */ +#define CCR3_MOD_CLK_SYNC BIT(17) /* Clock synchronous mode */ +#define CCR3_MOD_SPI (BIT(17) | BIT(16)) /* Simple SPI mode */ +#define CCR3_MOD_I2C BIT(18) /* Simple I2C mode */ +#define CCR3_RXDESEL BIT(15) /* Asynchronous Start Bit Edge Detection Se= lect */ +#define CCR3_STP BIT(14) /* Stop bit Length */ +#define CCR3_SINV BIT(13) /* Transmitted/Received Data Invert */ +#define CCR3_LSBF BIT(12) /* LSB First select */ +#define CCR3_CHR1 BIT(9) /* Character Length */ +#define CCR3_CHR0 BIT(8) /* Character Length */ +#define CCR3_BPEN BIT(7) /* Synchronizer Bypass Enable */ +#define CCR3_CPOL BIT(1) /* Clock Polarity Select */ +#define CCR3_CPHA BIT(0) /* Clock Phase Select */ + /* FCR (FIFO Control Register) */ #define FCR_RFRST BIT(23) /* Receive FIFO Data Register Reset */ #define FCR_TFRST BIT(15) /* Transmit FIFO Data Register Reset */ @@ -138,6 +175,29 @@ static void rsci_start_rx(struct uart_port *port) rsci_serial_out(port, CCR0, ctrl); } =20 +static void rsci_enable_ms(struct uart_port *port) +{ + mctrl_gpio_enable_ms(to_sci_port(port)->gpios); +} + +static void rsci_init_pins(struct uart_port *port, unsigned int cflag) +{ + struct sci_port *s =3D to_sci_port(port); + + /* Use port-specific handler if provided */ + if (s->cfg->ops && s->cfg->ops->init_pins) { + s->cfg->ops->init_pins(port, cflag); + return; + } + + if (!s->has_rtscts) + return; + + if (s->autorts) + rsci_serial_out(port, CCR1, rsci_serial_in(port, CCR1) | + CCR1_CTSE | CCR1_CTSPEN); +} + static int rsci_scif_set_rtrg(struct uart_port *port, int rx_trig) { u32 fcr =3D rsci_serial_in(port, FCR); @@ -157,18 +217,119 @@ static int rsci_scif_set_rtrg(struct uart_port *port= , int rx_trig) static void rsci_set_termios(struct uart_port *port, struct ktermios *term= ios, const struct ktermios *old) { + unsigned int ccr2_val =3D CCR2_INIT, ccr3_val =3D CCR3_INIT; + unsigned int ccr0_val =3D 0, ccr1_val =3D 0, ccr4_val =3D 0; + unsigned int brr1 =3D 255, cks1 =3D 0, srr1 =3D 15; struct sci_port *s =3D to_sci_port(port); + unsigned int brr =3D 255, cks =3D 0; + int min_err =3D INT_MAX, err; + unsigned long max_freq =3D 0; + unsigned int baud, i; unsigned long flags; + unsigned int ctrl; + int best_clk =3D -1; + + if ((termios->c_cflag & CSIZE) =3D=3D CS7) { + ccr3_val |=3D CCR3_CHR0; + } else { + termios->c_cflag &=3D ~CSIZE; + termios->c_cflag |=3D CS8; + } + + if (termios->c_cflag & PARENB) + ccr1_val |=3D CCR1_PE; + + if (termios->c_cflag & PARODD) + ccr1_val |=3D (CCR1_PE | CCR1_PM); + + if (termios->c_cflag & CSTOPB) + ccr3_val |=3D CCR3_STP; + + /* Enable noise filter function */ + ccr1_val |=3D CCR1_NFEN; + + /* + * earlyprintk comes here early on with port->uartclk set to zero. + * the clock framework is not up and running at this point so here + * we assume that 115200 is the maximum baud rate. please note that + * the baud rate is not programmed during earlyprintk - it is assumed + * that the previous boot loader has enabled required clocks and + * setup the baud rate generator hardware for us already. + */ + if (!port->uartclk) { + max_freq =3D 115200; + } else { + for (i =3D 0; i < SCI_NUM_CLKS; i++) + max_freq =3D max(max_freq, s->clk_rates[i]); + + max_freq /=3D min_sr(s); + } + + baud =3D uart_get_baud_rate(port, termios, old, 0, max_freq); + if (!baud) + goto done; + + /* Divided Functional Clock using standard Bit Rate Register */ + err =3D sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1); + if (abs(err) < abs(min_err)) { + best_clk =3D SCI_FCK; + ccr0_val =3D 0; + min_err =3D err; + brr =3D brr1; + cks =3D cks1; + } + +done: + if (best_clk >=3D 0) + dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n", + s->clks[best_clk], baud, min_err); =20 sci_port_enable(s); uart_port_lock_irqsave(port, &flags); =20 - /* For now, only RX enabling is supported */ - if (termios->c_cflag & CREAD) + uart_update_timeout(port, termios->c_cflag, baud); + + rsci_serial_out(port, CCR0, ccr0_val); + + ccr3_val |=3D CCR3_FM; + rsci_serial_out(port, CCR3, ccr3_val); + + ccr2_val |=3D (cks << 20) | (brr << 8); + rsci_serial_out(port, CCR2, ccr2_val); + + rsci_serial_out(port, CCR1, ccr1_val); + rsci_serial_out(port, CCR4, ccr4_val); + + ctrl =3D rsci_serial_in(port, FCR); + ctrl |=3D (FCR_RFRST | FCR_TFRST); + rsci_serial_out(port, FCR, ctrl); + + if (s->rx_trigger > 1) + rsci_scif_set_rtrg(port, s->rx_trigger); + + port->status &=3D ~UPSTAT_AUTOCTS; + s->autorts =3D false; + + if ((port->flags & UPF_HARD_FLOW) && (termios->c_cflag & CRTSCTS)) { + port->status |=3D UPSTAT_AUTOCTS; + s->autorts =3D true; + } + + rsci_init_pins(port, termios->c_cflag); + rsci_serial_out(port, CFCLR, CFCLR_CLRFLAG); + rsci_serial_out(port, FFCLR, FFCLR_DRC); + + ccr0_val |=3D CCR0_RE; + rsci_serial_out(port, CCR0, ccr0_val); + + if ((termios->c_cflag & CREAD) !=3D 0) rsci_start_rx(port); =20 uart_port_unlock_irqrestore(port, flags); sci_port_disable(s); + + if (UART_ENABLE_MS(port, termios->c_cflag)) + rsci_enable_ms(port); } =20 static int rsci_txfill(struct uart_port *port) @@ -193,13 +354,34 @@ static unsigned int rsci_tx_empty(struct uart_port *p= ort) =20 static void rsci_set_mctrl(struct uart_port *port, unsigned int mctrl) { - /* Not supported yet */ + if (mctrl & TIOCM_LOOP) { + /* Standard loopback mode */ + rsci_serial_out(port, CCR1, rsci_serial_in(port, CCR1) | CCR1_SPLP); + } } =20 static unsigned int rsci_get_mctrl(struct uart_port *port) { - /* Not supported yet */ - return 0; + struct sci_port *s =3D to_sci_port(port); + struct mctrl_gpios *gpios =3D s->gpios; + unsigned int mctrl =3D 0; + + mctrl_gpio_get(gpios, &mctrl); + + /* + * CTS/RTS is handled in hardware when supported, while nothing + * else is wired up. + */ + if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) + mctrl |=3D TIOCM_CTS; + + if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)) + mctrl |=3D TIOCM_DSR; + + if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)) + mctrl |=3D TIOCM_CAR; + + return mctrl; } =20 static void rsci_clear_CFC(struct uart_port *port, unsigned int mask) @@ -329,7 +511,8 @@ static void rsci_receive_chars(struct uart_port *port) continue; } =20 - /* Store data and status. + /* + * Store data and status. * Non FIFO mode is not supported */ if (rdat & RDR_FFER) { @@ -363,6 +546,28 @@ static void rsci_receive_chars(struct uart_port *port) } } =20 +static void rsci_break_ctl(struct uart_port *port, int break_state) +{ + unsigned short ccr0_val, ccr1_val; + unsigned long flags; + + uart_port_lock_irqsave(port, &flags); + ccr1_val =3D rsci_serial_in(port, CCR1); + ccr0_val =3D rsci_serial_in(port, CCR0); + + if (break_state =3D=3D -1) { + ccr1_val =3D (ccr1_val | CCR1_SPB2IO) & ~CCR1_SPB2DT; + ccr0_val &=3D ~CCR0_TE; + } else { + ccr1_val =3D (ccr1_val | CCR1_SPB2DT) & ~CCR1_SPB2IO; + ccr0_val |=3D CCR0_TE; + } + + rsci_serial_out(port, CCR1, ccr1_val); + rsci_serial_out(port, CCR0, ccr0_val); + uart_port_unlock_irqrestore(port, flags); +} + static void rsci_poll_put_char(struct uart_port *port, unsigned char c) { u32 status; @@ -384,12 +589,21 @@ static void rsci_poll_put_char(struct uart_port *port= , unsigned char c) static void rsci_prepare_console_write(struct uart_port *port, u32 ctrl) { struct sci_port *s =3D to_sci_port(port); - u32 ctrl_temp =3D - s->params->param_bits->rxtx_enable | CCR0_TIE | - s->hscif_tot; + u32 ctrl_temp =3D s->params->param_bits->rxtx_enable; + + if (s->type =3D=3D RSCI_PORT_SCIF16) + ctrl_temp |=3D CCR0_TIE | s->hscif_tot; + rsci_serial_out(port, CCR0, ctrl_temp); } =20 +static void rsci_finish_console_write(struct uart_port *port, u32 ctrl) +{ + /* First set TE =3D 0 and then restore the CCR0 value */ + rsci_serial_out(port, CCR0, ctrl & ~CCR0_TE); + rsci_serial_out(port, CCR0, ctrl); +} + static const char *rsci_type(struct uart_port *port) { return "rsci"; @@ -419,6 +633,17 @@ static const struct sci_port_params_bits rsci_port_par= am_bits =3D { .poll_sent_bits =3D CSR_TDRE | CSR_TEND, }; =20 +static const struct sci_port_params rsci_rzg3e_port_params =3D { + .fifosize =3D 32, + .overrun_reg =3D CSR, + .overrun_mask =3D CSR_ORER, + .sampling_rate_mask =3D SCI_SR(32), + .error_mask =3D RSCI_DEFAULT_ERROR_MASK, + .error_clear =3D RSCI_ERROR_CLEAR, + .param_bits =3D &rsci_port_param_bits, + .common_regs =3D &rsci_common_regs, +}; + static const struct sci_port_params rsci_rzt2h_port_params =3D { .fifosize =3D 16, .overrun_reg =3D CSR, @@ -437,6 +662,8 @@ static const struct uart_ops rsci_uart_ops =3D { .start_tx =3D rsci_start_tx, .stop_tx =3D rsci_stop_tx, .stop_rx =3D rsci_stop_rx, + .enable_ms =3D rsci_enable_ms, + .break_ctl =3D rsci_break_ctl, .startup =3D sci_startup, .shutdown =3D sci_shutdown, .set_termios =3D rsci_set_termios, @@ -456,11 +683,19 @@ static const struct sci_port_ops rsci_port_ops =3D { .receive_chars =3D rsci_receive_chars, .poll_put_char =3D rsci_poll_put_char, .prepare_console_write =3D rsci_prepare_console_write, + .finish_console_write =3D rsci_finish_console_write, .suspend_regs_size =3D rsci_suspend_regs_size, .set_rtrg =3D rsci_scif_set_rtrg, .shutdown_complete =3D rsci_shutdown_complete, }; =20 +struct sci_of_data of_rsci_rzg3e_data =3D { + .type =3D RSCI_PORT_SCIF32, + .ops =3D &rsci_port_ops, + .uart_ops =3D &rsci_uart_ops, + .params =3D &rsci_rzg3e_port_params, +}; + struct sci_of_data of_rsci_rzt2h_data =3D { .type =3D RSCI_PORT_SCIF16, .ops =3D &rsci_port_ops, @@ -470,12 +705,19 @@ struct sci_of_data of_rsci_rzt2h_data =3D { =20 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON =20 +static int __init rsci_rzg3e_early_console_setup(struct earlycon_device *d= evice, + const char *opt) +{ + return scix_early_console_setup(device, &of_rsci_rzg3e_data); +} + static int __init rsci_rzt2h_early_console_setup(struct earlycon_device *d= evice, const char *opt) { return scix_early_console_setup(device, &of_rsci_rzt2h_data); } =20 +OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g047-rsci", rsci_rzg3e_early_conso= le_setup); OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g077-rsci", rsci_rzt2h_early_conso= le_setup); =20 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */ diff --git a/drivers/tty/serial/rsci.h b/drivers/tty/serial/rsci.h index 9547148e8bd1..2aa2ba3973ee 100644 --- a/drivers/tty/serial/rsci.h +++ b/drivers/tty/serial/rsci.h @@ -5,6 +5,7 @@ =20 #include "sh-sci-common.h" =20 +extern struct sci_of_data of_rsci_rzg3e_data; extern struct sci_of_data of_rsci_rzt2h_data; =20 #endif /* __RSCI_H__ */ diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index 677293115f1e..a75d2113752b 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -3329,6 +3329,7 @@ static int sci_init_single(struct platform_device *de= v, sci_port->rx_trigger =3D 64; break; case PORT_SCIFA: + case RSCI_PORT_SCIF32: sci_port->rx_trigger =3D 32; break; case PORT_SCIF: @@ -3662,6 +3663,10 @@ static const struct of_device_id of_sci_match[] __ma= ybe_unused =3D { .data =3D &of_sci_scif_rzv2h, }, #ifdef CONFIG_SERIAL_RSCI + { + .compatible =3D "renesas,r9a09g047-rsci", + .data =3D &of_rsci_rzg3e_data, + }, { .compatible =3D "renesas,r9a09g077-rsci", .data =3D &of_rsci_rzt2h_data, --=20 2.43.0