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charset="utf-8" Follow common kernel idioms for indices derived from configfs attributes and suppress Smatch warnings: epf_ntb_mw1_show() warn: potential spectre issue 'ntb->mws_size' [r] epf_ntb_mw1_store() warn: potential spectre issue 'ntb->mws_size' [w] Also fix the error message for out-of-range MW indices. Signed-off-by: Koichiro Den Reviewed-by: Frank Li --- drivers/pci/endpoint/functions/pci-epf-vntb.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/pci/endpoint/functions/pci-epf-vntb.c b/drivers/pci/en= dpoint/functions/pci-epf-vntb.c index 3ecc5059f92b..6c4c78915970 100644 --- a/drivers/pci/endpoint/functions/pci-epf-vntb.c +++ b/drivers/pci/endpoint/functions/pci-epf-vntb.c @@ -995,17 +995,18 @@ static ssize_t epf_ntb_##_name##_show(struct config_i= tem *item, \ struct config_group *group =3D to_config_group(item); \ struct epf_ntb *ntb =3D to_epf_ntb(group); \ struct device *dev =3D &ntb->epf->dev; \ - int win_no; \ + int win_no, idx; \ \ if (sscanf(#_name, "mw%d", &win_no) !=3D 1) \ return -EINVAL; \ \ if (win_no <=3D 0 || win_no > ntb->num_mws) { \ - dev_err(dev, "Invalid num_nws: %d value\n", ntb->num_mws); \ + dev_err(dev, "MW%d out of range (num_mws=3D%d)\n", \ + win_no, ntb->num_mws); \ return -EINVAL; \ } \ - \ - return sprintf(page, "%lld\n", ntb->mws_size[win_no - 1]); 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Received: from TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:24c::11) by TYCP286MB2050.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:15e::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9366.17; Sat, 29 Nov 2025 16:04:20 +0000 Received: from TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM ([fe80::fb7e:f4ed:a580:9d03]) by TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM ([fe80::fb7e:f4ed:a580:9d03%5]) with mapi id 15.20.9366.012; Sat, 29 Nov 2025 16:04:20 +0000 From: Koichiro Den To: ntb@lists.linux.dev, linux-pci@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Frank.Li@nxp.com Cc: mani@kernel.org, kwilczynski@kernel.org, kishon@kernel.org, bhelgaas@google.com, corbet@lwn.net, vkoul@kernel.org, jdmason@kudzu.us, dave.jiang@intel.com, allenbh@gmail.com, Basavaraj.Natikar@amd.com, Shyam-sundar.S-k@amd.com, kurt.schwemmer@microsemi.com, logang@deltatee.com, jingoohan1@gmail.com, lpieralisi@kernel.org, robh@kernel.org, jbrunet@baylibre.com, fancer.lancer@gmail.com, arnd@arndb.de, pstanner@redhat.com, elfring@users.sourceforge.net Subject: [RFC PATCH v2 02/27] PCI: endpoint: pci-epf-vntb: Add mwN_offset configfs attributes Date: Sun, 30 Nov 2025 01:03:40 +0900 Message-ID: <20251129160405.2568284-3-den@valinux.co.jp> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20251129160405.2568284-1-den@valinux.co.jp> References: <20251129160405.2568284-1-den@valinux.co.jp> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: TYCP286CA0284.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:3c9::15) To TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:24c::11) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TYWP286MB2697:EE_|TYCP286MB2050:EE_ X-MS-Office365-Filtering-Correlation-Id: 903910ca-880a-41d5-acd3-08de2f60f4b4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|366016|1800799024|10070799003; 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charset="utf-8" Introduce new mwN_offset configfs attributes to specify memory window offsets. This enables mapping multiple windows into a single BAR at arbitrary offsets, improving layout flexibility. Signed-off-by: Koichiro Den --- drivers/pci/endpoint/functions/pci-epf-vntb.c | 133 ++++++++++++++++-- 1 file changed, 120 insertions(+), 13 deletions(-) diff --git a/drivers/pci/endpoint/functions/pci-epf-vntb.c b/drivers/pci/en= dpoint/functions/pci-epf-vntb.c index 6c4c78915970..1ff414703566 100644 --- a/drivers/pci/endpoint/functions/pci-epf-vntb.c +++ b/drivers/pci/endpoint/functions/pci-epf-vntb.c @@ -39,6 +39,7 @@ #include #include #include +#include #include #include =20 @@ -111,7 +112,8 @@ struct epf_ntb_ctrl { u64 addr; u64 size; u32 num_mws; - u32 reserved; + u32 mw_offset[MAX_MW]; + u32 mw_size[MAX_MW]; u32 spad_offset; u32 spad_count; u32 db_entry_size; @@ -128,6 +130,7 @@ struct epf_ntb { u32 db_count; u32 spad_count; u64 mws_size[MAX_MW]; + u64 mws_offset[MAX_MW]; atomic64_t db; u32 vbus_number; u16 vntb_pid; @@ -458,6 +461,8 @@ static int epf_ntb_config_spad_bar_alloc(struct epf_ntb= *ntb) =20 ctrl->spad_count =3D spad_count; ctrl->num_mws =3D ntb->num_mws; + memset(ctrl->mw_offset, 0, sizeof(ctrl->mw_offset)); + memset(ctrl->mw_size, 0, sizeof(ctrl->mw_size)); ntb->spad_size =3D spad_size; =20 ctrl->db_entry_size =3D sizeof(u32); @@ -689,15 +694,31 @@ static void epf_ntb_db_bar_clear(struct epf_ntb *ntb) */ static int epf_ntb_mw_bar_init(struct epf_ntb *ntb) { + struct device *dev =3D &ntb->epf->dev; + u64 bar_ends[BAR_5 + 1] =3D { 0 }; + unsigned long bars_used =3D 0; + enum pci_barno barno; + u64 off, size, end; int ret =3D 0; int i; - u64 size; - enum pci_barno barno; - struct device *dev =3D &ntb->epf->dev; =20 for (i =3D 0; i < ntb->num_mws; i++) { - size =3D ntb->mws_size[i]; barno =3D ntb->epf_ntb_bar[BAR_MW1 + i]; + off =3D ntb->mws_offset[i]; + size =3D ntb->mws_size[i]; + end =3D off + size; + if (end > bar_ends[barno]) + bar_ends[barno] =3D end; + bars_used |=3D BIT(barno); + } + + for (barno =3D BAR_0; barno <=3D BAR_5; barno++) { + if (!(bars_used & BIT(barno))) + continue; + if (bar_ends[barno] < SZ_4K) + size =3D SZ_4K; + else + size =3D roundup_pow_of_two(bar_ends[barno]); =20 ntb->epf->bar[barno].barno =3D barno; ntb->epf->bar[barno].size =3D size; @@ -713,8 +734,12 @@ static int epf_ntb_mw_bar_init(struct epf_ntb *ntb) &ntb->epf->bar[barno]); if (ret) { dev_err(dev, "MW set failed\n"); - goto err_alloc_mem; + goto err_set_bar; } + } + + for (i =3D 0; i < ntb->num_mws; i++) { + size =3D ntb->mws_size[i]; =20 /* Allocate EPC outbound memory windows to vpci vntb device */ ntb->vpci_mw_addr[i] =3D pci_epc_mem_alloc_addr(ntb->epf->epc, @@ -723,19 +748,31 @@ static int epf_ntb_mw_bar_init(struct epf_ntb *ntb) if (!ntb->vpci_mw_addr[i]) { ret =3D -ENOMEM; dev_err(dev, "Failed to allocate source address\n"); - goto err_set_bar; + goto err_alloc_mem; } } =20 + for (i =3D 0; i < ntb->num_mws; i++) { + ntb->reg->mw_offset[i] =3D (u32)ntb->mws_offset[i]; + ntb->reg->mw_size[i] =3D (u32)ntb->mws_size[i]; + } + return ret; =20 -err_set_bar: - pci_epc_clear_bar(ntb->epf->epc, - ntb->epf->func_no, - ntb->epf->vfunc_no, - &ntb->epf->bar[barno]); err_alloc_mem: - epf_ntb_mw_bar_clear(ntb, i); + while (--i >=3D 0) + pci_epc_mem_free_addr(ntb->epf->epc, + ntb->vpci_mw_phy[i], + ntb->vpci_mw_addr[i], + ntb->mws_size[i]); +err_set_bar: + while (--barno >=3D BAR_0) + if (bars_used & BIT(barno)) + pci_epc_clear_bar(ntb->epf->epc, + ntb->epf->func_no, + ntb->epf->vfunc_no, + &ntb->epf->bar[barno]); + return ret; } =20 @@ -1039,6 +1076,60 @@ static ssize_t epf_ntb_##_name##_store(struct config= _item *item, \ return len; \ } =20 +#define EPF_NTB_MW_OFF_R(_name) \ +static ssize_t epf_ntb_##_name##_show(struct config_item *item, \ + char *page) \ +{ \ + struct config_group *group =3D to_config_group(item); \ + struct epf_ntb *ntb =3D to_epf_ntb(group); \ + struct device *dev =3D &ntb->epf->dev; \ + int win_no, idx; \ + \ + if (sscanf(#_name, "mw%d_offset", &win_no) !=3D 1) \ + return -EINVAL; \ + \ + idx =3D win_no - 1; \ + if (idx < 0 || idx >=3D ntb->num_mws) { \ + dev_err(dev, "MW%d out of range (num_mws=3D%d)\n", \ + win_no, ntb->num_mws); \ + return -EINVAL; \ + } \ + \ + idx =3D array_index_nospec(idx, ntb->num_mws); \ + return sprintf(page, "%lld\n", ntb->mws_offset[idx]); \ +} + +#define EPF_NTB_MW_OFF_W(_name) \ +static ssize_t epf_ntb_##_name##_store(struct config_item *item, \ + const char *page, size_t len) \ +{ \ + struct config_group *group =3D to_config_group(item); \ + struct epf_ntb *ntb =3D to_epf_ntb(group); \ + struct device *dev =3D &ntb->epf->dev; \ + int win_no, idx; \ + u64 val; \ + int ret; \ + \ + ret =3D kstrtou64(page, 0, &val); \ + if (ret) \ + return ret; \ + \ + if (sscanf(#_name, "mw%d_offset", &win_no) !=3D 1) \ + return -EINVAL; \ + \ + idx =3D win_no - 1; \ + if (idx < 0 || idx >=3D ntb->num_mws) { \ + dev_err(dev, "MW%d out of range (num_mws=3D%d)\n", \ + win_no, ntb->num_mws); \ + return -EINVAL; \ + } \ + \ + idx =3D array_index_nospec(idx, ntb->num_mws); \ + ntb->mws_offset[idx] =3D val; \ + \ + return len; \ +} + #define EPF_NTB_BAR_R(_name, _id) \ static ssize_t epf_ntb_##_name##_show(struct config_item *item, \ char *page) \ @@ -1109,6 +1200,14 @@ EPF_NTB_MW_R(mw3) EPF_NTB_MW_W(mw3) EPF_NTB_MW_R(mw4) EPF_NTB_MW_W(mw4) +EPF_NTB_MW_OFF_R(mw1_offset) +EPF_NTB_MW_OFF_W(mw1_offset) +EPF_NTB_MW_OFF_R(mw2_offset) +EPF_NTB_MW_OFF_W(mw2_offset) +EPF_NTB_MW_OFF_R(mw3_offset) +EPF_NTB_MW_OFF_W(mw3_offset) +EPF_NTB_MW_OFF_R(mw4_offset) +EPF_NTB_MW_OFF_W(mw4_offset) EPF_NTB_BAR_R(ctrl_bar, BAR_CONFIG) EPF_NTB_BAR_W(ctrl_bar, BAR_CONFIG) EPF_NTB_BAR_R(db_bar, BAR_DB) @@ -1129,6 +1228,10 @@ CONFIGFS_ATTR(epf_ntb_, mw1); CONFIGFS_ATTR(epf_ntb_, mw2); CONFIGFS_ATTR(epf_ntb_, mw3); CONFIGFS_ATTR(epf_ntb_, mw4); +CONFIGFS_ATTR(epf_ntb_, mw1_offset); +CONFIGFS_ATTR(epf_ntb_, mw2_offset); +CONFIGFS_ATTR(epf_ntb_, mw3_offset); +CONFIGFS_ATTR(epf_ntb_, mw4_offset); CONFIGFS_ATTR(epf_ntb_, vbus_number); CONFIGFS_ATTR(epf_ntb_, vntb_pid); CONFIGFS_ATTR(epf_ntb_, vntb_vid); @@ -1147,6 +1250,10 @@ static struct configfs_attribute *epf_ntb_attrs[] = =3D { &epf_ntb_attr_mw2, &epf_ntb_attr_mw3, &epf_ntb_attr_mw4, + &epf_ntb_attr_mw1_offset, + &epf_ntb_attr_mw2_offset, + &epf_ntb_attr_mw3_offset, + &epf_ntb_attr_mw4_offset, &epf_ntb_attr_vbus_number, &epf_ntb_attr_vntb_pid, &epf_ntb_attr_vntb_vid, --=20 2.48.1 From nobody Mon Dec 1 22:07:44 2025 Received: from OS0P286CU010.outbound.protection.outlook.com (mail-japanwestazon11011070.outbound.protection.outlook.com [40.107.74.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12BA226E704; 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Received: from TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:24c::11) by TYCP286MB2050.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:15e::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9366.17; Sat, 29 Nov 2025 16:04:21 +0000 Received: from TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM ([fe80::fb7e:f4ed:a580:9d03]) by TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM ([fe80::fb7e:f4ed:a580:9d03%5]) with mapi id 15.20.9366.012; Sat, 29 Nov 2025 16:04:21 +0000 From: Koichiro Den To: ntb@lists.linux.dev, linux-pci@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Frank.Li@nxp.com Cc: mani@kernel.org, kwilczynski@kernel.org, kishon@kernel.org, bhelgaas@google.com, corbet@lwn.net, vkoul@kernel.org, jdmason@kudzu.us, dave.jiang@intel.com, allenbh@gmail.com, Basavaraj.Natikar@amd.com, Shyam-sundar.S-k@amd.com, kurt.schwemmer@microsemi.com, logang@deltatee.com, jingoohan1@gmail.com, lpieralisi@kernel.org, robh@kernel.org, jbrunet@baylibre.com, fancer.lancer@gmail.com, arnd@arndb.de, pstanner@redhat.com, elfring@users.sourceforge.net Subject: [RFC PATCH v2 03/27] NTB: epf: Handle mwN_offset for inbound MW regions Date: Sun, 30 Nov 2025 01:03:41 +0900 Message-ID: <20251129160405.2568284-4-den@valinux.co.jp> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20251129160405.2568284-1-den@valinux.co.jp> References: <20251129160405.2568284-1-den@valinux.co.jp> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: TYCPR01CA0085.jpnprd01.prod.outlook.com (2603:1096:405:3::25) To TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:24c::11) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TYWP286MB2697:EE_|TYCP286MB2050:EE_ X-MS-Office365-Filtering-Correlation-Id: 0d45160f-39d8-47fc-822d-08de2f60f56c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|366016|1800799024|10070799003; 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charset="utf-8" Add and use new fields in the common control register to convey both offset and size for each memory window (MW), so that it can correctly handle flexible MW layouts and support partial BAR mappings. Signed-off-by: Koichiro Den --- drivers/ntb/hw/epf/ntb_hw_epf.c | 27 ++++++++++++++++----------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/drivers/ntb/hw/epf/ntb_hw_epf.c b/drivers/ntb/hw/epf/ntb_hw_ep= f.c index d3ecf25a5162..91d3f8e05807 100644 --- a/drivers/ntb/hw/epf/ntb_hw_epf.c +++ b/drivers/ntb/hw/epf/ntb_hw_epf.c @@ -36,12 +36,13 @@ #define NTB_EPF_LOWER_SIZE 0x18 #define NTB_EPF_UPPER_SIZE 0x1C #define NTB_EPF_MW_COUNT 0x20 -#define NTB_EPF_MW1_OFFSET 0x24 -#define NTB_EPF_SPAD_OFFSET 0x28 -#define NTB_EPF_SPAD_COUNT 0x2C -#define NTB_EPF_DB_ENTRY_SIZE 0x30 -#define NTB_EPF_DB_DATA(n) (0x34 + (n) * 4) -#define NTB_EPF_DB_OFFSET(n) (0xB4 + (n) * 4) +#define NTB_EPF_MW_OFFSET(n) (0x24 + (n) * 4) +#define NTB_EPF_MW_SIZE(n) (0x34 + (n) * 4) +#define NTB_EPF_SPAD_OFFSET 0x44 +#define NTB_EPF_SPAD_COUNT 0x48 +#define NTB_EPF_DB_ENTRY_SIZE 0x4C +#define NTB_EPF_DB_DATA(n) (0x50 + (n) * 4) +#define NTB_EPF_DB_OFFSET(n) (0xD0 + (n) * 4) =20 #define NTB_EPF_MIN_DB_COUNT 3 #define NTB_EPF_MAX_DB_COUNT 31 @@ -451,11 +452,12 @@ static int ntb_epf_peer_mw_get_addr(struct ntb_dev *n= tb, int idx, phys_addr_t *base, resource_size_t *size) { struct ntb_epf_dev *ndev =3D ntb_ndev(ntb); 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charset="utf-8" Add new EPC ops map_inbound() and unmap_inbound() for mapping a subrange of a BAR into CPU space. These will be implemented by controller drivers such as DesignWare. Signed-off-by: Koichiro Den --- drivers/pci/endpoint/pci-epc-core.c | 44 +++++++++++++++++++++++++++++ include/linux/pci-epc.h | 11 ++++++++ 2 files changed, 55 insertions(+) diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci= -epc-core.c index ca7f19cc973a..825109e54ba9 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -444,6 +444,50 @@ int pci_epc_map_addr(struct pci_epc *epc, u8 func_no, = u8 vfunc_no, } EXPORT_SYMBOL_GPL(pci_epc_map_addr); =20 +/** + * pci_epc_map_inbound() - map a BAR subrange to the local CPU address + * @epc: the EPC device on which BAR has to be configured + * @func_no: the physical endpoint function number in the EPC device + * @vfunc_no: the virtual endpoint function number in the physical function + * @epf_bar: the struct epf_bar that contains the BAR information + * @offset: byte offset from the BAR base selected by the host + * + * Invoke to configure the BAR of the endpoint device and map a subrange + * selected by @offset to a CPU address. + * + * Returns 0 on success, -EOPNOTSUPP if unsupported, or a negative errno. + */ +int pci_epc_map_inbound(struct pci_epc *epc, u8 func_no, u8 vfunc_no, + struct pci_epf_bar *epf_bar, u64 offset) +{ + if (!epc || !epc->ops || !epc->ops->map_inbound) + return -EOPNOTSUPP; + + return epc->ops->map_inbound(epc, func_no, vfunc_no, epf_bar, offset); +} +EXPORT_SYMBOL_GPL(pci_epc_map_inbound); + +/** + * pci_epc_unmap_inbound() - unmap a previously mapped BAR subrange + * @epc: the EPC device on which the inbound mapping was programmed + * @func_no: the physical endpoint function number in the EPC device + * @vfunc_no: the virtual endpoint function number in the physical function + * @epf_bar: the struct epf_bar used when the mapping was created + * @offset: byte offset from the BAR base that was mapped + * + * Invoke to remove a BAR subrange mapping created by pci_epc_map_inbound(= ). + * If the controller has no support, this call is a no-op. + */ +void pci_epc_unmap_inbound(struct pci_epc *epc, u8 func_no, u8 vfunc_no, + struct pci_epf_bar *epf_bar, u64 offset) +{ + if (!epc || !epc->ops || !epc->ops->unmap_inbound) + return; + + epc->ops->unmap_inbound(epc, func_no, vfunc_no, epf_bar, offset); +} +EXPORT_SYMBOL_GPL(pci_epc_unmap_inbound); + /** * pci_epc_mem_map() - allocate and map a PCI address to a CPU address * @epc: the EPC device on which the CPU address is to be allocated and ma= pped diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index 4286bfdbfdfa..a5fb91cc2982 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -71,6 +71,8 @@ struct pci_epc_map { * region * @map_addr: ops to map CPU address to PCI address * @unmap_addr: ops to unmap CPU address and PCI address + * @map_inbound: ops to map a subrange inside a BAR to CPU address. + * @unmap_inbound: ops to unmap a subrange inside a BAR and CPU address. * @set_msi: ops to set the requested number of MSI interrupts in the MSI * capability register * @get_msi: ops to get the number of MSI interrupts allocated by the RC f= rom @@ -99,6 +101,10 @@ struct pci_epc_ops { phys_addr_t addr, u64 pci_addr, size_t size); void (*unmap_addr)(struct pci_epc *epc, u8 func_no, u8 vfunc_no, phys_addr_t addr); + int (*map_inbound)(struct pci_epc *epc, u8 func_no, u8 vfunc_no, + struct pci_epf_bar *epf_bar, u64 offset); + void (*unmap_inbound)(struct pci_epc *epc, u8 func_no, u8 vfunc_no, + struct pci_epf_bar *epf_bar, u64 offset); int (*set_msi)(struct pci_epc *epc, u8 func_no, u8 vfunc_no, u8 nr_irqs); int (*get_msi)(struct pci_epc *epc, u8 func_no, u8 vfunc_no); @@ -286,6 +292,11 @@ int pci_epc_map_addr(struct pci_epc *epc, u8 func_no, = u8 vfunc_no, u64 pci_addr, size_t size); void pci_epc_unmap_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no, phys_addr_t phys_addr); + +int pci_epc_map_inbound(struct pci_epc *epc, u8 func_no, u8 vfunc_no, + struct pci_epf_bar *epf_bar, u64 offset); +void pci_epc_unmap_inbound(struct pci_epc *epc, u8 func_no, u8 vfunc_no, + struct pci_epf_bar *epf_bar, u64 offset); int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no, u8 nr_ir= qs); int pci_epc_get_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no); 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b=Od17OFzfua3VsBLzDwEuo8/gqxdAhBIZpJTWYl04iKjCCdrTfoH+LG0oDviok5bz+dfT2uA0v8Oni45grK9DEcv/o0z0J80oZF0uWwiLIjErzRG40lfTcOhorb48sjoiA5nF+NPhlZvssp34AwlPGJoe4eEDNMnC/XSfN2j3g20= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=valinux.co.jp; Received: from TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:24c::11) by TYCP286MB2050.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:15e::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9366.17; Sat, 29 Nov 2025 16:04:23 +0000 Received: from TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM ([fe80::fb7e:f4ed:a580:9d03]) by TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM ([fe80::fb7e:f4ed:a580:9d03%5]) with mapi id 15.20.9366.012; Sat, 29 Nov 2025 16:04:23 +0000 From: Koichiro Den To: ntb@lists.linux.dev, linux-pci@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Frank.Li@nxp.com Cc: mani@kernel.org, kwilczynski@kernel.org, kishon@kernel.org, bhelgaas@google.com, corbet@lwn.net, vkoul@kernel.org, jdmason@kudzu.us, dave.jiang@intel.com, allenbh@gmail.com, Basavaraj.Natikar@amd.com, Shyam-sundar.S-k@amd.com, kurt.schwemmer@microsemi.com, logang@deltatee.com, jingoohan1@gmail.com, lpieralisi@kernel.org, robh@kernel.org, jbrunet@baylibre.com, fancer.lancer@gmail.com, arnd@arndb.de, pstanner@redhat.com, elfring@users.sourceforge.net Subject: [RFC PATCH v2 05/27] PCI: dwc: ep: Implement EPC inbound mapping support Date: Sun, 30 Nov 2025 01:03:43 +0900 Message-ID: <20251129160405.2568284-6-den@valinux.co.jp> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20251129160405.2568284-1-den@valinux.co.jp> References: <20251129160405.2568284-1-den@valinux.co.jp> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: TYCP286CA0022.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:263::8) To TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:24c::11) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TYWP286MB2697:EE_|TYCP286MB2050:EE_ X-MS-Office365-Filtering-Correlation-Id: 921972cf-8830-4849-f0a3-08de2f60f67c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|366016|1800799024|10070799003; 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charset="utf-8" Implement map_inbound() and unmap_inbound() for DesignWare endpoint controllers (Address Match mode). Allows subrange mappings within a BAR, enabling advanced endpoint functions such as NTB with offset-based windows. Signed-off-by: Koichiro Den --- .../pci/controller/dwc/pcie-designware-ep.c | 239 +++++++++++++++--- drivers/pci/controller/dwc/pcie-designware.h | 2 + 2 files changed, 212 insertions(+), 29 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/= controller/dwc/pcie-designware-ep.c index 19571ac2b961..3780a9bd6f79 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -8,13 +8,25 @@ =20 #include #include +#include #include +#include #include +#include =20 #include "pcie-designware.h" #include #include =20 +struct dw_pcie_ib_map { + struct list_head node; + enum pci_barno bar; + u64 pci_addr; /* BAR base + offset at map time */ + phys_addr_t cpu_addr; /* EP local phys */ + u64 size; + u32 index; /* iATU inbound window index */ +}; + /** * dw_pcie_ep_get_func_from_ep - Get the struct dw_pcie_ep_func correspond= ing to * the endpoint function @@ -205,6 +217,7 @@ static void dw_pcie_ep_clear_bar(struct pci_epc *epc, u= 8 func_no, u8 vfunc_no, struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); enum pci_barno bar =3D epf_bar->barno; u32 atu_index =3D ep->bar_to_atu[bar] - 1; + struct dw_pcie_ib_map *m, *tmp; =20 if (!ep->bar_to_atu[bar]) return; @@ -215,6 +228,16 @@ static void dw_pcie_ep_clear_bar(struct pci_epc *epc, = u8 func_no, u8 vfunc_no, clear_bit(atu_index, ep->ib_window_map); ep->epf_bar[bar] =3D NULL; ep->bar_to_atu[bar] =3D 0; + + guard(spinlock_irqsave)(&ep->ib_map_lock); + list_for_each_entry_safe(m, tmp, &ep->ib_map_list, node) { + if (m->bar !=3D bar) + continue; + dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_IB, m->index); + clear_bit(m->index, ep->ib_window_map); + list_del(&m->node); + kfree(m); + } } =20 static unsigned int dw_pcie_ep_get_rebar_offset(struct dw_pcie *pci, @@ -336,14 +359,46 @@ static enum pci_epc_bar_type dw_pcie_ep_get_bar_type(= struct dw_pcie_ep *ep, return epc_features->bar[bar].type; } =20 +static int dw_pcie_ep_set_bar_init(struct pci_epc *epc, u8 func_no, u8 vfu= nc_no, + struct pci_epf_bar *epf_bar) +{ + struct dw_pcie_ep *ep =3D epc_get_drvdata(epc); + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); + enum pci_barno bar =3D epf_bar->barno; + enum pci_epc_bar_type bar_type; + int ret; + + bar_type =3D dw_pcie_ep_get_bar_type(ep, bar); + switch (bar_type) { + case BAR_FIXED: + /* + * There is no need to write a BAR mask for a fixed BAR (except + * to write 1 to the LSB of the BAR mask register, to enable the + * BAR). Write the BAR mask regardless. (The fixed bits in the + * BAR mask register will be read-only anyway.) + */ + fallthrough; + case BAR_PROGRAMMABLE: + ret =3D dw_pcie_ep_set_bar_programmable(ep, func_no, epf_bar); + break; + case BAR_RESIZABLE: + ret =3D dw_pcie_ep_set_bar_resizable(ep, func_no, epf_bar); + break; + default: + ret =3D -EINVAL; + dev_err(pci->dev, "Invalid BAR type\n"); + break; + } + + return ret; +} + static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, struct pci_epf_bar *epf_bar) { struct dw_pcie_ep *ep =3D epc_get_drvdata(epc); - struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); enum pci_barno bar =3D epf_bar->barno; size_t size =3D epf_bar->size; - enum pci_epc_bar_type bar_type; int flags =3D epf_bar->flags; int ret, type; =20 @@ -374,35 +429,12 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8= func_no, u8 vfunc_no, * When dynamically changing a BAR, skip writing the BAR reg, as * that would clear the BAR's PCI address assigned by the host. */ - goto config_atu; - } - - bar_type =3D dw_pcie_ep_get_bar_type(ep, bar); - switch (bar_type) { - case BAR_FIXED: - /* - * There is no need to write a BAR mask for a fixed BAR (except - * to write 1 to the LSB of the BAR mask register, to enable the - * BAR). Write the BAR mask regardless. (The fixed bits in the - * BAR mask register will be read-only anyway.) - */ - fallthrough; - case BAR_PROGRAMMABLE: - ret =3D dw_pcie_ep_set_bar_programmable(ep, func_no, epf_bar); - break; - case BAR_RESIZABLE: - ret =3D dw_pcie_ep_set_bar_resizable(ep, func_no, epf_bar); - break; - default: - ret =3D -EINVAL; - dev_err(pci->dev, "Invalid BAR type\n"); - break; + } else { + ret =3D dw_pcie_ep_set_bar_init(epc, func_no, vfunc_no, epf_bar); + if (ret) + return ret; } =20 - if (ret) - return ret; - -config_atu: if (!(flags & PCI_BASE_ADDRESS_SPACE)) type =3D PCIE_ATU_TYPE_MEM; else @@ -488,6 +520,151 @@ static int dw_pcie_ep_map_addr(struct pci_epc *epc, u= 8 func_no, u8 vfunc_no, return 0; } =20 +static inline u64 dw_pcie_ep_read_bar_assigned(struct dw_pcie_ep *ep, u8 f= unc_no, + enum pci_barno bar, bool is_io, + bool is_64) +{ + u32 reg =3D PCI_BASE_ADDRESS_0 + 4 * bar; + u32 lo, hi =3D 0; + u64 base; + + lo =3D dw_pcie_ep_readl_dbi(ep, func_no, reg); + if (is_io) + base =3D lo & PCI_BASE_ADDRESS_IO_MASK; + else { + base =3D lo & PCI_BASE_ADDRESS_MEM_MASK; + if (is_64) { + hi =3D dw_pcie_ep_readl_dbi(ep, func_no, reg + 4); + base |=3D ((u64)hi) << 32; + } + } + return base; +} + +static int dw_pcie_ep_map_inbound(struct pci_epc *epc, u8 func_no, u8 vfun= c_no, + struct pci_epf_bar *epf_bar, u64 offset) +{ + struct dw_pcie_ep *ep =3D epc_get_drvdata(epc); + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); + enum pci_barno bar =3D epf_bar->barno; + size_t size =3D epf_bar->size; + int flags =3D epf_bar->flags; + struct dw_pcie_ib_map *m; + u64 base, pci_addr; + int ret, type, win; + + /* + * DWC does not allow BAR pairs to overlap, e.g. you cannot combine BARs + * 1 and 2 to form a 64-bit BAR. + */ + if ((flags & PCI_BASE_ADDRESS_MEM_TYPE_64) && (bar & 1)) + return -EINVAL; + + /* + * Certain EPF drivers dynamically change the physical address of a BAR + * (i.e. they call set_bar() twice, without ever calling clear_bar(), as + * calling clear_bar() would clear the BAR's PCI address assigned by the + * host). + */ + if (epf_bar->phys_addr && ep->epf_bar[bar]) { + /* + * We can only dynamically add a whole or partial mapping if the + * BAR flags do not differ from the existing configuration. + */ + if (ep->epf_bar[bar]->barno !=3D bar || + ep->epf_bar[bar]->flags !=3D flags) + return -EINVAL; + + /* + * When dynamically changing a BAR, skip writing the BAR reg, as + * that would clear the BAR's PCI address assigned by the host. + */ + } + + /* + * Skip programming the inbound translation if phys_addr is 0. + * In this case, the caller only intends to initialize the BAR. + */ + if (!epf_bar->phys_addr) { + ret =3D dw_pcie_ep_set_bar_init(epc, func_no, vfunc_no, epf_bar); + ep->epf_bar[bar] =3D epf_bar; + return ret; + } + + base =3D dw_pcie_ep_read_bar_assigned(ep, func_no, bar, + flags & PCI_BASE_ADDRESS_SPACE, + flags & PCI_BASE_ADDRESS_MEM_TYPE_64); + if (!(flags & PCI_BASE_ADDRESS_SPACE)) + type =3D PCIE_ATU_TYPE_MEM; + else + type =3D PCIE_ATU_TYPE_IO; + pci_addr =3D base + offset; + + /* Allocate an inbound iATU window */ + win =3D find_first_zero_bit(ep->ib_window_map, pci->num_ib_windows); + if (win >=3D pci->num_ib_windows) + return -ENOSPC; + + /* Program address-match inbound iATU */ + ret =3D dw_pcie_prog_inbound_atu(pci, win, type, + epf_bar->phys_addr - pci->parent_bus_offset, + pci_addr, size); + if (ret) + return ret; + + m =3D kzalloc(sizeof(*m), GFP_KERNEL); + if (!m) { + dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_IB, win); + return -ENOMEM; + } + m->bar =3D bar; + m->pci_addr =3D pci_addr; + m->cpu_addr =3D epf_bar->phys_addr; + m->size =3D size; + m->index =3D win; + + guard(spinlock_irqsave)(&ep->ib_map_lock); + set_bit(win, ep->ib_window_map); + list_add(&m->node, &ep->ib_map_list); + + return 0; +} + +static void dw_pcie_ep_unmap_inbound(struct pci_epc *epc, u8 func_no, u8 v= func_no, + struct pci_epf_bar *epf_bar, u64 offset) +{ + struct dw_pcie_ep *ep =3D epc_get_drvdata(epc); + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); + enum pci_barno bar =3D epf_bar->barno; + struct dw_pcie_ib_map *m, *tmp; + size_t size =3D epf_bar->size; + int flags =3D epf_bar->flags; + u64 match_pci =3D 0; + u64 base; + + /* If BAR base isn't assigned, there can't be any programmed sub-window */ + base =3D dw_pcie_ep_read_bar_assigned(ep, func_no, bar, + flags & PCI_BASE_ADDRESS_SPACE, + flags & PCI_BASE_ADDRESS_MEM_TYPE_64); + if (base) + match_pci =3D base + offset; + + guard(spinlock_irqsave)(&ep->ib_map_lock); + list_for_each_entry_safe(m, tmp, &ep->ib_map_list, node) { + if (m->bar !=3D bar) + continue; + if (match_pci && m->pci_addr !=3D match_pci) + continue; + if (size && m->size !=3D size) + /* Partial unmap is unsupported for now */ + continue; + dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_IB, m->index); + clear_bit(m->index, ep->ib_window_map); + list_del(&m->node); + kfree(m); + } +} + static int dw_pcie_ep_get_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no) { struct dw_pcie_ep *ep =3D epc_get_drvdata(epc); @@ -630,6 +807,8 @@ static const struct pci_epc_ops epc_ops =3D { .align_addr =3D dw_pcie_ep_align_addr, .map_addr =3D dw_pcie_ep_map_addr, .unmap_addr =3D dw_pcie_ep_unmap_addr, + .map_inbound =3D dw_pcie_ep_map_inbound, + .unmap_inbound =3D dw_pcie_ep_unmap_inbound, .set_msi =3D dw_pcie_ep_set_msi, .get_msi =3D dw_pcie_ep_get_msi, .set_msix =3D dw_pcie_ep_set_msix, @@ -1087,6 +1266,8 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) struct device *dev =3D pci->dev; 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Received: from TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:24c::11) by TYCP286MB2050.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:15e::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9366.17; Sat, 29 Nov 2025 16:04:24 +0000 Received: from TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM ([fe80::fb7e:f4ed:a580:9d03]) by TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM ([fe80::fb7e:f4ed:a580:9d03%5]) with mapi id 15.20.9366.012; Sat, 29 Nov 2025 16:04:24 +0000 From: Koichiro Den To: ntb@lists.linux.dev, linux-pci@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Frank.Li@nxp.com Cc: mani@kernel.org, kwilczynski@kernel.org, kishon@kernel.org, bhelgaas@google.com, corbet@lwn.net, vkoul@kernel.org, jdmason@kudzu.us, dave.jiang@intel.com, allenbh@gmail.com, Basavaraj.Natikar@amd.com, Shyam-sundar.S-k@amd.com, kurt.schwemmer@microsemi.com, logang@deltatee.com, jingoohan1@gmail.com, lpieralisi@kernel.org, robh@kernel.org, jbrunet@baylibre.com, fancer.lancer@gmail.com, arnd@arndb.de, pstanner@redhat.com, elfring@users.sourceforge.net Subject: [RFC PATCH v2 06/27] PCI: endpoint: pci-epf-vntb: Use pci_epc_map_inbound() for MW mapping Date: Sun, 30 Nov 2025 01:03:44 +0900 Message-ID: <20251129160405.2568284-7-den@valinux.co.jp> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20251129160405.2568284-1-den@valinux.co.jp> References: <20251129160405.2568284-1-den@valinux.co.jp> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: TYWPR01CA0004.jpnprd01.prod.outlook.com (2603:1096:400:a9::9) To TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:24c::11) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TYWP286MB2697:EE_|TYCP286MB2050:EE_ X-MS-Office365-Filtering-Correlation-Id: cb0e7384-61f0-489f-7a38-08de2f60f711 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|366016|1800799024|10070799003; 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charset="utf-8" Switch MW setup to use pci_epc_map_inbound() when supported. This allows mapping portions of a BAR rather than the entire region, supporting partial BAR usage on capable controllers. Signed-off-by: Koichiro Den Reviewed-by: Frank Li --- drivers/pci/endpoint/functions/pci-epf-vntb.c | 21 ++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/drivers/pci/endpoint/functions/pci-epf-vntb.c b/drivers/pci/en= dpoint/functions/pci-epf-vntb.c index 1ff414703566..42e57721dcb4 100644 --- a/drivers/pci/endpoint/functions/pci-epf-vntb.c +++ b/drivers/pci/endpoint/functions/pci-epf-vntb.c @@ -728,10 +728,15 @@ static int epf_ntb_mw_bar_init(struct epf_ntb *ntb) PCI_BASE_ADDRESS_MEM_TYPE_64 : PCI_BASE_ADDRESS_MEM_TYPE_32; =20 - ret =3D pci_epc_set_bar(ntb->epf->epc, - ntb->epf->func_no, - ntb->epf->vfunc_no, - &ntb->epf->bar[barno]); + ret =3D pci_epc_map_inbound(ntb->epf->epc, + ntb->epf->func_no, + ntb->epf->vfunc_no, + &ntb->epf->bar[barno], 0); + if (ret =3D=3D -EOPNOTSUPP) + ret =3D pci_epc_set_bar(ntb->epf->epc, + ntb->epf->func_no, + ntb->epf->vfunc_no, + &ntb->epf->bar[barno]); if (ret) { dev_err(dev, "MW set failed\n"); goto err_set_bar; @@ -1385,17 +1390,23 @@ static int vntb_epf_mw_set_trans(struct ntb_dev *nd= ev, int pidx, int idx, struct epf_ntb *ntb =3D ntb_ndev(ndev); struct pci_epf_bar *epf_bar; enum pci_barno barno; + struct pci_epc *epc; int ret; struct device *dev; =20 + epc =3D ntb->epf->epc; dev =3D &ntb->ntb.dev; barno =3D ntb->epf_ntb_bar[BAR_MW1 + idx]; + epf_bar =3D &ntb->epf->bar[barno]; epf_bar->phys_addr =3D addr; epf_bar->barno =3D barno; epf_bar->size =3D size; =20 - ret =3D pci_epc_set_bar(ntb->epf->epc, 0, 0, epf_bar); + ret =3D pci_epc_map_inbound(epc, 0, 0, epf_bar, 0); + if (ret =3D=3D -EOPNOTSUPP) + ret =3D pci_epc_set_bar(epc, 0, 0, epf_bar); + if (ret) { dev_err(dev, "failure set mw trans\n"); return ret; --=20 2.48.1 From nobody Mon Dec 1 22:07:44 2025 Received: from TYVP286CU001.outbound.protection.outlook.com (mail-japaneastazon11011006.outbound.protection.outlook.com [52.101.125.6]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F169330FF08; Sat, 29 Nov 2025 16:04:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Received: from TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:24c::11) by TYCP286MB2050.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:15e::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9366.17; Sat, 29 Nov 2025 16:04:25 +0000 Received: from TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM ([fe80::fb7e:f4ed:a580:9d03]) by TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM ([fe80::fb7e:f4ed:a580:9d03%5]) with mapi id 15.20.9366.012; Sat, 29 Nov 2025 16:04:25 +0000 From: Koichiro Den To: ntb@lists.linux.dev, linux-pci@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Frank.Li@nxp.com Cc: mani@kernel.org, kwilczynski@kernel.org, kishon@kernel.org, bhelgaas@google.com, corbet@lwn.net, vkoul@kernel.org, jdmason@kudzu.us, dave.jiang@intel.com, allenbh@gmail.com, Basavaraj.Natikar@amd.com, Shyam-sundar.S-k@amd.com, kurt.schwemmer@microsemi.com, logang@deltatee.com, jingoohan1@gmail.com, lpieralisi@kernel.org, robh@kernel.org, jbrunet@baylibre.com, fancer.lancer@gmail.com, arnd@arndb.de, pstanner@redhat.com, elfring@users.sourceforge.net Subject: [RFC PATCH v2 07/27] NTB: Add offset parameter to MW translation APIs Date: Sun, 30 Nov 2025 01:03:45 +0900 Message-ID: <20251129160405.2568284-8-den@valinux.co.jp> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20251129160405.2568284-1-den@valinux.co.jp> References: <20251129160405.2568284-1-den@valinux.co.jp> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: TYCP286CA0055.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:2b5::10) To TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:24c::11) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TYWP286MB2697:EE_|TYCP286MB2050:EE_ X-MS-Office365-Filtering-Correlation-Id: 228c3c99-34b5-44e0-89e6-08de2f60f7cd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|366016|1800799024|10070799003; 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charset="utf-8" Extend ntb_mw_set_trans() and ntb_mw_get_align() with an offset argument. This supports subrange mapping inside a BAR for platforms that require offset-based translations. Signed-off-by: Koichiro Den --- drivers/ntb/hw/amd/ntb_hw_amd.c | 6 ++++-- drivers/ntb/hw/epf/ntb_hw_epf.c | 6 ++++-- drivers/ntb/hw/idt/ntb_hw_idt.c | 3 ++- drivers/ntb/hw/intel/ntb_hw_gen1.c | 6 ++++-- drivers/ntb/hw/intel/ntb_hw_gen1.h | 2 +- drivers/ntb/hw/intel/ntb_hw_gen3.c | 3 ++- drivers/ntb/hw/intel/ntb_hw_gen4.c | 6 ++++-- drivers/ntb/hw/mscc/ntb_hw_switchtec.c | 6 ++++-- drivers/ntb/msi.c | 6 +++--- drivers/ntb/ntb_transport.c | 4 ++-- drivers/ntb/test/ntb_perf.c | 4 ++-- drivers/ntb/test/ntb_tool.c | 6 +++--- drivers/pci/endpoint/functions/pci-epf-vntb.c | 7 ++++--- include/linux/ntb.h | 18 +++++++++++------- 14 files changed, 50 insertions(+), 33 deletions(-) diff --git a/drivers/ntb/hw/amd/ntb_hw_amd.c b/drivers/ntb/hw/amd/ntb_hw_am= d.c index 1a163596ddf5..c0137df413c4 100644 --- a/drivers/ntb/hw/amd/ntb_hw_amd.c +++ b/drivers/ntb/hw/amd/ntb_hw_amd.c @@ -92,7 +92,8 @@ static int amd_ntb_mw_count(struct ntb_dev *ntb, int pidx) static int amd_ntb_mw_get_align(struct ntb_dev *ntb, int pidx, int idx, resource_size_t *addr_align, resource_size_t *size_align, - resource_size_t *size_max) + resource_size_t *size_max, + resource_size_t *offset) { struct amd_ntb_dev *ndev =3D ntb_ndev(ntb); int bar; @@ -117,7 +118,8 @@ static int amd_ntb_mw_get_align(struct ntb_dev *ntb, in= t pidx, int idx, } =20 static int amd_ntb_mw_set_trans(struct ntb_dev *ntb, int pidx, int idx, - dma_addr_t addr, resource_size_t size) + dma_addr_t addr, resource_size_t size, + resource_size_t offset) { struct amd_ntb_dev *ndev =3D ntb_ndev(ntb); unsigned long xlat_reg, limit_reg =3D 0; diff --git a/drivers/ntb/hw/epf/ntb_hw_epf.c b/drivers/ntb/hw/epf/ntb_hw_ep= f.c index 91d3f8e05807..a3ec411bfe49 100644 --- a/drivers/ntb/hw/epf/ntb_hw_epf.c +++ b/drivers/ntb/hw/epf/ntb_hw_epf.c @@ -164,7 +164,8 @@ static int ntb_epf_mw_count(struct ntb_dev *ntb, int pi= dx) static int ntb_epf_mw_get_align(struct ntb_dev *ntb, int pidx, int idx, resource_size_t *addr_align, resource_size_t *size_align, - resource_size_t *size_max) + resource_size_t *size_max, + resource_size_t *offset) { struct ntb_epf_dev *ndev =3D ntb_ndev(ntb); struct device *dev =3D ndev->dev; @@ -402,7 +403,8 @@ static int ntb_epf_db_set_mask(struct ntb_dev *ntb, u64= db_bits) } =20 static int ntb_epf_mw_set_trans(struct ntb_dev *ntb, int pidx, int idx, - dma_addr_t addr, resource_size_t size) + dma_addr_t addr, resource_size_t size, + resource_size_t offset) { struct ntb_epf_dev *ndev =3D ntb_ndev(ntb); struct device *dev =3D ndev->dev; diff --git a/drivers/ntb/hw/idt/ntb_hw_idt.c b/drivers/ntb/hw/idt/ntb_hw_id= t.c index f27df8d7f3b9..8c2cf149b99b 100644 --- a/drivers/ntb/hw/idt/ntb_hw_idt.c +++ b/drivers/ntb/hw/idt/ntb_hw_idt.c @@ -1190,7 +1190,8 @@ static int idt_ntb_mw_count(struct ntb_dev *ntb, int = pidx) static int idt_ntb_mw_get_align(struct ntb_dev *ntb, int pidx, int widx, resource_size_t *addr_align, resource_size_t *size_align, - resource_size_t *size_max) + resource_size_t *size_max, + resource_size_t *offset) { struct idt_ntb_dev *ndev =3D to_ndev_ntb(ntb); struct idt_ntb_peer *peer; diff --git a/drivers/ntb/hw/intel/ntb_hw_gen1.c b/drivers/ntb/hw/intel/ntb_= hw_gen1.c index 079b8cd79785..6cbbd6cdf4c0 100644 --- a/drivers/ntb/hw/intel/ntb_hw_gen1.c +++ b/drivers/ntb/hw/intel/ntb_hw_gen1.c @@ -804,7 +804,8 @@ int intel_ntb_mw_count(struct ntb_dev *ntb, int pidx) int intel_ntb_mw_get_align(struct ntb_dev *ntb, int pidx, int idx, resource_size_t *addr_align, resource_size_t *size_align, - resource_size_t *size_max) + resource_size_t *size_max, + resource_size_t *offset) { struct intel_ntb_dev *ndev =3D ntb_ndev(ntb); resource_size_t bar_size, mw_size; @@ -840,7 +841,8 @@ int intel_ntb_mw_get_align(struct ntb_dev *ntb, int pid= x, int idx, } =20 static int intel_ntb_mw_set_trans(struct ntb_dev *ntb, int pidx, int idx, - dma_addr_t addr, resource_size_t size) + dma_addr_t addr, resource_size_t size, + resource_size_t offset) { struct intel_ntb_dev *ndev =3D ntb_ndev(ntb); unsigned long base_reg, xlat_reg, limit_reg; diff --git a/drivers/ntb/hw/intel/ntb_hw_gen1.h b/drivers/ntb/hw/intel/ntb_= hw_gen1.h index 344249fc18d1..f9ebd2780b7f 100644 --- a/drivers/ntb/hw/intel/ntb_hw_gen1.h +++ b/drivers/ntb/hw/intel/ntb_hw_gen1.h @@ -159,7 +159,7 @@ int ndev_mw_to_bar(struct intel_ntb_dev *ndev, int idx); int intel_ntb_mw_count(struct ntb_dev *ntb, int pidx); int intel_ntb_mw_get_align(struct ntb_dev *ntb, int pidx, int idx, resource_size_t *addr_align, resource_size_t *size_align, - resource_size_t *size_max); + resource_size_t *size_max, resource_size_t *offset); int intel_ntb_peer_mw_count(struct ntb_dev *ntb); int intel_ntb_peer_mw_get_addr(struct ntb_dev *ntb, int idx, phys_addr_t *base, resource_size_t *size); diff --git a/drivers/ntb/hw/intel/ntb_hw_gen3.c b/drivers/ntb/hw/intel/ntb_= hw_gen3.c index a5aa96a31f4a..98722032ca5d 100644 --- a/drivers/ntb/hw/intel/ntb_hw_gen3.c +++ b/drivers/ntb/hw/intel/ntb_hw_gen3.c @@ -444,7 +444,8 @@ int intel_ntb3_link_enable(struct ntb_dev *ntb, enum nt= b_speed max_speed, return 0; } static int intel_ntb3_mw_set_trans(struct ntb_dev *ntb, int pidx, int idx, - dma_addr_t addr, resource_size_t size) + dma_addr_t addr, resource_size_t size, + resource_size_t offset) { struct intel_ntb_dev *ndev =3D ntb_ndev(ntb); unsigned long xlat_reg, limit_reg; diff --git a/drivers/ntb/hw/intel/ntb_hw_gen4.c b/drivers/ntb/hw/intel/ntb_= hw_gen4.c index 22cac7975b3c..8df90ea04c7c 100644 --- a/drivers/ntb/hw/intel/ntb_hw_gen4.c +++ b/drivers/ntb/hw/intel/ntb_hw_gen4.c @@ -335,7 +335,8 @@ ssize_t ndev_ntb4_debugfs_read(struct file *filp, char = __user *ubuf, } =20 static int intel_ntb4_mw_set_trans(struct ntb_dev *ntb, int pidx, int idx, - dma_addr_t addr, resource_size_t size) + dma_addr_t addr, resource_size_t size, + resource_size_t offset) { struct intel_ntb_dev *ndev =3D ntb_ndev(ntb); unsigned long xlat_reg, limit_reg, idx_reg; @@ -524,7 +525,8 @@ static int intel_ntb4_link_disable(struct ntb_dev *ntb) static int intel_ntb4_mw_get_align(struct ntb_dev *ntb, int pidx, int idx, resource_size_t *addr_align, resource_size_t *size_align, - resource_size_t *size_max) + resource_size_t *size_max, + resource_size_t *offset) { struct intel_ntb_dev *ndev =3D ntb_ndev(ntb); resource_size_t bar_size, mw_size; diff --git a/drivers/ntb/hw/mscc/ntb_hw_switchtec.c b/drivers/ntb/hw/mscc/n= tb_hw_switchtec.c index e38540b92716..5d8bace78d4f 100644 --- a/drivers/ntb/hw/mscc/ntb_hw_switchtec.c +++ b/drivers/ntb/hw/mscc/ntb_hw_switchtec.c @@ -191,7 +191,8 @@ static int peer_lut_index(struct switchtec_ntb *sndev, = int mw_idx) static int switchtec_ntb_mw_get_align(struct ntb_dev *ntb, int pidx, int widx, resource_size_t *addr_align, resource_size_t *size_align, - resource_size_t *size_max) + resource_size_t *size_max, + resource_size_t *offset) { struct switchtec_ntb *sndev =3D ntb_sndev(ntb); int lut; @@ -268,7 +269,8 @@ static void switchtec_ntb_mw_set_lut(struct switchtec_n= tb *sndev, int idx, } =20 static int switchtec_ntb_mw_set_trans(struct ntb_dev *ntb, int pidx, int w= idx, - dma_addr_t addr, resource_size_t size) + dma_addr_t addr, resource_size_t size, + resource_size_t offset) { struct switchtec_ntb *sndev =3D ntb_sndev(ntb); struct ntb_ctrl_regs __iomem *ctl =3D sndev->mmio_peer_ctrl; diff --git a/drivers/ntb/msi.c b/drivers/ntb/msi.c index 6817d504c12a..8875bcbf2ea4 100644 --- a/drivers/ntb/msi.c +++ b/drivers/ntb/msi.c @@ -117,7 +117,7 @@ int ntb_msi_setup_mws(struct ntb_dev *ntb) return peer_widx; =20 ret =3D ntb_mw_get_align(ntb, peer, peer_widx, &addr_align, - NULL, NULL); + NULL, NULL, NULL); if (ret) return ret; =20 @@ -132,7 +132,7 @@ int ntb_msi_setup_mws(struct ntb_dev *ntb) } =20 ret =3D ntb_mw_get_align(ntb, peer, peer_widx, NULL, - &size_align, &size_max); + &size_align, &size_max, NULL); if (ret) goto error_out; =20 @@ -142,7 +142,7 @@ int ntb_msi_setup_mws(struct ntb_dev *ntb) mw_min_size =3D mw_size; =20 ret =3D ntb_mw_set_trans(ntb, peer, peer_widx, - addr, mw_size); + addr, mw_size, 0); if (ret) goto error_out; } diff --git a/drivers/ntb/ntb_transport.c b/drivers/ntb/ntb_transport.c index eb875e3db2e3..4bb1a64c1090 100644 --- a/drivers/ntb/ntb_transport.c +++ b/drivers/ntb/ntb_transport.c @@ -883,7 +883,7 @@ static int ntb_set_mw(struct ntb_transport_ctx *nt, int= num_mw, return -EINVAL; =20 rc =3D ntb_mw_get_align(nt->ndev, PIDX, num_mw, &xlat_align, - &xlat_align_size, NULL); + &xlat_align_size, NULL, NULL); if (rc) return rc; =20 @@ -918,7 +918,7 @@ static int ntb_set_mw(struct ntb_transport_ctx *nt, int= num_mw, =20 /* Notify HW the memory location of the receive buffer */ rc =3D ntb_mw_set_trans(nt->ndev, PIDX, num_mw, mw->dma_addr, - mw->xlat_size); + mw->xlat_size, 0); if (rc) { dev_err(&pdev->dev, "Unable to set mw%d translation", num_mw); ntb_free_mw(nt, num_mw); diff --git a/drivers/ntb/test/ntb_perf.c b/drivers/ntb/test/ntb_perf.c index dfd175f79e8f..b842b69e4242 100644 --- a/drivers/ntb/test/ntb_perf.c +++ b/drivers/ntb/test/ntb_perf.c @@ -573,7 +573,7 @@ static int perf_setup_inbuf(struct perf_peer *peer) =20 /* Get inbound MW parameters */ ret =3D ntb_mw_get_align(perf->ntb, peer->pidx, perf->gidx, - &xlat_align, &size_align, &size_max); + &xlat_align, &size_align, &size_max, NULL); if (ret) { dev_err(&perf->ntb->dev, "Couldn't get inbuf restrictions\n"); return ret; @@ -604,7 +604,7 @@ static int perf_setup_inbuf(struct perf_peer *peer) } =20 ret =3D ntb_mw_set_trans(perf->ntb, peer->pidx, peer->gidx, - peer->inbuf_xlat, peer->inbuf_size); + peer->inbuf_xlat, peer->inbuf_size, 0); if (ret) { dev_err(&perf->ntb->dev, "Failed to set inbuf translation\n"); goto err_free_inbuf; diff --git a/drivers/ntb/test/ntb_tool.c b/drivers/ntb/test/ntb_tool.c index 641cb7e05a47..7a7ba486bba7 100644 --- a/drivers/ntb/test/ntb_tool.c +++ b/drivers/ntb/test/ntb_tool.c @@ -578,7 +578,7 @@ static int tool_setup_mw(struct tool_ctx *tc, int pidx,= int widx, return 0; =20 ret =3D ntb_mw_get_align(tc->ntb, pidx, widx, &addr_align, - &size_align, &size); + &size_align, &size, NULL); if (ret) return ret; =20 @@ -595,7 +595,7 @@ static int tool_setup_mw(struct tool_ctx *tc, int pidx,= int widx, goto err_free_dma; } =20 - ret =3D ntb_mw_set_trans(tc->ntb, pidx, widx, inmw->dma_base, inmw->size); + ret =3D ntb_mw_set_trans(tc->ntb, pidx, widx, inmw->dma_base, inmw->size,= 0); if (ret) goto err_free_dma; =20 @@ -652,7 +652,7 @@ static ssize_t tool_mw_trans_read(struct file *filep, c= har __user *ubuf, return -ENOMEM; =20 ret =3D ntb_mw_get_align(inmw->tc->ntb, inmw->pidx, inmw->widx, - &addr_align, &size_align, &size_max); + &addr_align, &size_align, &size_max, NULL); if (ret) goto err; =20 diff --git a/drivers/pci/endpoint/functions/pci-epf-vntb.c b/drivers/pci/en= dpoint/functions/pci-epf-vntb.c index 42e57721dcb4..8dbae9be9402 100644 --- a/drivers/pci/endpoint/functions/pci-epf-vntb.c +++ b/drivers/pci/endpoint/functions/pci-epf-vntb.c @@ -1385,7 +1385,7 @@ static int vntb_epf_db_set_mask(struct ntb_dev *ntb, = u64 db_bits) } =20 static int vntb_epf_mw_set_trans(struct ntb_dev *ndev, int pidx, int idx, - dma_addr_t addr, resource_size_t size) + dma_addr_t addr, resource_size_t size, resource_size_t offset) { struct epf_ntb *ntb =3D ntb_ndev(ndev); struct pci_epf_bar *epf_bar; @@ -1403,7 +1403,7 @@ static int vntb_epf_mw_set_trans(struct ntb_dev *ndev= , int pidx, int idx, epf_bar->barno =3D barno; epf_bar->size =3D size; =20 - ret =3D pci_epc_map_inbound(epc, 0, 0, epf_bar, 0); + ret =3D pci_epc_map_inbound(epc, 0, 0, epf_bar, offset); if (ret =3D=3D -EOPNOTSUPP) ret =3D pci_epc_set_bar(epc, 0, 0, epf_bar); =20 @@ -1514,7 +1514,8 @@ static u64 vntb_epf_db_read(struct ntb_dev *ndev) static int vntb_epf_mw_get_align(struct ntb_dev *ndev, int pidx, int idx, resource_size_t *addr_align, resource_size_t *size_align, - resource_size_t *size_max) + resource_size_t *size_max, + resource_size_t *offset) { struct epf_ntb *ntb =3D ntb_ndev(ndev); =20 diff --git a/include/linux/ntb.h b/include/linux/ntb.h index 8ff9d663096b..d7ce5d2e60d0 100644 --- a/include/linux/ntb.h +++ b/include/linux/ntb.h @@ -273,9 +273,11 @@ struct ntb_dev_ops { int (*mw_get_align)(struct ntb_dev *ntb, int pidx, int widx, resource_size_t *addr_align, resource_size_t *size_align, - resource_size_t *size_max); + resource_size_t *size_max, + resource_size_t *offset); int (*mw_set_trans)(struct ntb_dev *ntb, int pidx, int widx, - dma_addr_t addr, resource_size_t size); + dma_addr_t addr, resource_size_t size, + resource_size_t offset); int (*mw_clear_trans)(struct ntb_dev *ntb, int pidx, int widx); int (*peer_mw_count)(struct ntb_dev *ntb); int (*peer_mw_get_addr)(struct ntb_dev *ntb, int widx, @@ -823,13 +825,14 @@ static inline int ntb_mw_count(struct ntb_dev *ntb, i= nt pidx) static inline int ntb_mw_get_align(struct ntb_dev *ntb, int pidx, int widx, resource_size_t *addr_align, resource_size_t *size_align, - resource_size_t *size_max) + resource_size_t *size_max, + resource_size_t *offset) { if (!(ntb_link_is_up(ntb, NULL, NULL) & BIT_ULL(pidx))) return -ENOTCONN; =20 return ntb->ops->mw_get_align(ntb, pidx, widx, addr_align, size_align, - size_max); + size_max, offset); } =20 /** @@ -852,12 +855,13 @@ static inline int ntb_mw_get_align(struct ntb_dev *nt= b, int pidx, int widx, * Return: Zero on success, otherwise an error number. */ static inline int ntb_mw_set_trans(struct ntb_dev *ntb, int pidx, int widx, - dma_addr_t addr, resource_size_t size) + dma_addr_t addr, resource_size_t size, + resource_size_t offset) { if (!ntb->ops->mw_set_trans) return 0; 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Received: from TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:24c::11) by TYCP286MB2050.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:15e::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9366.17; Sat, 29 Nov 2025 16:04:26 +0000 Received: from TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM ([fe80::fb7e:f4ed:a580:9d03]) by TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM ([fe80::fb7e:f4ed:a580:9d03%5]) with mapi id 15.20.9366.012; Sat, 29 Nov 2025 16:04:26 +0000 From: Koichiro Den To: ntb@lists.linux.dev, linux-pci@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Frank.Li@nxp.com Cc: mani@kernel.org, kwilczynski@kernel.org, kishon@kernel.org, bhelgaas@google.com, corbet@lwn.net, vkoul@kernel.org, jdmason@kudzu.us, dave.jiang@intel.com, allenbh@gmail.com, Basavaraj.Natikar@amd.com, Shyam-sundar.S-k@amd.com, kurt.schwemmer@microsemi.com, logang@deltatee.com, jingoohan1@gmail.com, lpieralisi@kernel.org, robh@kernel.org, jbrunet@baylibre.com, fancer.lancer@gmail.com, arnd@arndb.de, pstanner@redhat.com, elfring@users.sourceforge.net Subject: [RFC PATCH v2 08/27] PCI: endpoint: pci-epf-vntb: Propagate MW offset from configfs when present Date: Sun, 30 Nov 2025 01:03:46 +0900 Message-ID: <20251129160405.2568284-9-den@valinux.co.jp> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20251129160405.2568284-1-den@valinux.co.jp> References: <20251129160405.2568284-1-den@valinux.co.jp> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: TYCP286CA0017.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:263::7) To TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:24c::11) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TYWP286MB2697:EE_|TYCP286MB2050:EE_ X-MS-Office365-Filtering-Correlation-Id: 15740015-afe2-4c4e-6c90-08de2f60f856 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|366016|1800799024|10070799003; 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charset="utf-8" The NTB API functions ntb_mw_set_trans() and ntb_mw_get_align() now support non-zero MW offsets. Update pci-epf-vntb to populate mws_offset[idx] when the offset parameter is provided. Users can now get the offset value and use it on ntb_mw_set_trans(). Signed-off-by: Koichiro Den Reviewed-by: Frank Li --- drivers/pci/endpoint/functions/pci-epf-vntb.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/endpoint/functions/pci-epf-vntb.c b/drivers/pci/en= dpoint/functions/pci-epf-vntb.c index 8dbae9be9402..aa44dcd5c943 100644 --- a/drivers/pci/endpoint/functions/pci-epf-vntb.c +++ b/drivers/pci/endpoint/functions/pci-epf-vntb.c @@ -1528,6 +1528,9 @@ static int vntb_epf_mw_get_align(struct ntb_dev *ndev= , int pidx, int idx, if (size_max) *size_max =3D ntb->mws_size[idx]; =20 + if (offset) + *offset =3D ntb->mws_offset[idx]; + return 0; } =20 --=20 2.48.1 From nobody Mon Dec 1 22:07:44 2025 Received: from OS0P286CU010.outbound.protection.outlook.com (mail-japanwestazon11011070.outbound.protection.outlook.com [40.107.74.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 40CFE3101C4; Sat, 29 Nov 2025 16:04:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Received: from TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:24c::11) by TYCP286MB2050.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:15e::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9366.17; Sat, 29 Nov 2025 16:04:27 +0000 Received: from TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM ([fe80::fb7e:f4ed:a580:9d03]) by TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM ([fe80::fb7e:f4ed:a580:9d03%5]) with mapi id 15.20.9366.012; Sat, 29 Nov 2025 16:04:27 +0000 From: Koichiro Den To: ntb@lists.linux.dev, linux-pci@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Frank.Li@nxp.com Cc: mani@kernel.org, kwilczynski@kernel.org, kishon@kernel.org, bhelgaas@google.com, corbet@lwn.net, vkoul@kernel.org, jdmason@kudzu.us, dave.jiang@intel.com, allenbh@gmail.com, Basavaraj.Natikar@amd.com, Shyam-sundar.S-k@amd.com, kurt.schwemmer@microsemi.com, logang@deltatee.com, jingoohan1@gmail.com, lpieralisi@kernel.org, robh@kernel.org, jbrunet@baylibre.com, fancer.lancer@gmail.com, arnd@arndb.de, pstanner@redhat.com, elfring@users.sourceforge.net Subject: [RFC PATCH v2 09/27] NTB: ntb_transport: Support offsetted partial memory windows Date: Sun, 30 Nov 2025 01:03:47 +0900 Message-ID: <20251129160405.2568284-10-den@valinux.co.jp> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20251129160405.2568284-1-den@valinux.co.jp> References: <20251129160405.2568284-1-den@valinux.co.jp> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: TYCP286CA0057.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:2b5::20) To TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:24c::11) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TYWP286MB2697:EE_|TYCP286MB2050:EE_ X-MS-Office365-Filtering-Correlation-Id: da02b3dc-6812-4d6a-c5a2-08de2f60f8ec X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|366016|1800799024|10070799003; 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charset="utf-8" The NTB API functions ntb_mw_set_trans() and ntb_mw_get_align() now support non-zero MW offsets. Update ntb_transport to make use of this capability by propagating the offset when setting up MW translations. Signed-off-by: Koichiro Den --- drivers/ntb/ntb_transport.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/ntb/ntb_transport.c b/drivers/ntb/ntb_transport.c index 4bb1a64c1090..3f3bc991e667 100644 --- a/drivers/ntb/ntb_transport.c +++ b/drivers/ntb/ntb_transport.c @@ -877,13 +877,14 @@ static int ntb_set_mw(struct ntb_transport_ctx *nt, i= nt num_mw, size_t xlat_size, buff_size; resource_size_t xlat_align; resource_size_t xlat_align_size; + resource_size_t offset; int rc; =20 if (!size) return -EINVAL; =20 rc =3D ntb_mw_get_align(nt->ndev, PIDX, num_mw, &xlat_align, - &xlat_align_size, NULL, NULL); + &xlat_align_size, NULL, &offset); if (rc) return rc; =20 @@ -918,7 +919,7 @@ static int ntb_set_mw(struct ntb_transport_ctx *nt, int= num_mw, =20 /* Notify HW the memory location of the receive buffer */ rc =3D ntb_mw_set_trans(nt->ndev, PIDX, num_mw, mw->dma_addr, - mw->xlat_size, 0); + mw->xlat_size, offset); if (rc) { dev_err(&pdev->dev, "Unable to set mw%d translation", num_mw); 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charset="utf-8" Add an optional get_pci_epc() callback to retrieve the underlying pci_epc device associated with the NTB implementation. Signed-off-by: Koichiro Den --- drivers/ntb/hw/epf/ntb_hw_epf.c | 11 +---------- include/linux/ntb.h | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+), 10 deletions(-) diff --git a/drivers/ntb/hw/epf/ntb_hw_epf.c b/drivers/ntb/hw/epf/ntb_hw_ep= f.c index a3ec411bfe49..d55ce6b0fad4 100644 --- a/drivers/ntb/hw/epf/ntb_hw_epf.c +++ b/drivers/ntb/hw/epf/ntb_hw_epf.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include =20 @@ -49,16 +50,6 @@ =20 #define NTB_EPF_COMMAND_TIMEOUT 1000 /* 1 Sec */ =20 -enum pci_barno { - NO_BAR =3D -1, - BAR_0, - BAR_1, - BAR_2, - BAR_3, - BAR_4, - BAR_5, -}; - enum epf_ntb_bar { BAR_CONFIG, BAR_PEER_SPAD, diff --git a/include/linux/ntb.h b/include/linux/ntb.h index d7ce5d2e60d0..04dc9a4d6b85 100644 --- a/include/linux/ntb.h +++ b/include/linux/ntb.h @@ -64,6 +64,7 @@ struct ntb_client; struct ntb_dev; struct ntb_msi; struct pci_dev; +struct pci_epc; =20 /** * enum ntb_topo - NTB connection topology @@ -256,6 +257,7 @@ static inline int ntb_ctx_ops_is_valid(const struct ntb= _ctx_ops *ops) * @msg_clear_mask: See ntb_msg_clear_mask(). * @msg_read: See ntb_msg_read(). * @peer_msg_write: See ntb_peer_msg_write(). + * @get_pci_epc: See ntb_get_pci_epc(). */ struct ntb_dev_ops { int (*port_number)(struct ntb_dev *ntb); @@ -331,6 +333,7 @@ struct ntb_dev_ops { int (*msg_clear_mask)(struct ntb_dev *ntb, u64 mask_bits); u32 (*msg_read)(struct ntb_dev *ntb, int *pidx, int midx); int (*peer_msg_write)(struct ntb_dev *ntb, int pidx, int midx, u32 msg); + struct pci_epc *(*get_pci_epc)(struct ntb_dev *ntb); }; =20 static inline int ntb_dev_ops_is_valid(const struct ntb_dev_ops *ops) @@ -393,6 +396,9 @@ static inline int ntb_dev_ops_is_valid(const struct ntb= _dev_ops *ops) /* !ops->msg_clear_mask =3D=3D !ops->msg_count && */ !ops->msg_read =3D=3D !ops->msg_count && !ops->peer_msg_write =3D=3D !ops->msg_count && + + /* Miscellaneous optional callbacks */ + /* ops->get_pci_epc && */ 1; } =20 @@ -1567,6 +1573,21 @@ static inline int ntb_peer_msg_write(struct ntb_dev = *ntb, int pidx, int midx, return ntb->ops->peer_msg_write(ntb, pidx, midx, msg); } =20 +/** + * ntb_get_pci_epc() - get backing PCI endpoint controller if possible. + * @ntb: NTB device context. + * + * Get the backing PCI endpoint controller representation. + * + * Return: A pointer to the pci_epc instance if available. or %NULL if not. + */ +static inline struct pci_epc __maybe_unused *ntb_get_pci_epc(struct ntb_de= v *ntb) +{ + if (!ntb->ops->get_pci_epc) + return NULL; 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Sat, 29 Nov 2025 16:04:29 +0000 From: Koichiro Den To: ntb@lists.linux.dev, linux-pci@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Frank.Li@nxp.com Cc: mani@kernel.org, kwilczynski@kernel.org, kishon@kernel.org, bhelgaas@google.com, corbet@lwn.net, vkoul@kernel.org, jdmason@kudzu.us, dave.jiang@intel.com, allenbh@gmail.com, Basavaraj.Natikar@amd.com, Shyam-sundar.S-k@amd.com, kurt.schwemmer@microsemi.com, logang@deltatee.com, jingoohan1@gmail.com, lpieralisi@kernel.org, robh@kernel.org, jbrunet@baylibre.com, fancer.lancer@gmail.com, arnd@arndb.de, pstanner@redhat.com, elfring@users.sourceforge.net Subject: [RFC PATCH v2 11/27] NTB: epf: vntb: Implement .get_pci_epc() callback Date: Sun, 30 Nov 2025 01:03:49 +0900 Message-ID: <20251129160405.2568284-12-den@valinux.co.jp> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20251129160405.2568284-1-den@valinux.co.jp> References: <20251129160405.2568284-1-den@valinux.co.jp> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: TY4PR01CA0078.jpnprd01.prod.outlook.com (2603:1096:405:36c::16) To TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:24c::11) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TYWP286MB2697:EE_|TYCP286MB2050:EE_ X-MS-Office365-Filtering-Correlation-Id: 89c3914f-b680-4f01-8820-08de2f60fa3d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|366016|1800799024|10070799003; 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charset="utf-8" Implement the new get_pci_epc() operation for the EPF vNTB driver to expose its associated EPC device to NTB subsystems. Signed-off-by: Koichiro Den --- drivers/pci/endpoint/functions/pci-epf-vntb.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/pci/endpoint/functions/pci-epf-vntb.c b/drivers/pci/en= dpoint/functions/pci-epf-vntb.c index aa44dcd5c943..93fd724a8faa 100644 --- a/drivers/pci/endpoint/functions/pci-epf-vntb.c +++ b/drivers/pci/endpoint/functions/pci-epf-vntb.c @@ -1561,6 +1561,15 @@ static int vntb_epf_link_disable(struct ntb_dev *ntb) return 0; } =20 +static struct pci_epc *vntb_epf_get_pci_epc(struct ntb_dev *ntb) +{ + struct epf_ntb *ndev =3D ntb_ndev(ntb); + + if (!ndev || !ndev->epf) + return NULL; + return ndev->epf->epc; +} + static const struct ntb_dev_ops vntb_epf_ops =3D { .mw_count =3D vntb_epf_mw_count, .spad_count =3D vntb_epf_spad_count, @@ -1582,6 +1591,7 @@ static const struct ntb_dev_ops vntb_epf_ops =3D { .db_clear_mask =3D vntb_epf_db_clear_mask, .db_clear =3D vntb_epf_db_clear, .link_disable =3D vntb_epf_link_disable, + .get_pci_epc =3D vntb_epf_get_pci_epc, }; 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charset="utf-8" When multiple MSI vectors are allocated for the DesignWare eDMA, the driver currently records the same MSI message for all IRQs by calling get_cached_msi_msg() per vector. For multi-vector MSI (as opposed to MSI-X), the cached message corresponds to vector 0 and msg.data is supposed to be adjusted by the IRQ index. As a result, all eDMA interrupts share the same MSI data value and the interrupt controller cannot distinguish between them. Introduce dw_edma_compose_msi() to construct the correct MSI message for each vector. For MSI-X nothing changes. For multi-vector MSI, derive the base IRQ with msi_get_virq(dev, 0) and OR in the per-vector offset into msg.data before storing it in dw->irq[i].msi. This makes each IMWr MSI vector use a unique MSI data value. Signed-off-by: Koichiro Den --- drivers/dma/dw-edma/dw-edma-core.c | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-ed= ma-core.c index 8e5f7defa6b6..3542177a4a8e 100644 --- a/drivers/dma/dw-edma/dw-edma-core.c +++ b/drivers/dma/dw-edma/dw-edma-core.c @@ -839,6 +839,28 @@ static inline void dw_edma_add_irq_mask(u32 *mask, u32= alloc, u16 cnt) (*mask)++; } =20 +static void dw_edma_compose_msi(struct device *dev, int irq, struct msi_ms= g *out) +{ + struct msi_desc *desc =3D irq_get_msi_desc(irq); + struct msi_msg msg; + unsigned int base; + + if (!desc) + return; + + get_cached_msi_msg(irq, &msg); + if (!desc->pci.msi_attrib.is_msix) { + /* + * For multi-vector MSI, the cached message corresponds to + * vector 0. Adjust msg.data by the IRQ index so that each + * vector gets a unique MSI data value for IMWr Data Register. + */ + base =3D msi_get_virq(dev, 0); + msg.data |=3D (irq - base); + } + *out =3D msg; +} + static int dw_edma_irq_request(struct dw_edma *dw, u32 *wr_alloc, u32 *rd_alloc) { @@ -869,8 +891,7 @@ static int dw_edma_irq_request(struct dw_edma *dw, return err; } =20 - if (irq_get_msi_desc(irq)) - get_cached_msi_msg(irq, &dw->irq[0].msi); + dw_edma_compose_msi(dev, irq, &dw->irq[0].msi); =20 dw->nr_irqs =3D 1; } else { @@ -896,8 +917,7 @@ static int dw_edma_irq_request(struct dw_edma *dw, if (err) goto err_irq_free; =20 - if (irq_get_msi_desc(irq)) - get_cached_msi_msg(irq, &dw->irq[i].msi); + dw_edma_compose_msi(dev, irq, &dw->irq[i].msi); } =20 dw->nr_irqs =3D i; --=20 2.48.1 From nobody Mon Dec 1 22:07:44 2025 Received: from OS0P286CU010.outbound.protection.outlook.com (mail-japanwestazon11011070.outbound.protection.outlook.com [40.107.74.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C621311C3B; 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Received: from TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:24c::11) by TYCP286MB2050.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:15e::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9366.17; Sat, 29 Nov 2025 16:04:31 +0000 Received: from TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM ([fe80::fb7e:f4ed:a580:9d03]) by TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM ([fe80::fb7e:f4ed:a580:9d03%5]) with mapi id 15.20.9366.012; Sat, 29 Nov 2025 16:04:31 +0000 From: Koichiro Den To: ntb@lists.linux.dev, linux-pci@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Frank.Li@nxp.com Cc: mani@kernel.org, kwilczynski@kernel.org, kishon@kernel.org, bhelgaas@google.com, corbet@lwn.net, vkoul@kernel.org, jdmason@kudzu.us, dave.jiang@intel.com, allenbh@gmail.com, Basavaraj.Natikar@amd.com, Shyam-sundar.S-k@amd.com, kurt.schwemmer@microsemi.com, logang@deltatee.com, jingoohan1@gmail.com, lpieralisi@kernel.org, robh@kernel.org, jbrunet@baylibre.com, fancer.lancer@gmail.com, arnd@arndb.de, pstanner@redhat.com, elfring@users.sourceforge.net Subject: [RFC PATCH v2 13/27] NTB: ntb_transport: Use seq_file for QP stats debugfs Date: Sun, 30 Nov 2025 01:03:51 +0900 Message-ID: <20251129160405.2568284-14-den@valinux.co.jp> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20251129160405.2568284-1-den@valinux.co.jp> References: <20251129160405.2568284-1-den@valinux.co.jp> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: TYCP286CA0218.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:3c5::17) To TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:24c::11) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TYWP286MB2697:EE_|TYCP286MB2050:EE_ X-MS-Office365-Filtering-Correlation-Id: f0187964-dc57-42a0-6b28-08de2f60fb7f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|366016|1800799024|10070799003; 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charset="utf-8" The ./qp*/stats debugfs file for each NTB transport QP is currently implemented with a hand-crafted kmalloc() buffer and a series of scnprintf() calls. This is a pre-seq_file style pattern and makes future extensions easy to truncate. Convert the stats file to use the seq_file helpers via DEFINE_SHOW_ATTRIBUTE(), which simplifies the code and lets the seq_file core handle buffering and partial reads. While touching this area, fix a bug in the per-QP debugfs directory naming: the buffer used for "qp%d" was only 4 bytes, which truncates names like "qp10" to "qp1" and causes multiple queues to share the same directory. Enlarge the buffer and use sizeof() to avoid truncation. Signed-off-by: Koichiro Den Reviewed-by: Frank Li --- drivers/ntb/ntb_transport.c | 136 +++++++++++------------------------- 1 file changed, 41 insertions(+), 95 deletions(-) diff --git a/drivers/ntb/ntb_transport.c b/drivers/ntb/ntb_transport.c index 3f3bc991e667..57b4c0511927 100644 --- a/drivers/ntb/ntb_transport.c +++ b/drivers/ntb/ntb_transport.c @@ -57,6 +57,7 @@ #include #include #include +#include #include #include #include @@ -466,104 +467,49 @@ void ntb_transport_unregister_client(struct ntb_tran= sport_client *drv) } EXPORT_SYMBOL_GPL(ntb_transport_unregister_client); =20 -static ssize_t debugfs_read(struct file *filp, char __user *ubuf, size_t c= ount, - loff_t *offp) +static int ntb_qp_debugfs_stats_show(struct seq_file *s, void *v) { - struct ntb_transport_qp *qp; - char *buf; - ssize_t ret, out_offset, out_count; - - qp =3D filp->private_data; + struct ntb_transport_qp *qp =3D s->private; =20 if (!qp || !qp->link_is_up) return 0; =20 - out_count =3D 1000; - - buf =3D kmalloc(out_count, GFP_KERNEL); - if (!buf) - return -ENOMEM; + seq_puts(s, "\nNTB QP stats:\n\n"); + + seq_printf(s, "rx_bytes - \t%llu\n", qp->rx_bytes); + seq_printf(s, "rx_pkts - \t%llu\n", qp->rx_pkts); + seq_printf(s, "rx_memcpy - \t%llu\n", qp->rx_memcpy); + seq_printf(s, "rx_async - \t%llu\n", qp->rx_async); + seq_printf(s, "rx_ring_empty - %llu\n", qp->rx_ring_empty); + seq_printf(s, "rx_err_no_buf - %llu\n", qp->rx_err_no_buf); + seq_printf(s, "rx_err_oflow - \t%llu\n", qp->rx_err_oflow); + seq_printf(s, "rx_err_ver - \t%llu\n", qp->rx_err_ver); + seq_printf(s, "rx_buff - \t0x%p\n", qp->rx_buff); + seq_printf(s, "rx_index - \t%u\n", qp->rx_index); + seq_printf(s, "rx_max_entry - \t%u\n", qp->rx_max_entry); + seq_printf(s, "rx_alloc_entry - \t%u\n\n", qp->rx_alloc_entry); + + seq_printf(s, "tx_bytes - \t%llu\n", qp->tx_bytes); + seq_printf(s, "tx_pkts - \t%llu\n", qp->tx_pkts); + seq_printf(s, "tx_memcpy - \t%llu\n", qp->tx_memcpy); + seq_printf(s, "tx_async - \t%llu\n", qp->tx_async); + seq_printf(s, "tx_ring_full - \t%llu\n", qp->tx_ring_full); + seq_printf(s, "tx_err_no_buf - %llu\n", qp->tx_err_no_buf); + seq_printf(s, "tx_mw - \t0x%p\n", qp->tx_mw); + seq_printf(s, "tx_index (H) - \t%u\n", qp->tx_index); + seq_printf(s, "RRI (T) - \t%u\n", qp->remote_rx_info->entry); + seq_printf(s, "tx_max_entry - \t%u\n", qp->tx_max_entry); + seq_printf(s, "free tx - \t%u\n", ntb_transport_tx_free_entry(qp)); + seq_putc(s, '\n'); + + seq_printf(s, "Using TX DMA - \t%s\n", qp->tx_dma_chan ? "Yes" : "No"); + seq_printf(s, "Using RX DMA - \t%s\n", qp->rx_dma_chan ? "Yes" : "No"); + seq_printf(s, "QP Link - \t%s\n", qp->link_is_up ? "Up" : "Down"); + seq_putc(s, '\n'); =20 - out_offset =3D 0; - out_offset +=3D scnprintf(buf + out_offset, out_count - out_offset, - "\nNTB QP stats:\n\n"); - out_offset +=3D scnprintf(buf + out_offset, out_count - out_offset, - "rx_bytes - \t%llu\n", qp->rx_bytes); - out_offset +=3D scnprintf(buf + out_offset, out_count - out_offset, - "rx_pkts - \t%llu\n", qp->rx_pkts); - out_offset +=3D scnprintf(buf + out_offset, out_count - out_offset, - "rx_memcpy - \t%llu\n", qp->rx_memcpy); - out_offset +=3D scnprintf(buf + out_offset, out_count - out_offset, - "rx_async - \t%llu\n", qp->rx_async); - out_offset +=3D scnprintf(buf + out_offset, out_count - out_offset, - "rx_ring_empty - %llu\n", qp->rx_ring_empty); - out_offset +=3D scnprintf(buf + out_offset, out_count - out_offset, - "rx_err_no_buf - %llu\n", qp->rx_err_no_buf); - out_offset +=3D scnprintf(buf + out_offset, out_count - out_offset, - "rx_err_oflow - \t%llu\n", qp->rx_err_oflow); - out_offset +=3D scnprintf(buf + out_offset, out_count - out_offset, - "rx_err_ver - \t%llu\n", qp->rx_err_ver); - out_offset +=3D scnprintf(buf + out_offset, out_count - out_offset, - "rx_buff - \t0x%p\n", qp->rx_buff); - out_offset +=3D scnprintf(buf + out_offset, out_count - out_offset, - "rx_index - \t%u\n", qp->rx_index); - out_offset +=3D scnprintf(buf + out_offset, out_count - out_offset, - "rx_max_entry - \t%u\n", qp->rx_max_entry); - out_offset +=3D scnprintf(buf + out_offset, out_count - out_offset, - "rx_alloc_entry - \t%u\n\n", qp->rx_alloc_entry); - - out_offset +=3D scnprintf(buf + out_offset, out_count - out_offset, - "tx_bytes - \t%llu\n", qp->tx_bytes); - out_offset +=3D scnprintf(buf + out_offset, out_count - out_offset, - "tx_pkts - \t%llu\n", qp->tx_pkts); - out_offset +=3D scnprintf(buf + out_offset, out_count - out_offset, - "tx_memcpy - \t%llu\n", qp->tx_memcpy); - out_offset +=3D scnprintf(buf + out_offset, out_count - out_offset, - "tx_async - \t%llu\n", qp->tx_async); - out_offset +=3D scnprintf(buf + out_offset, out_count - out_offset, - "tx_ring_full - \t%llu\n", qp->tx_ring_full); - out_offset +=3D scnprintf(buf + out_offset, out_count - out_offset, - "tx_err_no_buf - %llu\n", qp->tx_err_no_buf); - out_offset +=3D scnprintf(buf + out_offset, out_count - out_offset, - "tx_mw - \t0x%p\n", qp->tx_mw); - out_offset +=3D scnprintf(buf + out_offset, out_count - out_offset, - "tx_index (H) - \t%u\n", qp->tx_index); - out_offset +=3D scnprintf(buf + out_offset, out_count - out_offset, - "RRI (T) - \t%u\n", - qp->remote_rx_info->entry); - out_offset +=3D scnprintf(buf + out_offset, out_count - out_offset, - "tx_max_entry - \t%u\n", qp->tx_max_entry); - out_offset +=3D scnprintf(buf + out_offset, out_count - out_offset, - "free tx - \t%u\n", - ntb_transport_tx_free_entry(qp)); - - out_offset +=3D scnprintf(buf + out_offset, out_count - out_offset, - "\n"); - out_offset +=3D scnprintf(buf + out_offset, out_count - out_offset, - "Using TX DMA - \t%s\n", - qp->tx_dma_chan ? "Yes" : "No"); - out_offset +=3D scnprintf(buf + out_offset, out_count - out_offset, - "Using RX DMA - \t%s\n", - qp->rx_dma_chan ? "Yes" : "No"); - out_offset +=3D scnprintf(buf + out_offset, out_count - out_offset, - "QP Link - \t%s\n", - qp->link_is_up ? "Up" : "Down"); - out_offset +=3D scnprintf(buf + out_offset, out_count - out_offset, - "\n"); - - if (out_offset > out_count) - out_offset =3D out_count; - - ret =3D simple_read_from_buffer(ubuf, count, offp, buf, out_offset); - kfree(buf); - return ret; -} - -static const struct file_operations ntb_qp_debugfs_stats =3D { - .owner =3D THIS_MODULE, - .open =3D simple_open, - .read =3D debugfs_read, -}; + return 0; +} +DEFINE_SHOW_ATTRIBUTE(ntb_qp_debugfs_stats); =20 static void ntb_list_add(spinlock_t *lock, struct list_head *entry, struct list_head *list) @@ -1237,15 +1183,15 @@ static int ntb_transport_init_queue(struct ntb_tran= sport_ctx *nt, qp->tx_max_entry =3D tx_size / qp->tx_max_frame; =20 if (nt->debugfs_node_dir) { - char debugfs_name[4]; + char debugfs_name[8]; =20 - snprintf(debugfs_name, 4, "qp%d", qp_num); + snprintf(debugfs_name, sizeof(debugfs_name), "qp%d", qp_num); qp->debugfs_dir =3D debugfs_create_dir(debugfs_name, nt->debugfs_node_dir); =20 qp->debugfs_stats =3D debugfs_create_file("stats", S_IRUSR, qp->debugfs_dir, qp, - &ntb_qp_debugfs_stats); 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charset="utf-8" Historically both TX and RX have assumed the same per-QP MW slice (tx_max_entry =3D=3D remote rx_max_entry), while those are calculated separately in different places (pre and post the link-up negotiation point). This has been safe because nt->link_is_up is never set to true unless the pre-determined qp_count are the same among them, and qp_count is typically limited to nt->mw_count, which should be carefully configured by admin. However, setup_qp_mw can actually split mw and handle multi-qps in one MW properly, so qp_count needs not to be limited by nt->mw_count. Once we relaxing the limitation, pre-determined qp_count can differ among host side and endpoint, and link-up negotiation can easily fail. Move the TX MW configuration (per-QP offset and size) into ntb_transport_setup_qp_mw() so that both RX and TX layout decisions are centralized in a single helper. ntb_transport_init_queue() now deals only with per-QP software state, not with MW layout. This keeps the previous behaviour, while preparing for relaxing the qp_count limitation and improving readibility. No functional change is intended. Signed-off-by: Koichiro Den --- drivers/ntb/ntb_transport.c | 67 ++++++++++++++----------------------- 1 file changed, 26 insertions(+), 41 deletions(-) diff --git a/drivers/ntb/ntb_transport.c b/drivers/ntb/ntb_transport.c index 57b4c0511927..79063e2f911b 100644 --- a/drivers/ntb/ntb_transport.c +++ b/drivers/ntb/ntb_transport.c @@ -569,7 +569,8 @@ static int ntb_transport_setup_qp_mw(struct ntb_transpo= rt_ctx *nt, struct ntb_transport_mw *mw; struct ntb_dev *ndev =3D nt->ndev; struct ntb_queue_entry *entry; - unsigned int rx_size, num_qps_mw; + unsigned int num_qps_mw; + unsigned int mw_size, mw_size_per_qp, qp_offset, rx_info_offset; unsigned int mw_num, mw_count, qp_count; unsigned int i; int node; @@ -588,15 +589,33 @@ static int ntb_transport_setup_qp_mw(struct ntb_trans= port_ctx *nt, else num_qps_mw =3D qp_count / mw_count; =20 - rx_size =3D (unsigned int)mw->xlat_size / num_qps_mw; - qp->rx_buff =3D mw->virt_addr + rx_size * (qp_num / mw_count); - rx_size -=3D sizeof(struct ntb_rx_info); + mw_size =3D min(nt->mw_vec[mw_num].phys_size, mw->xlat_size); + if (max_mw_size && mw_size > max_mw_size) + mw_size =3D max_mw_size; =20 - qp->remote_rx_info =3D qp->rx_buff + rx_size; + /* Split this MW evenly among the queue pairs mapped to it. */ + mw_size_per_qp =3D (unsigned int)mw_size / num_qps_mw; + qp_offset =3D mw_size_per_qp * (qp_num / mw_count); + + /* Place remote_rx_info at the end of the per-QP region. */ + rx_info_offset =3D mw_size_per_qp - sizeof(struct ntb_rx_info); + + qp->tx_mw_size =3D mw_size_per_qp; + qp->tx_mw =3D nt->mw_vec[mw_num].vbase + qp_offset; + if (!qp->tx_mw) + return -EINVAL; + qp->tx_mw_phys =3D nt->mw_vec[mw_num].phys_addr + qp_offset; + if (!qp->tx_mw_phys) + return -EINVAL; + qp->rx_info =3D qp->tx_mw + rx_info_offset; + qp->rx_buff =3D mw->virt_addr + qp_offset; + qp->remote_rx_info =3D qp->rx_buff + rx_info_offset; =20 /* Due to housekeeping, there must be atleast 2 buffs */ - qp->rx_max_frame =3D min(transport_mtu, rx_size / 2); - qp->rx_max_entry =3D rx_size / qp->rx_max_frame; + qp->tx_max_frame =3D min(transport_mtu, mw_size_per_qp / 2); + qp->tx_max_entry =3D mw_size_per_qp / qp->tx_max_frame; + qp->rx_max_frame =3D min(transport_mtu, mw_size_per_qp / 2); + qp->rx_max_entry =3D mw_size_per_qp / qp->rx_max_frame; qp->rx_index =3D 0; =20 /* @@ -1133,11 +1152,7 @@ static int ntb_transport_init_queue(struct ntb_trans= port_ctx *nt, unsigned int qp_num) { struct ntb_transport_qp *qp; - phys_addr_t mw_base; - resource_size_t mw_size; - unsigned int num_qps_mw, tx_size; unsigned int mw_num, mw_count, qp_count; - u64 qp_offset; =20 mw_count =3D nt->mw_count; qp_count =3D nt->qp_count; @@ -1152,36 +1167,6 @@ static int ntb_transport_init_queue(struct ntb_trans= port_ctx *nt, qp->event_handler =3D NULL; ntb_qp_link_context_reset(qp); =20 - if (mw_num < qp_count % mw_count) - num_qps_mw =3D qp_count / mw_count + 1; - else - num_qps_mw =3D qp_count / mw_count; - - mw_base =3D nt->mw_vec[mw_num].phys_addr; - mw_size =3D nt->mw_vec[mw_num].phys_size; - - if (max_mw_size && mw_size > max_mw_size) - mw_size =3D max_mw_size; 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Received: from TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:24c::11) by OS9P286MB4684.JPNP286.PROD.OUTLOOK.COM (2603:1096:604:2fa::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9366.17; Sat, 29 Nov 2025 16:04:34 +0000 Received: from TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM ([fe80::fb7e:f4ed:a580:9d03]) by TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM ([fe80::fb7e:f4ed:a580:9d03%5]) with mapi id 15.20.9366.012; Sat, 29 Nov 2025 16:04:34 +0000 From: Koichiro Den To: ntb@lists.linux.dev, linux-pci@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Frank.Li@nxp.com Cc: mani@kernel.org, kwilczynski@kernel.org, kishon@kernel.org, bhelgaas@google.com, corbet@lwn.net, vkoul@kernel.org, jdmason@kudzu.us, dave.jiang@intel.com, allenbh@gmail.com, Basavaraj.Natikar@amd.com, Shyam-sundar.S-k@amd.com, kurt.schwemmer@microsemi.com, logang@deltatee.com, jingoohan1@gmail.com, lpieralisi@kernel.org, robh@kernel.org, jbrunet@baylibre.com, fancer.lancer@gmail.com, arnd@arndb.de, pstanner@redhat.com, elfring@users.sourceforge.net Subject: [RFC PATCH v2 15/27] NTB: ntb_transport: Dynamically determine qp count Date: Sun, 30 Nov 2025 01:03:53 +0900 Message-ID: <20251129160405.2568284-16-den@valinux.co.jp> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20251129160405.2568284-1-den@valinux.co.jp> References: <20251129160405.2568284-1-den@valinux.co.jp> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: TY4P286CA0120.JPNP286.PROD.OUTLOOK.COM (2603:1096:405:37c::9) To TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:24c::11) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TYWP286MB2697:EE_|OS9P286MB4684:EE_ X-MS-Office365-Filtering-Correlation-Id: df360f69-c2b5-4db0-d08a-08de2f60fcdd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|366016|10070799003|1800799024; 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charset="utf-8" One MW can host multiple queue pairs, so stop limiting qp_count to the number of MWs. Now that both TX and RX MW sizing are done in the same place, the MW layout is derived from a single code path on both host and endpoint, so the layout cannot diverge between the two sides. Signed-off-by: Koichiro Den --- drivers/ntb/ntb_transport.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/ntb/ntb_transport.c b/drivers/ntb/ntb_transport.c index 79063e2f911b..5e2a87358e87 100644 --- a/drivers/ntb/ntb_transport.c +++ b/drivers/ntb/ntb_transport.c @@ -1015,6 +1015,7 @@ static void ntb_transport_link_work(struct work_struc= t *work) struct ntb_dev *ndev =3D nt->ndev; struct pci_dev *pdev =3D ndev->pdev; resource_size_t size; + u64 qp_bitmap_free; u32 val; int rc =3D 0, i, spad; =20 @@ -1062,8 +1063,23 @@ static void ntb_transport_link_work(struct work_stru= ct *work) =20 val =3D ntb_spad_read(ndev, NUM_QPS); dev_dbg(&pdev->dev, "Remote max number of qps =3D %d\n", val); - if (val !=3D nt->qp_count) + if (val =3D=3D 0) goto out; + else if (val < nt->qp_count) { + /* + * Clamp local qp_count to peer-advertised NUM_QPS to avoid + * mismatched queues. + */ + qp_bitmap_free =3D nt->qp_bitmap_free; + for (i =3D val; i < nt->qp_count; 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Received: from TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:24c::11) by OS9P286MB4684.JPNP286.PROD.OUTLOOK.COM (2603:1096:604:2fa::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9366.17; Sat, 29 Nov 2025 16:04:35 +0000 Received: from TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM ([fe80::fb7e:f4ed:a580:9d03]) by TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM ([fe80::fb7e:f4ed:a580:9d03%5]) with mapi id 15.20.9366.012; Sat, 29 Nov 2025 16:04:35 +0000 From: Koichiro Den To: ntb@lists.linux.dev, linux-pci@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Frank.Li@nxp.com Cc: mani@kernel.org, kwilczynski@kernel.org, kishon@kernel.org, bhelgaas@google.com, corbet@lwn.net, vkoul@kernel.org, jdmason@kudzu.us, dave.jiang@intel.com, allenbh@gmail.com, Basavaraj.Natikar@amd.com, Shyam-sundar.S-k@amd.com, kurt.schwemmer@microsemi.com, logang@deltatee.com, jingoohan1@gmail.com, lpieralisi@kernel.org, robh@kernel.org, jbrunet@baylibre.com, fancer.lancer@gmail.com, arnd@arndb.de, pstanner@redhat.com, elfring@users.sourceforge.net Subject: [RFC PATCH v2 16/27] NTB: ntb_transport: Introduce get_dma_dev() helper Date: Sun, 30 Nov 2025 01:03:54 +0900 Message-ID: <20251129160405.2568284-17-den@valinux.co.jp> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20251129160405.2568284-1-den@valinux.co.jp> References: <20251129160405.2568284-1-den@valinux.co.jp> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: TYCP301CA0067.JPNP301.PROD.OUTLOOK.COM (2603:1096:405:7d::20) To TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:24c::11) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TYWP286MB2697:EE_|OS9P286MB4684:EE_ X-MS-Office365-Filtering-Correlation-Id: 971e36ce-e429-4d2c-f25d-08de2f60fd7a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|366016|10070799003|1800799024; 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charset="utf-8" When ntb_transport is used on top of an endpoint function (EPF) NTB implementation, DMA mappings should be associated with the underlying PCIe controller device rather than the virtual NTB PCI function. This matters for IOMMU configuration and DMA mask validation. Add a small helper, get_dma_dev(), that returns the appropriate struct device for DMA mapping, i.e. &pdev->dev for a regular NTB host bridge and the EPC parent device for EPF-based NTB endpoints. Use it in the places where we set up DMA mappings or log DMA-related errors. Signed-off-by: Koichiro Den --- drivers/ntb/ntb_transport.c | 35 ++++++++++++++++++++++++++++------- 1 file changed, 28 insertions(+), 7 deletions(-) diff --git a/drivers/ntb/ntb_transport.c b/drivers/ntb/ntb_transport.c index 5e2a87358e87..dad596e3a405 100644 --- a/drivers/ntb/ntb_transport.c +++ b/drivers/ntb/ntb_transport.c @@ -63,6 +63,7 @@ #include #include "linux/ntb.h" #include "linux/ntb_transport.h" +#include =20 #define NTB_TRANSPORT_VERSION 4 #define NTB_TRANSPORT_VER "4" @@ -259,6 +260,26 @@ struct ntb_payload_header { unsigned int flags; }; =20 +/* + * Return the device that should be used for DMA mapping. + * + * On RC, this is simply &pdev->dev. + * On EPF-backed NTB endpoints, use the EPC parent device so that + * DMA capabilities and IOMMU configuration are taken from the + * controller rather than the virtual NTB PCI function. + */ +static struct device *get_dma_dev(struct ntb_dev *ndev) +{ + struct device *dev =3D &ndev->pdev->dev; + struct pci_epc *epc; + + epc =3D ntb_get_pci_epc(ndev); + if (epc) + dev =3D epc->dev.parent; + + return dev; +} + enum { VERSION =3D 0, QP_LINKS, @@ -762,13 +783,13 @@ static void ntb_transport_msi_desc_changed(void *data) static void ntb_free_mw(struct ntb_transport_ctx *nt, int num_mw) { struct ntb_transport_mw *mw =3D &nt->mw_vec[num_mw]; - struct pci_dev *pdev =3D nt->ndev->pdev; + struct device *dev =3D get_dma_dev(nt->ndev); =20 if (!mw->virt_addr) return; =20 ntb_mw_clear_trans(nt->ndev, PIDX, num_mw); - dma_free_coherent(&pdev->dev, mw->alloc_size, + dma_free_coherent(dev, mw->alloc_size, mw->alloc_addr, mw->dma_addr); mw->xlat_size =3D 0; mw->buff_size =3D 0; @@ -838,7 +859,7 @@ static int ntb_set_mw(struct ntb_transport_ctx *nt, int= num_mw, resource_size_t size) { struct ntb_transport_mw *mw =3D &nt->mw_vec[num_mw]; - struct pci_dev *pdev =3D nt->ndev->pdev; + struct device *dev =3D get_dma_dev(nt->ndev); size_t xlat_size, buff_size; resource_size_t xlat_align; resource_size_t xlat_align_size; @@ -868,12 +889,12 @@ static int ntb_set_mw(struct ntb_transport_ctx *nt, i= nt num_mw, mw->buff_size =3D buff_size; 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Received: from TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:24c::11) by OS9P286MB4684.JPNP286.PROD.OUTLOOK.COM (2603:1096:604:2fa::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9366.17; Sat, 29 Nov 2025 16:04:36 +0000 Received: from TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM ([fe80::fb7e:f4ed:a580:9d03]) by TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM ([fe80::fb7e:f4ed:a580:9d03%5]) with mapi id 15.20.9366.012; Sat, 29 Nov 2025 16:04:36 +0000 From: Koichiro Den To: ntb@lists.linux.dev, linux-pci@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Frank.Li@nxp.com Cc: mani@kernel.org, kwilczynski@kernel.org, kishon@kernel.org, bhelgaas@google.com, corbet@lwn.net, vkoul@kernel.org, jdmason@kudzu.us, dave.jiang@intel.com, allenbh@gmail.com, Basavaraj.Natikar@amd.com, Shyam-sundar.S-k@amd.com, kurt.schwemmer@microsemi.com, logang@deltatee.com, jingoohan1@gmail.com, lpieralisi@kernel.org, robh@kernel.org, jbrunet@baylibre.com, fancer.lancer@gmail.com, arnd@arndb.de, pstanner@redhat.com, elfring@users.sourceforge.net Subject: [RFC PATCH v2 17/27] NTB: epf: Reserve a subset of MSI vectors for non-NTB users Date: Sun, 30 Nov 2025 01:03:55 +0900 Message-ID: <20251129160405.2568284-18-den@valinux.co.jp> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20251129160405.2568284-1-den@valinux.co.jp> References: <20251129160405.2568284-1-den@valinux.co.jp> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: TYCP286CA0332.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:38e::18) To TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:24c::11) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TYWP286MB2697:EE_|OS9P286MB4684:EE_ X-MS-Office365-Filtering-Correlation-Id: 089f83d5-ca02-46ff-2e7b-08de2f60fe5e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|366016|10070799003|1800799024; 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charset="utf-8" The ntb_hw_epf driver currently uses all MSI/MSI-X vectors allocated for the endpoint as doorbell interrupts. On SoCs that also run other functions on the same PCIe controller (e.g. DesignWare eDMA), we need to reserve some vectors for those other consumers. Introduce NTB_EPF_IRQ_RESERVE and track the total number of allocated vectors in ntb_epf_dev's 'num_irqs' field. Use only (num_irqs - NTB_EPF_IRQ_RESERVE) vectors for NTB doorbells and free all num_irqs vectors in the teardown path, so that the remaining vectors can be used by other endpoint functions such as the integrated DesignWare eDMA. This makes it possible to share the PCIe controller MSI space between NTB and other on-chip IP blocks. Signed-off-by: Koichiro Den --- drivers/ntb/hw/epf/ntb_hw_epf.c | 34 +++++++++++++++++++++------------ 1 file changed, 22 insertions(+), 12 deletions(-) diff --git a/drivers/ntb/hw/epf/ntb_hw_epf.c b/drivers/ntb/hw/epf/ntb_hw_ep= f.c index d55ce6b0fad4..c94bf63d69ff 100644 --- a/drivers/ntb/hw/epf/ntb_hw_epf.c +++ b/drivers/ntb/hw/epf/ntb_hw_epf.c @@ -47,6 +47,7 @@ =20 #define NTB_EPF_MIN_DB_COUNT 3 #define NTB_EPF_MAX_DB_COUNT 31 +#define NTB_EPF_IRQ_RESERVE 8 =20 #define NTB_EPF_COMMAND_TIMEOUT 1000 /* 1 Sec */ =20 @@ -75,6 +76,8 @@ struct ntb_epf_dev { unsigned int spad_count; unsigned int db_count; =20 + unsigned int num_irqs; + void __iomem *ctrl_reg; void __iomem *db_reg; void __iomem *peer_spad_reg; @@ -329,7 +332,7 @@ static int ntb_epf_init_isr(struct ntb_epf_dev *ndev, i= nt msi_min, int msi_max) u32 argument =3D MSIX_ENABLE; int irq; int ret; - int i; + int i =3D 0; =20 irq =3D pci_alloc_irq_vectors(pdev, msi_min, msi_max, PCI_IRQ_MSIX); if (irq < 0) { @@ -343,33 +346,39 @@ static int ntb_epf_init_isr(struct ntb_epf_dev *ndev,= int msi_min, int msi_max) argument &=3D ~MSIX_ENABLE; } =20 + ndev->num_irqs =3D irq; + irq -=3D NTB_EPF_IRQ_RESERVE; + if (irq <=3D 0) { + dev_err(dev, "Not enough irqs allocated\n"); + ret =3D -ENOSPC; + goto err_out; + } + for (i =3D 0; i < irq; i++) { ret =3D request_irq(pci_irq_vector(pdev, i), ntb_epf_vec_isr, 0, "ntb_epf", ndev); if (ret) { dev_err(dev, "Failed to request irq\n"); - goto err_request_irq; + goto err_out; } } =20 - ndev->db_count =3D irq - 1; + ndev->db_count =3D irq; =20 ret =3D ntb_epf_send_command(ndev, CMD_CONFIGURE_DOORBELL, argument | irq); if (ret) { dev_err(dev, "Failed to configure doorbell\n"); - goto err_configure_db; + goto err_out; } =20 return 0; =20 -err_configure_db: - for (i =3D 0; i < ndev->db_count + 1; i++) +err_out: + while (i-- > 0) free_irq(pci_irq_vector(pdev, i), ndev); =20 -err_request_irq: pci_free_irq_vectors(pdev); - return ret; } =20 @@ -477,7 +486,7 @@ static int ntb_epf_peer_db_set(struct ntb_dev *ntb, u64= db_bits) u32 db_offset; u32 db_data; =20 - if (interrupt_num > ndev->db_count) { + if (interrupt_num >=3D ndev->db_count) { dev_err(dev, "DB interrupt %d greater than Max Supported %d\n", interrupt_num, ndev->db_count); return -EINVAL; @@ -487,6 +496,7 @@ static int ntb_epf_peer_db_set(struct ntb_dev *ntb, u64= db_bits) =20 db_data =3D readl(ndev->ctrl_reg + NTB_EPF_DB_DATA(interrupt_num)); db_offset =3D readl(ndev->ctrl_reg + NTB_EPF_DB_OFFSET(interrupt_num)); + writel(db_data, ndev->db_reg + (db_entry_size * interrupt_num) + db_offset); =20 @@ -551,8 +561,8 @@ static int ntb_epf_init_dev(struct ntb_epf_dev *ndev) int ret; =20 /* One Link interrupt and rest doorbell interrupt */ - ret =3D ntb_epf_init_isr(ndev, NTB_EPF_MIN_DB_COUNT + 1, - NTB_EPF_MAX_DB_COUNT + 1); + ret =3D ntb_epf_init_isr(ndev, NTB_EPF_MIN_DB_COUNT + NTB_EPF_IRQ_RESERVE, + NTB_EPF_MAX_DB_COUNT + NTB_EPF_IRQ_RESERVE); if (ret) { dev_err(dev, "Failed to init ISR\n"); return ret; @@ -659,7 +669,7 @@ static void ntb_epf_cleanup_isr(struct ntb_epf_dev *nde= v) =20 ntb_epf_send_command(ndev, CMD_TEARDOWN_DOORBELL, ndev->db_count + 1); =20 - for (i =3D 0; i < ndev->db_count + 1; i++) + for (i =3D 0; i < ndev->num_irqs; i++) free_irq(pci_irq_vector(pdev, i), ndev); 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charset="utf-8" Introduce struct ntb_transport_backend_ops to abstract queue setup and enqueue/poll operations. The existing implementation is moved behind this interface, and a subsequent patch will add an eDMA-backed implementation. No functional changes intended. Signed-off-by: Koichiro Den --- drivers/ntb/ntb_transport.c | 127 +++++++++++++++++++++++----------- include/linux/ntb_transport.h | 21 ++++++ 2 files changed, 106 insertions(+), 42 deletions(-) diff --git a/drivers/ntb/ntb_transport.c b/drivers/ntb/ntb_transport.c index dad596e3a405..907db6c93d4d 100644 --- a/drivers/ntb/ntb_transport.c +++ b/drivers/ntb/ntb_transport.c @@ -228,6 +228,8 @@ struct ntb_transport_ctx { =20 struct ntb_dev *ndev; =20 + struct ntb_transport_backend_ops backend_ops; + struct ntb_transport_mw *mw_vec; struct ntb_transport_qp *qp_vec; unsigned int mw_count; @@ -488,15 +490,9 @@ void ntb_transport_unregister_client(struct ntb_transp= ort_client *drv) } EXPORT_SYMBOL_GPL(ntb_transport_unregister_client); =20 -static int ntb_qp_debugfs_stats_show(struct seq_file *s, void *v) +static void ntb_transport_default_debugfs_stats_show(struct seq_file *s, + struct ntb_transport_qp *qp) { - struct ntb_transport_qp *qp =3D s->private; - - if (!qp || !qp->link_is_up) - return 0; - - seq_puts(s, "\nNTB QP stats:\n\n"); - seq_printf(s, "rx_bytes - \t%llu\n", qp->rx_bytes); seq_printf(s, "rx_pkts - \t%llu\n", qp->rx_pkts); seq_printf(s, "rx_memcpy - \t%llu\n", qp->rx_memcpy); @@ -526,6 +522,17 @@ static int ntb_qp_debugfs_stats_show(struct seq_file *= s, void *v) seq_printf(s, "Using TX DMA - \t%s\n", qp->tx_dma_chan ? "Yes" : "No"); seq_printf(s, "Using RX DMA - \t%s\n", qp->rx_dma_chan ? "Yes" : "No"); seq_printf(s, "QP Link - \t%s\n", qp->link_is_up ? "Up" : "Down"); +} + +static int ntb_qp_debugfs_stats_show(struct seq_file *s, void *v) +{ + struct ntb_transport_qp *qp =3D s->private; + + if (!qp || !qp->link_is_up) + return 0; + + seq_puts(s, "\nNTB QP stats:\n\n"); + qp->transport->backend_ops.debugfs_stats_show(s, qp); seq_putc(s, '\n'); =20 return 0; @@ -583,8 +590,8 @@ static struct ntb_queue_entry *ntb_list_mv(spinlock_t *= lock, return entry; } =20 -static int ntb_transport_setup_qp_mw(struct ntb_transport_ctx *nt, - unsigned int qp_num) +static int ntb_transport_default_setup_qp_mw(struct ntb_transport_ctx *nt, + unsigned int qp_num) { struct ntb_transport_qp *qp =3D &nt->qp_vec[qp_num]; struct ntb_transport_mw *mw; @@ -1128,7 +1135,7 @@ static void ntb_transport_link_work(struct work_struc= t *work) for (i =3D 0; i < nt->qp_count; i++) { struct ntb_transport_qp *qp =3D &nt->qp_vec[i]; =20 - ntb_transport_setup_qp_mw(nt, i); + nt->backend_ops.setup_qp_mw(nt, i); ntb_transport_setup_qp_peer_msi(nt, i); =20 if (qp->client_ready) @@ -1236,6 +1243,40 @@ static int ntb_transport_init_queue(struct ntb_trans= port_ctx *nt, return 0; } =20 +static unsigned int ntb_transport_default_tx_free_entry(struct ntb_transpo= rt_qp *qp) +{ + unsigned int head =3D qp->tx_index; + unsigned int tail =3D qp->remote_rx_info->entry; + + return tail >=3D head ? tail - head : qp->tx_max_entry + tail - head; +} + +static int ntb_transport_default_rx_enqueue(struct ntb_transport_qp *qp, + struct ntb_queue_entry *entry) +{ + ntb_list_add(&qp->ntb_rx_q_lock, &entry->entry, &qp->rx_pend_q); + + if (qp->active) + tasklet_schedule(&qp->rxc_db_work); + + return 0; +} + +static void ntb_transport_default_rx_poll(struct ntb_transport_qp *qp); +static int ntb_transport_default_tx_enqueue(struct ntb_transport_qp *qp, + struct ntb_queue_entry *entry, + void *cb, void *data, unsigned int len, + unsigned int flags); + +static const struct ntb_transport_backend_ops default_backend_ops =3D { + .setup_qp_mw =3D ntb_transport_default_setup_qp_mw, + .tx_free_entry =3D ntb_transport_default_tx_free_entry, + .tx_enqueue =3D ntb_transport_default_tx_enqueue, + .rx_enqueue =3D ntb_transport_default_rx_enqueue, + .rx_poll =3D ntb_transport_default_rx_poll, + .debugfs_stats_show =3D ntb_transport_default_debugfs_stats_show, +}; + static int ntb_transport_probe(struct ntb_client *self, struct ntb_dev *nd= ev) { struct ntb_transport_ctx *nt; @@ -1270,6 +1311,8 @@ static int ntb_transport_probe(struct ntb_client *sel= f, struct ntb_dev *ndev) =20 nt->ndev =3D ndev; =20 + nt->backend_ops =3D default_backend_ops; + /* * If we are using MSI, and have at least one extra memory window, * we will reserve the last MW for the MSI window. @@ -1679,14 +1722,10 @@ static int ntb_process_rxc(struct ntb_transport_qp = *qp) return 0; } =20 -static void ntb_transport_rxc_db(unsigned long data) +static void ntb_transport_default_rx_poll(struct ntb_transport_qp *qp) { - struct ntb_transport_qp *qp =3D (void *)data; int rc, i; =20 - dev_dbg(&qp->ndev->pdev->dev, "%s: doorbell %d received\n", - __func__, qp->qp_num); - /* Limit the number of packets processed in a single interrupt to * provide fairness to others */ @@ -1718,6 +1757,17 @@ static void ntb_transport_rxc_db(unsigned long data) } } =20 +static void ntb_transport_rxc_db(unsigned long data) +{ + struct ntb_transport_qp *qp =3D (void *)data; + struct ntb_transport_ctx *nt =3D qp->transport; + + dev_dbg(&qp->ndev->pdev->dev, "%s: doorbell %d received\n", + __func__, qp->qp_num); + + nt->backend_ops.rx_poll(qp); +} + static void ntb_tx_copy_callback(void *data, const struct dmaengine_result *res) { @@ -1887,9 +1937,18 @@ static void ntb_async_tx(struct ntb_transport_qp *qp, qp->tx_memcpy++; } =20 -static int ntb_process_tx(struct ntb_transport_qp *qp, - struct ntb_queue_entry *entry) +static int ntb_transport_default_tx_enqueue(struct ntb_transport_qp *qp, + struct ntb_queue_entry *entry, + void *cb, void *data, unsigned int len, + unsigned int flags) { + entry->cb_data =3D cb; + entry->buf =3D data; + entry->len =3D len; + entry->flags =3D flags; + entry->errors =3D 0; + entry->tx_index =3D 0; + if (!ntb_transport_tx_free_entry(qp)) { qp->tx_ring_full++; return -EAGAIN; @@ -1916,6 +1975,7 @@ static int ntb_process_tx(struct ntb_transport_qp *qp, =20 static void ntb_send_link_down(struct ntb_transport_qp *qp) { + struct ntb_transport_ctx *nt =3D qp->transport; struct pci_dev *pdev =3D qp->ndev->pdev; struct ntb_queue_entry *entry; int i, rc; @@ -1935,12 +1995,7 @@ static void ntb_send_link_down(struct ntb_transport_= qp *qp) if (!entry) return; =20 - entry->cb_data =3D NULL; - entry->buf =3D NULL; - entry->len =3D 0; - entry->flags =3D LINK_DOWN_FLAG; - - rc =3D ntb_process_tx(qp, entry); + rc =3D nt->backend_ops.tx_enqueue(qp, entry, NULL, NULL, 0, LINK_DOWN_FLA= G); if (rc) dev_err(&pdev->dev, "ntb: QP%d unable to send linkdown msg\n", qp->qp_num); @@ -2227,6 +2282,7 @@ EXPORT_SYMBOL_GPL(ntb_transport_rx_remove); int ntb_transport_rx_enqueue(struct ntb_transport_qp *qp, void *cb, void *= data, unsigned int len) { + struct ntb_transport_ctx *nt =3D qp->transport; struct ntb_queue_entry *entry; =20 if (!qp) @@ -2244,12 +2300,7 @@ int ntb_transport_rx_enqueue(struct ntb_transport_qp= *qp, void *cb, void *data, entry->errors =3D 0; entry->rx_index =3D 0; =20 - ntb_list_add(&qp->ntb_rx_q_lock, &entry->entry, &qp->rx_pend_q); - - if (qp->active) - tasklet_schedule(&qp->rxc_db_work); - - return 0; + return nt->backend_ops.rx_enqueue(qp, entry); } EXPORT_SYMBOL_GPL(ntb_transport_rx_enqueue); =20 @@ -2269,6 +2320,7 @@ EXPORT_SYMBOL_GPL(ntb_transport_rx_enqueue); int ntb_transport_tx_enqueue(struct ntb_transport_qp *qp, void *cb, void *= data, unsigned int len) { + struct ntb_transport_ctx *nt =3D qp->transport; struct ntb_queue_entry *entry; int rc; =20 @@ -2285,15 +2337,7 @@ int ntb_transport_tx_enqueue(struct ntb_transport_qp= *qp, void *cb, void *data, return -EBUSY; } =20 - entry->cb_data =3D cb; - entry->buf =3D data; - entry->len =3D len; - entry->flags =3D 0; - entry->errors =3D 0; - entry->retries =3D 0; - entry->tx_index =3D 0; - - rc =3D ntb_process_tx(qp, entry); + rc =3D nt->backend_ops.tx_enqueue(qp, entry, cb, data, len, 0); if (rc) ntb_list_add(&qp->ntb_tx_free_q_lock, &entry->entry, &qp->tx_free_q); @@ -2415,10 +2459,9 @@ EXPORT_SYMBOL_GPL(ntb_transport_max_size); =20 unsigned int ntb_transport_tx_free_entry(struct ntb_transport_qp *qp) { - unsigned int head =3D qp->tx_index; - unsigned int tail =3D qp->remote_rx_info->entry; + struct ntb_transport_ctx *nt =3D qp->transport; =20 - return tail >=3D head ? tail - head : qp->tx_max_entry + tail - head; + return nt->backend_ops.tx_free_entry(qp); } EXPORT_SYMBOL_GPL(ntb_transport_tx_free_entry); =20 diff --git a/include/linux/ntb_transport.h b/include/linux/ntb_transport.h index 7243eb98a722..297099d42370 100644 --- a/include/linux/ntb_transport.h +++ b/include/linux/ntb_transport.h @@ -49,6 +49,8 @@ */ =20 struct ntb_transport_qp; +struct ntb_transport_ctx; +struct ntb_queue_entry; =20 struct ntb_transport_client { struct device_driver driver; @@ -84,3 +86,22 @@ void ntb_transport_link_up(struct ntb_transport_qp *qp); void ntb_transport_link_down(struct ntb_transport_qp *qp); bool ntb_transport_link_query(struct ntb_transport_qp *qp); unsigned int ntb_transport_tx_free_entry(struct ntb_transport_qp *qp); + +/** + * struct ntb_transport_backend_ops - backend-specific transport hooks + * @setup_qp_mw: Set up memory windows for a given queue pair. + * @tx_free_entry: Return the number of free TX entries for the queue pai= r. + * @tx_enqueue: Backend-specific TX enqueue implementation. + * @rx_enqueue: Backend-specific RX enqueue implementation. + * @rx_poll: Poll for RX completions / push new RX buffers. + * @debugfs_stats_show: Dump backend-specific statistics, if any. + */ +struct ntb_transport_backend_ops { + int (*setup_qp_mw)(struct ntb_transport_ctx *nt, unsigned int qp_num); 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Sat, 29 Nov 2025 16:04:38 +0000 From: Koichiro Den To: ntb@lists.linux.dev, linux-pci@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Frank.Li@nxp.com Cc: mani@kernel.org, kwilczynski@kernel.org, kishon@kernel.org, bhelgaas@google.com, corbet@lwn.net, vkoul@kernel.org, jdmason@kudzu.us, dave.jiang@intel.com, allenbh@gmail.com, Basavaraj.Natikar@amd.com, Shyam-sundar.S-k@amd.com, kurt.schwemmer@microsemi.com, logang@deltatee.com, jingoohan1@gmail.com, lpieralisi@kernel.org, robh@kernel.org, jbrunet@baylibre.com, fancer.lancer@gmail.com, arnd@arndb.de, pstanner@redhat.com, elfring@users.sourceforge.net Subject: [RFC PATCH v2 19/27] PCI: dwc: ep: Cache MSI outbound iATU mapping Date: Sun, 30 Nov 2025 01:03:57 +0900 Message-ID: <20251129160405.2568284-20-den@valinux.co.jp> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20251129160405.2568284-1-den@valinux.co.jp> References: <20251129160405.2568284-1-den@valinux.co.jp> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: TYCP286CA0098.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:2b4::19) To TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:24c::11) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TYWP286MB2697:EE_|OS9P286MB4684:EE_ X-MS-Office365-Filtering-Correlation-Id: 84139169-70ac-4086-e09a-08de2f60ff7a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|366016|10070799003|1800799024; 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charset="utf-8" dw_pcie_ep_raise_msi_irq() currently programs an outbound iATU window for the MSI target address on every interrupt and tears it down again via dw_pcie_ep_unmap_addr(). On systems that heavily use the AXI bridge interface (for example when the integrated eDMA engine is active), this means the outbound iATU registers are updated while traffic is in flight. The DesignWare endpoint spec warns that updating iATU registers in this situation is not supported, and the behavior is undefined. Under high MSI and eDMA load this pattern results in occasional bogus outbound transactions and IOMMU faults such as: ipmmu-vmsa eed40000.iommu: Unhandled fault: status 0x00001502 iova 0xfe00= 0000 followed by the system becoming unresponsive. This is the actual output observed on Renesas R-Car S4, with its ipmmu_hc used with PCIe ch0. There is no need to reprogram the iATU region used for MSI on every interrupt. The host-provided MSI address is stable while MSI is enabled, and the endpoint driver already dedicates a scratch buffer for MSI generation. Cache the aligned MSI address and map size, program the outbound iATU once, and keep the window enabled. Subsequent interrupts only perform a write to the MSI scratch buffer, avoiding dynamic iATU reprogramming in the hot path and fixing the lockups seen under load. Signed-off-by: Koichiro Den --- .../pci/controller/dwc/pcie-designware-ep.c | 48 ++++++++++++++++--- drivers/pci/controller/dwc/pcie-designware.h | 5 ++ 2 files changed, 47 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/= controller/dwc/pcie-designware-ep.c index 3780a9bd6f79..ef8ded34d9ab 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -778,6 +778,16 @@ static void dw_pcie_ep_stop(struct pci_epc *epc) struct dw_pcie_ep *ep =3D epc_get_drvdata(epc); struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); =20 + /* + * Tear down the dedicated outbound window used for MSI + * generation. This avoids leaking an iATU window across + * endpoint stop/start cycles. + */ + if (ep->msi_iatu_mapped) { + dw_pcie_ep_unmap_addr(epc, 0, 0, ep->msi_mem_phys); + ep->msi_iatu_mapped =3D false; + } + dw_pcie_stop_link(pci); } =20 @@ -881,14 +891,37 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u= 8 func_no, msg_addr =3D ((u64)msg_addr_upper) << 32 | msg_addr_lower; =20 msg_addr =3D dw_pcie_ep_align_addr(epc, msg_addr, &map_size, &offset); - ret =3D dw_pcie_ep_map_addr(epc, func_no, 0, ep->msi_mem_phys, msg_addr, - map_size); - if (ret) - return ret; =20 - writel(msg_data | (interrupt_num - 1), ep->msi_mem + offset); + /* + * Program the outbound iATU once and keep it enabled. + * + * The spec warns that updating iATU registers while there are + * operations in flight on the AXI bridge interface is not + * supported, so we avoid reprogramming the region on every MSI, + * specifically unmapping immediately after writel(). + */ + if (!ep->msi_iatu_mapped) { + ret =3D dw_pcie_ep_map_addr(epc, func_no, 0, + ep->msi_mem_phys, msg_addr, + map_size); + if (ret) + return ret; =20 - dw_pcie_ep_unmap_addr(epc, func_no, 0, ep->msi_mem_phys); + ep->msi_iatu_mapped =3D true; + ep->msi_msg_addr =3D msg_addr; + ep->msi_map_size =3D map_size; + } else if (WARN_ON_ONCE(ep->msi_msg_addr !=3D msg_addr || + ep->msi_map_size !=3D map_size)) { + /* + * The host changed the MSI target address or the required + * mapping size. Reprogramming the iATU at runtime is unsafe + * on this controller, so bail out instead of trying to update + * the existing region. + */ + return -EINVAL; + } + + writel(msg_data | (interrupt_num - 1), ep->msi_mem + offset); =20 return 0; } @@ -1268,6 +1301,9 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) INIT_LIST_HEAD(&ep->func_list); INIT_LIST_HEAD(&ep->ib_map_list); spin_lock_init(&ep->ib_map_lock); + ep->msi_iatu_mapped =3D false; + ep->msi_msg_addr =3D 0; + ep->msi_map_size =3D 0; =20 epc =3D devm_pci_epc_create(dev, &epc_ops); if (IS_ERR(epc)) { diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index 269a9fe0501f..1770a2318557 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -481,6 +481,11 @@ struct dw_pcie_ep { void __iomem *msi_mem; phys_addr_t msi_mem_phys; struct pci_epf_bar *epf_bar[PCI_STD_NUM_BARS]; + + /* MSI outbound iATU state */ + bool msi_iatu_mapped; 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b=fnPbNYGdg/6Tx9H+jOaHt9HCNvLWEUQgOODNtD4js0cMUtiGrJQVdsaNXl1BodQRdZZz7qNiS+GuibepUW8RvnSIwK5XumIrRDoDpmcNSRfAyHzYsSjgdvmp8YadeF30hR3za1gz3wknGDU/TGIR9qY83s9BsGjs//GD1tOARC8= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=valinux.co.jp; Received: from TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:24c::11) by OS9P286MB4684.JPNP286.PROD.OUTLOOK.COM (2603:1096:604:2fa::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9366.17; Sat, 29 Nov 2025 16:04:39 +0000 Received: from TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM ([fe80::fb7e:f4ed:a580:9d03]) by TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM ([fe80::fb7e:f4ed:a580:9d03%5]) with mapi id 15.20.9366.012; Sat, 29 Nov 2025 16:04:39 +0000 From: Koichiro Den To: ntb@lists.linux.dev, linux-pci@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Frank.Li@nxp.com Cc: mani@kernel.org, kwilczynski@kernel.org, kishon@kernel.org, bhelgaas@google.com, corbet@lwn.net, vkoul@kernel.org, jdmason@kudzu.us, dave.jiang@intel.com, allenbh@gmail.com, Basavaraj.Natikar@amd.com, Shyam-sundar.S-k@amd.com, kurt.schwemmer@microsemi.com, logang@deltatee.com, jingoohan1@gmail.com, lpieralisi@kernel.org, robh@kernel.org, jbrunet@baylibre.com, fancer.lancer@gmail.com, arnd@arndb.de, pstanner@redhat.com, elfring@users.sourceforge.net Subject: [RFC PATCH v2 20/27] NTB: ntb_transport: Introduce remote eDMA backed transport mode Date: Sun, 30 Nov 2025 01:03:58 +0900 Message-ID: <20251129160405.2568284-21-den@valinux.co.jp> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20251129160405.2568284-1-den@valinux.co.jp> References: <20251129160405.2568284-1-den@valinux.co.jp> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: TY4P286CA0036.JPNP286.PROD.OUTLOOK.COM (2603:1096:405:2b2::17) To TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:24c::11) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TYWP286MB2697:EE_|OS9P286MB4684:EE_ X-MS-Office365-Filtering-Correlation-Id: 688de064-4d82-41c1-2565-08de2f60fffc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|366016|10070799003|1800799024; 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charset="utf-8" Add a new transport backend that uses a remote DesignWare eDMA engine located on the NTB endpoint to move data between host and endpoint. In this mode: - The endpoint exposes a dedicated memory window that contains the eDMA register block followed by a small control structure (struct ntb_edma_info) and per-channel linked-list (LL) rings. - On the endpoint side, ntb_edma_setup_mws() allocates the control structure and LL rings in endpoint memory, then programs an inbound iATU region so that the host can access them via a peer MW. - On the host side, ntb_edma_setup_peer() ioremaps the peer MW, reads ntb_edma_info and configures a dw-edma DMA device to use the LL rings provided by the endpoint. - ntb_transport is extended with a new backend_ops implementation that routes TX and RX enqueue/poll operations through the remote eDMA rings while keeping the existing shared-memory backend intact. - The host signals the endpoint via a dedicated DMA read channel. 'use_msi' module option is ignored when 'use_remote_edma=3D1'. The new mode is guarded by a Kconfig option (NTB_TRANSPORT_EDMA) and a module parameter (use_remote_edma). When disabled, the existing ntb_transport behaviour is unchanged. Signed-off-by: Koichiro Den --- drivers/ntb/Kconfig | 11 + drivers/ntb/Makefile | 3 + drivers/ntb/ntb_edma.c | 628 ++++++++ drivers/ntb/ntb_edma.h | 128 ++ .../{ntb_transport.c =3D> ntb_transport_core.c} | 1281 ++++++++++++++++- 5 files changed, 2048 insertions(+), 3 deletions(-) create mode 100644 drivers/ntb/ntb_edma.c create mode 100644 drivers/ntb/ntb_edma.h rename drivers/ntb/{ntb_transport.c =3D> ntb_transport_core.c} (65%) diff --git a/drivers/ntb/Kconfig b/drivers/ntb/Kconfig index df16c755b4da..db63f02bb116 100644 --- a/drivers/ntb/Kconfig +++ b/drivers/ntb/Kconfig @@ -37,4 +37,15 @@ config NTB_TRANSPORT =20 If unsure, say N. =20 +config NTB_TRANSPORT_EDMA + bool "NTB Transport backed by remote eDMA" + depends on NTB_TRANSPORT + depends on PCI + select DMA_ENGINE + help + Enable a transport backend that uses a remote DesignWare eDMA engine + exposed through a dedicated NTB memory window. The host uses the + endpoint's eDMA engine to move data in both directions. + Say Y here if you intend to use the 'use_remote_edma' module parameter. + endif # NTB diff --git a/drivers/ntb/Makefile b/drivers/ntb/Makefile index 3a6fa181ff99..51f0e1e3aec7 100644 --- a/drivers/ntb/Makefile +++ b/drivers/ntb/Makefile @@ -4,3 +4,6 @@ obj-$(CONFIG_NTB_TRANSPORT) +=3D ntb_transport.o =20 ntb-y :=3D core.o ntb-$(CONFIG_NTB_MSI) +=3D msi.o + +ntb_transport-y :=3D ntb_transport_core.o +ntb_transport-$(CONFIG_NTB_TRANSPORT_EDMA) +=3D ntb_edma.o diff --git a/drivers/ntb/ntb_edma.c b/drivers/ntb/ntb_edma.c new file mode 100644 index 000000000000..cb35e0d56aa8 --- /dev/null +++ b/drivers/ntb/ntb_edma.c @@ -0,0 +1,628 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ntb_edma.h" + +/* + * The interrupt register offsets below are taken from the DesignWare + * eDMA "unrolled" register map (EDMA_MF_EDMA_UNROLL). The remote eDMA + * backend currently only supports this layout. + */ +#define DMA_WRITE_INT_STATUS_OFF 0x4c +#define DMA_WRITE_INT_MASK_OFF 0x54 +#define DMA_WRITE_INT_CLEAR_OFF 0x58 +#define DMA_READ_INT_STATUS_OFF 0xa0 +#define DMA_READ_INT_MASK_OFF 0xa8 +#define DMA_READ_INT_CLEAR_OFF 0xac + +#define NTB_EDMA_NOTIFY_MAX_QP 64 + +static unsigned int edma_spi =3D 417; /* 0x1a1 */ +module_param(edma_spi, uint, 0644); +MODULE_PARM_DESC(edma_spi, "SPI number used by remote eDMA interrupt (EP l= ocal)"); + +static u64 edma_regs_phys =3D 0xe65d5000; +module_param(edma_regs_phys, ullong, 0644); +MODULE_PARM_DESC(edma_regs_phys, "Physical base address of local eDMA regi= sters (EP)"); + +static unsigned long edma_regs_size =3D 0x1200; +module_param(edma_regs_size, ulong, 0644); +MODULE_PARM_DESC(edma_regs_size, "Size of the local eDMA register space (E= P)"); + +struct ntb_edma_intr { + u32 db[NTB_EDMA_NOTIFY_MAX_QP]; +}; + +struct ntb_edma_ctx { + void *ll_wr_virt[EDMA_WR_CH_NUM]; + dma_addr_t ll_wr_phys[EDMA_WR_CH_NUM]; + void *ll_rd_virt[EDMA_RD_CH_NUM + 1]; + dma_addr_t ll_rd_phys[EDMA_RD_CH_NUM + 1]; + + struct ntb_edma_intr *intr_ep_virt; + dma_addr_t intr_ep_phys; + struct ntb_edma_intr *intr_rc_virt; + dma_addr_t intr_rc_phys; + u32 notify_qp_max; + + bool initialized; +}; + +static struct ntb_edma_ctx edma_ctx; + +typedef void (*ntb_edma_interrupt_cb_t)(void *data, int qp_num); + +struct ntb_edma_interrupt { + int virq; + void __iomem *base; + ntb_edma_interrupt_cb_t cb; + void *data; +}; + +static struct ntb_edma_interrupt ntb_edma_intr; + +static int ntb_edma_map_spi_to_virq(struct device *dev, unsigned int spi) +{ + struct device_node *np =3D dev_of_node(dev); + struct device_node *parent; + struct irq_fwspec fwspec =3D { 0 }; + int virq; + + parent =3D of_irq_find_parent(np); + if (!parent) + return -ENODEV; + + fwspec.fwnode =3D of_fwnode_handle(parent); + fwspec.param_count =3D 3; + fwspec.param[0] =3D GIC_SPI; + fwspec.param[1] =3D spi; + fwspec.param[2] =3D IRQ_TYPE_LEVEL_HIGH; + + virq =3D irq_create_fwspec_mapping(&fwspec); + of_node_put(parent); + return (virq > 0) ? virq : -EINVAL; +} + +static irqreturn_t ntb_edma_isr(int irq, void *data) +{ + struct ntb_edma_interrupt *v =3D data; + u32 mask =3D BIT(EDMA_RD_CH_NUM); + u32 i, val; + + /* + * We do not ack interrupts here but instead we mask all local interrupt + * sources except the read channel used for notification. This reduces + * needless ISR invocations. + * + * In theory we could configure LIE=3D1/RIE=3D0 only for the notification + * transfer (keeping all other channels at LIE=3D1/RIE=3D1), but that wou= ld + * require intrusive changes to the dw-edma core. + * + * Note: The host side may have already cleared the read interrupt used + * for notification, so reading DMA_READ_INT_CLEAR_OFF is not a reliable + * way to detect it. As a result, we cannot reliably tell which specific + * channel triggered this interrupt. intr_ep_virt->db[i] teaches us + * instead. + */ + iowrite32(~0x0, v->base + DMA_WRITE_INT_MASK_OFF); + iowrite32(~mask, v->base + DMA_READ_INT_MASK_OFF); + + if (!v->cb || !edma_ctx.intr_ep_virt) + return IRQ_HANDLED; + + for (i =3D 0; i < edma_ctx.notify_qp_max; i++) { + val =3D READ_ONCE(edma_ctx.intr_ep_virt->db[i]); + if (!val) + continue; + + WRITE_ONCE(edma_ctx.intr_ep_virt->db[i], 0); + v->cb(v->data, i); + } + + return IRQ_HANDLED; +} + +int ntb_edma_setup_isr(struct device *dev, struct device *epc_dev, + ntb_edma_interrupt_cb_t cb, void *data) +{ + struct ntb_edma_interrupt *v =3D &ntb_edma_intr; + int virq =3D ntb_edma_map_spi_to_virq(epc_dev->parent, edma_spi); + int ret; + + if (virq < 0) { + dev_err(dev, "failed to get virq (%d)\n", virq); + return virq; + } + + v->virq =3D virq; + v->cb =3D cb; + v->data =3D data; + if (edma_regs_phys && !v->base) + v->base =3D devm_ioremap(dev, edma_regs_phys, edma_regs_size); + if (!v->base) { + dev_err(dev, "failed to setup v->base\n"); + return -1; + } + ret =3D devm_request_irq(dev, v->virq, ntb_edma_isr, 0, "ntb-edma", v); + if (ret) + return ret; + + if (v->base) { + iowrite32(0x0, v->base + DMA_WRITE_INT_MASK_OFF); + iowrite32(0x0, v->base + DMA_READ_INT_MASK_OFF); + } + return 0; +} + +void ntb_edma_teardown_isr(struct device *dev) +{ + struct ntb_edma_interrupt *v =3D &ntb_edma_intr; + + /* Mask all write/read interrupts so we don't get called again. */ + if (v->base) { + iowrite32(~0x0, v->base + DMA_WRITE_INT_MASK_OFF); + iowrite32(~0x0, v->base + DMA_READ_INT_MASK_OFF); + } + + if (v->virq > 0) + devm_free_irq(dev, v->virq, v); + + if (v->base) + devm_iounmap(dev, v->base); + + v->virq =3D 0; + v->cb =3D NULL; + v->data =3D NULL; +} + +int ntb_edma_setup_mws(struct ntb_dev *ndev) +{ + const size_t info_bytes =3D PAGE_SIZE; + resource_size_t size_max, offset; + dma_addr_t intr_phys, info_phys; + u32 wr_done =3D 0, rd_done =3D 0; + struct ntb_edma_intr *intr; + struct ntb_edma_info *info; + int peer_mw, mw_index, rc; + struct iommu_domain *dom; + bool reg_mapped =3D false; + size_t ll_bytes, size; + struct pci_epc *epc; + struct device *dev; + unsigned long iova; + phys_addr_t phys; + u64 need; + u32 i; + + /* +1 is for interruption */ + ll_bytes =3D (EDMA_WR_CH_NUM + EDMA_RD_CH_NUM + 1) * DMA_LLP_MEM_SIZE; + need =3D EDMA_REG_SIZE + info_bytes + ll_bytes; + + epc =3D ntb_get_pci_epc(ndev); + if (!epc) + return -ENODEV; + dev =3D epc->dev.parent; + + if (edma_ctx.initialized) + return 0; + + info =3D dma_alloc_coherent(dev, info_bytes, &info_phys, GFP_KERNEL); + if (!info) + return -ENOMEM; + + memset(info, 0, info_bytes); + info->magic =3D NTB_EDMA_INFO_MAGIC; + info->wr_cnt =3D EDMA_WR_CH_NUM; + info->rd_cnt =3D EDMA_RD_CH_NUM + 1; /* +1 for interruption */ + info->regs_phys =3D edma_regs_phys; + info->ll_stride =3D DMA_LLP_MEM_SIZE; + + for (i =3D 0; i < EDMA_WR_CH_NUM; i++) { + edma_ctx.ll_wr_virt[i] =3D dma_alloc_attrs(dev, DMA_LLP_MEM_SIZE, + &edma_ctx.ll_wr_phys[i], + GFP_KERNEL, + DMA_ATTR_FORCE_CONTIGUOUS); + if (!edma_ctx.ll_wr_virt[i]) { + rc =3D -ENOMEM; + goto err_free_ll; + } + wr_done++; + info->ll_wr_phys[i] =3D edma_ctx.ll_wr_phys[i]; + } + for (i =3D 0; i < EDMA_RD_CH_NUM + 1; i++) { + edma_ctx.ll_rd_virt[i] =3D dma_alloc_attrs(dev, DMA_LLP_MEM_SIZE, + &edma_ctx.ll_rd_phys[i], + GFP_KERNEL, + DMA_ATTR_FORCE_CONTIGUOUS); + if (!edma_ctx.ll_rd_virt[i]) { + rc =3D -ENOMEM; + goto err_free_ll; + } + rd_done++; + info->ll_rd_phys[i] =3D edma_ctx.ll_rd_phys[i]; + } + + /* For interruption */ + edma_ctx.notify_qp_max =3D NTB_EDMA_NOTIFY_MAX_QP; + intr =3D dma_alloc_coherent(dev, sizeof(*intr), &intr_phys, GFP_KERNEL); + if (!intr) { + rc =3D -ENOMEM; + goto err_free_ll; + } + memset(intr, 0, sizeof(*intr)); + edma_ctx.intr_ep_virt =3D intr; + edma_ctx.intr_ep_phys =3D intr_phys; + info->intr_dar_base =3D intr_phys; + + peer_mw =3D ntb_peer_mw_count(ndev); + if (peer_mw <=3D 0) { + rc =3D -ENODEV; + goto err_free_ll; + } + + mw_index =3D peer_mw - 1; /* last MW */ + + rc =3D ntb_mw_get_align(ndev, 0, mw_index, 0, NULL, &size_max, + &offset); + if (rc) + goto err_free_ll; + + if (size_max < need) { + rc =3D -ENOSPC; + goto err_free_ll; + } + + /* Map register space (direct) */ + dom =3D iommu_get_domain_for_dev(dev); + if (dom) { + phys =3D edma_regs_phys & PAGE_MASK; + size =3D PAGE_ALIGN(EDMA_REG_SIZE + edma_regs_phys - phys); + iova =3D phys; + + rc =3D iommu_map(dom, iova, phys, EDMA_REG_SIZE, + IOMMU_READ | IOMMU_WRITE | IOMMU_MMIO, GFP_KERNEL); + if (rc) + dev_err(&ndev->dev, "failed to create direct mapping for eDMA reg space= \n"); + reg_mapped =3D true; + } + + rc =3D ntb_mw_set_trans(ndev, 0, mw_index, edma_regs_phys, EDMA_REG_SIZE,= offset); + if (rc) + goto err_unmap_reg; + + offset +=3D EDMA_REG_SIZE; + + /* Map ntb_edma_info */ + rc =3D ntb_mw_set_trans(ndev, 0, mw_index, info_phys, info_bytes, offset); + if (rc) + goto err_clear_trans; + offset +=3D info_bytes; + + /* Map LL location */ + for (i =3D 0; i < EDMA_WR_CH_NUM; i++) { + rc =3D ntb_mw_set_trans(ndev, 0, mw_index, edma_ctx.ll_wr_phys[i], + DMA_LLP_MEM_SIZE, offset); + if (rc) + goto err_clear_trans; + offset +=3D DMA_LLP_MEM_SIZE; + } + for (i =3D 0; i < EDMA_RD_CH_NUM + 1; i++) { + rc =3D ntb_mw_set_trans(ndev, 0, mw_index, edma_ctx.ll_rd_phys[i], + DMA_LLP_MEM_SIZE, offset); + if (rc) + goto err_clear_trans; + offset +=3D DMA_LLP_MEM_SIZE; + } + edma_ctx.initialized =3D true; + + return 0; + +err_clear_trans: + /* + * Tear down the NTB translation window used for the eDMA MW. + * There is no sub-range clear API for ntb_mw_set_trans(), so we + * unconditionally drop the whole mapping on error. + */ + ntb_mw_clear_trans(ndev, 0, mw_index); + +err_unmap_reg: + if (reg_mapped) + iommu_unmap(dom, iova, size); +err_free_ll: + while (rd_done--) + dma_free_attrs(dev, DMA_LLP_MEM_SIZE, + edma_ctx.ll_rd_virt[rd_done], + edma_ctx.ll_rd_phys[rd_done], + DMA_ATTR_FORCE_CONTIGUOUS); + while (wr_done--) + dma_free_attrs(dev, DMA_LLP_MEM_SIZE, + edma_ctx.ll_wr_virt[wr_done], + edma_ctx.ll_wr_phys[wr_done], + DMA_ATTR_FORCE_CONTIGUOUS); + if (edma_ctx.intr_ep_virt) + dma_free_coherent(dev, sizeof(struct ntb_edma_intr), + edma_ctx.intr_ep_virt, + edma_ctx.intr_ep_phys); + dma_free_coherent(dev, info_bytes, info, info_phys); + return rc; +} + +static int ntb_edma_irq_vector(struct device *dev, unsigned int nr) +{ + struct pci_dev *pdev =3D to_pci_dev(dev); + int ret, nvec; + + nvec =3D pci_msi_vec_count(pdev); + for (; nr < nvec; nr++) { + ret =3D pci_irq_vector(pdev, nr); + if (!irq_has_action(ret)) + return ret; + } + return 0; +} + +static const struct dw_edma_plat_ops ntb_edma_ops =3D { + .irq_vector =3D ntb_edma_irq_vector, +}; + +int ntb_edma_setup_peer(struct ntb_dev *ndev) +{ + struct ntb_edma_info *info; + unsigned int wr_cnt, rd_cnt; + struct dw_edma_chip *chip; + void __iomem *edma_virt; + phys_addr_t edma_phys; + resource_size_t mw_size; + u64 off =3D EDMA_REG_SIZE; + int peer_mw, mw_index; + unsigned int i; + int ret; + + peer_mw =3D ntb_peer_mw_count(ndev); + if (peer_mw <=3D 0) + return -ENODEV; + + mw_index =3D peer_mw - 1; /* last MW */ + + ret =3D ntb_peer_mw_get_addr(ndev, mw_index, &edma_phys, + &mw_size); + if (ret) + return -1; + + edma_virt =3D ioremap(edma_phys, mw_size); + + chip =3D devm_kzalloc(&ndev->dev, sizeof(*chip), GFP_KERNEL); + if (!chip) { + ret =3D -ENOMEM; + return ret; + } + + chip->dev =3D &ndev->pdev->dev; + chip->nr_irqs =3D 4; + chip->ops =3D &ntb_edma_ops; + chip->flags =3D 0; + chip->reg_base =3D edma_virt; + chip->mf =3D EDMA_MF_EDMA_UNROLL; + + info =3D edma_virt + off; + if (info->magic !=3D NTB_EDMA_INFO_MAGIC) + return -EINVAL; + wr_cnt =3D info->wr_cnt; + rd_cnt =3D info->rd_cnt; + chip->ll_wr_cnt =3D wr_cnt; + chip->ll_rd_cnt =3D rd_cnt; + off +=3D PAGE_SIZE; + + edma_ctx.notify_qp_max =3D NTB_EDMA_NOTIFY_MAX_QP; + edma_ctx.intr_ep_phys =3D info->intr_dar_base; + if (edma_ctx.intr_ep_phys) { + edma_ctx.intr_rc_virt =3D + dma_alloc_coherent(&ndev->pdev->dev, + sizeof(struct ntb_edma_intr), + &edma_ctx.intr_rc_phys, + GFP_KERNEL); + if (!edma_ctx.intr_rc_virt) + return -ENOMEM; + memset(edma_ctx.intr_rc_virt, 0, + sizeof(struct ntb_edma_intr)); + } + + for (i =3D 0; i < wr_cnt; i++) { + chip->ll_region_wr[i].vaddr.io =3D edma_virt + off; + chip->ll_region_wr[i].paddr =3D info->ll_wr_phys[i]; + chip->ll_region_wr[i].sz =3D DMA_LLP_MEM_SIZE; + off +=3D DMA_LLP_MEM_SIZE; + } + for (i =3D 0; i < rd_cnt; i++) { + chip->ll_region_rd[i].vaddr.io =3D edma_virt + off; + chip->ll_region_rd[i].paddr =3D info->ll_rd_phys[i]; + chip->ll_region_rd[i].sz =3D DMA_LLP_MEM_SIZE; + off +=3D DMA_LLP_MEM_SIZE; + } + + if (!pci_dev_msi_enabled(ndev->pdev)) + return -ENXIO; + + ret =3D dw_edma_probe(chip); + if (ret) { + dev_err(&ndev->dev, "dw_edma_probe failed: %d\n", ret); + return ret; + } + + return 0; +} + +struct ntb_edma_filter { + struct device *dma_dev; + u32 direction; +}; + +static bool ntb_edma_filter_fn(struct dma_chan *chan, void *arg) +{ + struct ntb_edma_filter *filter =3D arg; + u32 dir =3D filter->direction; + struct dma_slave_caps caps; + int ret; + + if (chan->device->dev !=3D filter->dma_dev) + return false; + + ret =3D dma_get_slave_caps(chan, &caps); + if (ret < 0) + return false; + + return !!(caps.directions & dir); +} + +void ntb_edma_teardown_chans(struct ntb_edma_chans *edma) +{ + unsigned int i; + + for (i =3D 0; i < edma->num_wr_chan; i++) + dma_release_channel(edma->wr_chan[i]); + + for (i =3D 0; i < edma->num_rd_chan; i++) + dma_release_channel(edma->rd_chan[i]); + + if (edma->intr_chan) + dma_release_channel(edma->intr_chan); +} + +int ntb_edma_setup_chans(struct device *dma_dev, struct ntb_edma_chans *ed= ma) +{ + struct ntb_edma_filter filter; + dma_cap_mask_t dma_mask; + unsigned int i; + + dma_cap_zero(dma_mask); + dma_cap_set(DMA_SLAVE, dma_mask); + + memset(edma, 0, sizeof(*edma)); + edma->dev =3D dma_dev; + + filter.dma_dev =3D dma_dev; + filter.direction =3D BIT(DMA_DEV_TO_MEM); + for (i =3D 0; i < EDMA_WR_CH_NUM; i++) { + edma->wr_chan[i] =3D dma_request_channel(dma_mask, + ntb_edma_filter_fn, + &filter); + if (!edma->wr_chan[i]) + break; + edma->num_wr_chan++; + } + + filter.direction =3D BIT(DMA_MEM_TO_DEV); + for (i =3D 0; i < EDMA_RD_CH_NUM; i++) { + edma->rd_chan[i] =3D dma_request_channel(dma_mask, + ntb_edma_filter_fn, + &filter); + if (!edma->rd_chan[i]) + break; + edma->num_rd_chan++; + } + + edma->intr_chan =3D dma_request_channel(dma_mask, ntb_edma_filter_fn, + &filter); + if (!edma->intr_chan) + dev_warn(dma_dev, + "Remote eDMA notify channel could not be allocated\n"); + + if (!edma->num_wr_chan || !edma->num_rd_chan) { + dev_warn(dma_dev, "Remote eDMA channels failed to initialize\n"); + ntb_edma_teardown_chans(edma); + return -ENODEV; + } + return 0; +} + +struct dma_chan *ntb_edma_pick_chan(struct ntb_edma_chans *edma, + remote_edma_dir_t dir) +{ + unsigned int n, cur, idx; + struct dma_chan **chans; + atomic_t *cur_chan; + + if (dir =3D=3D REMOTE_EDMA_WRITE) { + n =3D edma->num_wr_chan; + chans =3D edma->wr_chan; + cur_chan =3D &edma->cur_wr_chan; + } else { + n =3D edma->num_rd_chan; + chans =3D edma->rd_chan; + cur_chan =3D &edma->cur_rd_chan; + } + if (WARN_ON_ONCE(!n)) + return NULL; + + /* Simple round-robin */ + cur =3D (unsigned int)atomic_inc_return(cur_chan) - 1; + idx =3D cur % n; + return chans[idx]; +} + +int ntb_edma_notify_peer(struct ntb_edma_chans *edma, int qp_num) +{ + struct dma_async_tx_descriptor *txd; + struct dma_slave_config cfg; + struct scatterlist sgl; + dma_cookie_t cookie; + struct device *dev; + + if (!edma || !edma->intr_chan) + return -ENXIO; + + if (qp_num < 0 || qp_num >=3D edma_ctx.notify_qp_max) + return -EINVAL; + + if (!edma_ctx.intr_rc_virt || !edma_ctx.intr_ep_phys) + return -EINVAL; + + dev =3D edma->dev; + if (!dev) + return -ENODEV; + + WRITE_ONCE(edma_ctx.intr_rc_virt->db[qp_num], 1); + + /* Ensure store is visible before kicking the DMA transfer */ + wmb(); + + sg_init_table(&sgl, 1); + sg_dma_address(&sgl) =3D edma_ctx.intr_rc_phys + qp_num * sizeof(u32); + sg_dma_len(&sgl) =3D sizeof(u32); + + memset(&cfg, 0, sizeof(cfg)); + cfg.dst_addr =3D edma_ctx.intr_ep_phys + qp_num * sizeof(u32); + cfg.src_addr_width =3D DMA_SLAVE_BUSWIDTH_4_BYTES; + cfg.dst_addr_width =3D DMA_SLAVE_BUSWIDTH_4_BYTES; + cfg.direction =3D DMA_MEM_TO_DEV; + + if (dmaengine_slave_config(edma->intr_chan, &cfg)) + return -EINVAL; + + txd =3D dmaengine_prep_slave_sg(edma->intr_chan, &sgl, 1, + DMA_MEM_TO_DEV, + DMA_CTRL_ACK | DMA_PREP_INTERRUPT); + if (!txd) + return -ENOSPC; + + cookie =3D dmaengine_submit(txd); + if (dma_submit_error(cookie)) + return -ENOSPC; + + dma_async_issue_pending(edma->intr_chan); + return 0; +} diff --git a/drivers/ntb/ntb_edma.h b/drivers/ntb/ntb_edma.h new file mode 100644 index 000000000000..da0451827edb --- /dev/null +++ b/drivers/ntb/ntb_edma.h @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ +#ifndef _NTB_EDMA_H_ +#define _NTB_EDMA_H_ + +#include +#include +#include + +#define EDMA_REG_SIZE SZ_64K +#define DMA_LLP_MEM_SIZE SZ_4K +#define EDMA_WR_CH_NUM 4 +#define EDMA_RD_CH_NUM 4 +#define NTB_EDMA_MAX_CH 8 + +#define NTB_EDMA_INFO_MAGIC 0x45444D41 /* "EDMA" */ +#define NTB_EDMA_INFO_OFF EDMA_REG_SIZE + +#define NTB_EDMA_RING_ORDER 7 +#define NTB_EDMA_RING_ENTRIES (1U << NTB_EDMA_RING_ORDER) +#define NTB_EDMA_RING_MASK (NTB_EDMA_RING_ENTRIES - 1) + +typedef void (*ntb_edma_interrupt_cb_t)(void *data, int qp_num); + +/* + * REMOTE_EDMA_EP: + * Endpoint owns the eDMA engine and pushes descriptors into a shared MW. + * + * REMOTE_EDMA_RC: + * Root Complex controls the endpoint eDMA through the shared MW and + * drives reads/writes on behalf of the host. + */ +typedef enum { + REMOTE_EDMA_UNKNOWN, + REMOTE_EDMA_EP, + REMOTE_EDMA_RC, +} remote_edma_mode_t; + +typedef enum { + REMOTE_EDMA_WRITE, + REMOTE_EDMA_READ, +} remote_edma_dir_t; + +/* + * Layout of remote eDMA MW (EP local address space, RC sees via peer MW): + * + * 0 .. EDMA_REG_SIZE-1 : DesignWare eDMA registers + * EDMA_REG_SIZE .. +PAGE_SIZE : struct ntb_edma_info (EP writes, RC read= s) + * +PAGE_SIZE .. : LL ring buffers (EP allocates phys addre= sses, + * RC configures via dw_edma) + * + * ntb_edma_setup_mws() on EP: + * - allocates ntb_edma_info and LLs in EP memory + * - programs inbound iATU so that RC peer MW[n] points at this block + * + * ntb_edma_setup_peer() on RC: + * - ioremaps peer MW[n] + * - reads ntb_edma_info + * - sets up dw_edma_chip ll_region_* from that info + */ +struct ntb_edma_info { + u32 magic; + u16 wr_cnt; + u16 rd_cnt; + u64 regs_phys; + u32 ll_stride; + u32 rsvd; + u64 ll_wr_phys[NTB_EDMA_MAX_CH]; + u64 ll_rd_phys[NTB_EDMA_MAX_CH]; + + u64 intr_dar_base; +} __packed; + +struct ll_dma_addrs { + dma_addr_t wr[EDMA_WR_CH_NUM]; + dma_addr_t rd[EDMA_RD_CH_NUM]; +}; + +struct ntb_edma_chans { + struct device *dev; + + struct dma_chan *wr_chan[EDMA_WR_CH_NUM]; + struct dma_chan *rd_chan[EDMA_RD_CH_NUM]; + struct dma_chan *intr_chan; + + unsigned int num_wr_chan; + unsigned int num_rd_chan; + atomic_t cur_wr_chan; + atomic_t cur_rd_chan; +}; + +static __always_inline u32 ntb_edma_ring_idx(u32 v) +{ + return v & NTB_EDMA_RING_MASK; +} + +static __always_inline u32 ntb_edma_ring_used_entry(u32 head, u32 tail) +{ + if (head >=3D tail) { + WARN_ON_ONCE((head - tail) > (NTB_EDMA_RING_ENTRIES - 1)); + return head - tail; + } + + WARN_ON_ONCE((U32_MAX - tail + head + 1) > (NTB_EDMA_RING_ENTRIES - 1)); + return U32_MAX - tail + head + 1; +} + +static __always_inline u32 ntb_edma_ring_free_entry(u32 head, u32 tail) +{ + return NTB_EDMA_RING_ENTRIES - ntb_edma_ring_used_entry(head, tail) - 1; +} + +static __always_inline bool ntb_edma_ring_full(u32 head, u32 tail) +{ + return ntb_edma_ring_free_entry(head, tail) =3D=3D 0; +} + +int ntb_edma_setup_isr(struct device *dev, struct device *epc_dev, + ntb_edma_interrupt_cb_t cb, void *data); +void ntb_edma_teardown_isr(struct device *dev); +int ntb_edma_setup_mws(struct ntb_dev *ndev); +int ntb_edma_setup_peer(struct ntb_dev *ndev); +int ntb_edma_setup_chans(struct device *dma_dev, struct ntb_edma_chans *ed= ma); +struct dma_chan *ntb_edma_pick_chan(struct ntb_edma_chans *edma, + remote_edma_dir_t dir); +void ntb_edma_teardown_chans(struct ntb_edma_chans *edma); +int ntb_edma_notify_peer(struct ntb_edma_chans *edma, int qp_num); + +#endif diff --git a/drivers/ntb/ntb_transport.c b/drivers/ntb/ntb_transport_core.c similarity index 65% rename from drivers/ntb/ntb_transport.c rename to drivers/ntb/ntb_transport_core.c index 907db6c93d4d..48d48921978d 100644 --- a/drivers/ntb/ntb_transport.c +++ b/drivers/ntb/ntb_transport_core.c @@ -47,6 +47,9 @@ * Contact Information: * Jon Mason */ +#include +#include +#include #include #include #include @@ -71,6 +74,8 @@ #define NTB_TRANSPORT_DESC "Software Queue-Pair Transport over NTB" #define NTB_TRANSPORT_MIN_SPADS (MW0_SZ_HIGH + 2) =20 +#define NTB_EDMA_MAX_POLL 32 + MODULE_DESCRIPTION(NTB_TRANSPORT_DESC); MODULE_VERSION(NTB_TRANSPORT_VER); MODULE_LICENSE("Dual BSD/GPL"); @@ -102,6 +107,13 @@ module_param(use_msi, bool, 0644); MODULE_PARM_DESC(use_msi, "Use MSI interrupts instead of doorbells"); #endif =20 +#ifdef CONFIG_NTB_TRANSPORT_EDMA +#include "ntb_edma.h" +static bool use_remote_edma; +module_param(use_remote_edma, bool, 0644); +MODULE_PARM_DESC(use_remote_edma, "Use remote eDMA mode (when enabled, use= _msi is ignored)"); +#endif + static struct dentry *nt_debugfs_dir; =20 /* Only two-ports NTB devices are supported */ @@ -125,6 +137,14 @@ struct ntb_queue_entry { struct ntb_payload_header __iomem *tx_hdr; struct ntb_payload_header *rx_hdr; }; + +#ifdef CONFIG_NTB_TRANSPORT_EDMA + dma_addr_t addr; + + /* Used by RC side only */ + struct scatterlist sgl; + struct work_struct dma_work; +#endif }; =20 struct ntb_rx_info { @@ -202,6 +222,33 @@ struct ntb_transport_qp { int msi_irq; struct ntb_msi_desc msi_desc; struct ntb_msi_desc peer_msi_desc; + +#ifdef CONFIG_NTB_TRANSPORT_EDMA + /* + * For ensuring peer notification in non-atomic context. + * ntb_peer_db_set might sleep or schedule. + */ + struct work_struct db_work; + + /* + * wr: remote eDMA write transfer (EP -> RC direction) + * rd: remote eDMA read transfer (RC -> EP direction) + */ + u32 wr_cons; + u32 rd_cons; + u32 wr_prod; + u32 rd_prod; + u32 wr_issue; + u32 rd_issue; + + spinlock_t ep_tx_lock; + spinlock_t ep_rx_lock; + spinlock_t rc_lock; + + /* Completion work for read/write transfers. */ + struct work_struct read_work; + struct work_struct write_work; +#endif }; =20 struct ntb_transport_mw { @@ -249,6 +296,13 @@ struct ntb_transport_ctx { =20 /* Make sure workq of link event be executed serially */ struct mutex link_event_lock; + +#ifdef CONFIG_NTB_TRANSPORT_EDMA + remote_edma_mode_t remote_edma_mode; + struct device *dma_dev; + struct workqueue_struct *wq; + struct ntb_edma_chans edma; +#endif }; =20 enum { @@ -262,6 +316,19 @@ struct ntb_payload_header { unsigned int flags; }; =20 +#ifdef CONFIG_NTB_TRANSPORT_EDMA +static void ntb_transport_edma_uninit(struct ntb_transport_ctx *nt); +static int ntb_transport_edma_init(struct ntb_transport_ctx *nt, + unsigned int *mw_count); +static void ntb_transport_edma_init_queue(struct ntb_transport_ctx *nt, + unsigned int qp_num); +static void ntb_transport_edma_create_queue(struct ntb_transport_ctx *nt, + struct ntb_transport_qp *qp); +static int ntb_transport_edma_rc_init(struct ntb_transport_ctx *nt); +static int ntb_transport_edma_ep_init(struct ntb_transport_ctx *nt); +static void ntb_transport_edma_rc_dma_work(struct work_struct *work); +#endif /* CONFIG_NTB_TRANSPORT_EDMA */ + /* * Return the device that should be used for DMA mapping. * @@ -298,7 +365,7 @@ enum { container_of((__drv), struct ntb_transport_client, driver) =20 #define QP_TO_MW(nt, qp) ((qp) % nt->mw_count) -#define NTB_QP_DEF_NUM_ENTRIES 100 +#define NTB_QP_DEF_NUM_ENTRIES 128 #define NTB_LINK_DOWN_TIMEOUT 10 =20 static void ntb_transport_rxc_db(unsigned long data); @@ -1015,6 +1082,10 @@ static void ntb_transport_link_cleanup(struct ntb_tr= ansport_ctx *nt) count =3D ntb_spad_count(nt->ndev); for (i =3D 0; i < count; i++) ntb_spad_write(nt->ndev, i, 0); + +#ifdef CONFIG_NTB_TRANSPORT_EDMA + ntb_edma_teardown_chans(&nt->edma); +#endif } =20 static void ntb_transport_link_cleanup_work(struct work_struct *work) @@ -1051,6 +1122,14 @@ static void ntb_transport_link_work(struct work_stru= ct *work) =20 /* send the local info, in the opposite order of the way we read it */ =20 +#ifdef CONFIG_NTB_TRANSPORT_EDMA + rc =3D ntb_transport_edma_ep_init(nt); + if (rc) { + dev_err(&pdev->dev, "Failed to init EP: %d\n", rc); + return; + } +#endif + if (nt->use_msi) { rc =3D ntb_msi_setup_mws(ndev); if (rc) { @@ -1132,6 +1211,14 @@ static void ntb_transport_link_work(struct work_stru= ct *work) =20 nt->link_is_up =3D true; =20 +#ifdef CONFIG_NTB_TRANSPORT_EDMA + rc =3D ntb_transport_edma_rc_init(nt); + if (rc) { + dev_err(&pdev->dev, "Failed to init RC: %d\n", rc); + goto out1; + } +#endif + for (i =3D 0; i < nt->qp_count; i++) { struct ntb_transport_qp *qp =3D &nt->qp_vec[i]; =20 @@ -1277,6 +1364,8 @@ static const struct ntb_transport_backend_ops default= _backend_ops =3D { .debugfs_stats_show =3D ntb_transport_default_debugfs_stats_show, }; =20 +static const struct ntb_transport_backend_ops edma_backend_ops; + static int ntb_transport_probe(struct ntb_client *self, struct ntb_dev *nd= ev) { struct ntb_transport_ctx *nt; @@ -1311,7 +1400,23 @@ static int ntb_transport_probe(struct ntb_client *se= lf, struct ntb_dev *ndev) =20 nt->ndev =3D ndev; =20 - nt->backend_ops =3D default_backend_ops; +#ifdef CONFIG_NTB_TRANSPORT_EDMA + if (use_remote_edma) { + rc =3D ntb_transport_edma_init(nt, &mw_count); + if (rc) { + nt->mw_count =3D 0; + goto err; + } + nt->backend_ops =3D edma_backend_ops; + + /* + * On remote eDMA mode, we reserve a read channel for Host->EP + * interruption. + */ + use_msi =3D false; + } else +#endif + nt->backend_ops =3D default_backend_ops; =20 /* * If we are using MSI, and have at least one extra memory window, @@ -1402,6 +1507,10 @@ static int ntb_transport_probe(struct ntb_client *se= lf, struct ntb_dev *ndev) rc =3D ntb_transport_init_queue(nt, i); if (rc) goto err2; + +#ifdef CONFIG_NTB_TRANSPORT_EDMA + ntb_transport_edma_init_queue(nt, i); +#endif } =20 INIT_DELAYED_WORK(&nt->link_work, ntb_transport_link_work); @@ -1433,6 +1542,9 @@ static int ntb_transport_probe(struct ntb_client *sel= f, struct ntb_dev *ndev) } kfree(nt->mw_vec); err: +#ifdef CONFIG_NTB_TRANSPORT_EDMA + ntb_transport_edma_uninit(nt); +#endif kfree(nt); return rc; } @@ -2055,11 +2167,16 @@ ntb_transport_create_queue(void *data, struct devic= e *client_dev, =20 nt->qp_bitmap_free &=3D ~qp_bit; =20 + qp->qp_bit =3D qp_bit; qp->cb_data =3D data; qp->rx_handler =3D handlers->rx_handler; qp->tx_handler =3D handlers->tx_handler; qp->event_handler =3D handlers->event_handler; =20 +#ifdef CONFIG_NTB_TRANSPORT_EDMA + ntb_transport_edma_create_queue(nt, qp); +#endif + dma_cap_zero(dma_mask); dma_cap_set(DMA_MEMCPY, dma_mask); =20 @@ -2105,6 +2222,9 @@ ntb_transport_create_queue(void *data, struct device = *client_dev, goto err1; =20 entry->qp =3D qp; +#ifdef CONFIG_NTB_TRANSPORT_EDMA + INIT_WORK(&entry->dma_work, ntb_transport_edma_rc_dma_work); +#endif ntb_list_add(&qp->ntb_rx_q_lock, &entry->entry, &qp->rx_free_q); } @@ -2156,8 +2276,8 @@ EXPORT_SYMBOL_GPL(ntb_transport_create_queue); */ void ntb_transport_free_queue(struct ntb_transport_qp *qp) { - struct pci_dev *pdev; struct ntb_queue_entry *entry; + struct pci_dev *pdev; u64 qp_bit; =20 if (!qp) @@ -2208,6 +2328,10 @@ void ntb_transport_free_queue(struct ntb_transport_q= p *qp) tasklet_kill(&qp->rxc_db_work); =20 cancel_delayed_work_sync(&qp->link_work); +#ifdef CONFIG_NTB_TRANSPORT_EDMA + cancel_work_sync(&qp->read_work); + cancel_work_sync(&qp->write_work); +#endif =20 qp->cb_data =3D NULL; qp->rx_handler =3D NULL; @@ -2346,6 +2470,1157 @@ int ntb_transport_tx_enqueue(struct ntb_transport_= qp *qp, void *cb, void *data, } EXPORT_SYMBOL_GPL(ntb_transport_tx_enqueue); =20 +#ifdef CONFIG_NTB_TRANSPORT_EDMA +/* + * Remote eDMA mode implementation + */ +struct ntb_edma_desc { + u32 len; + u32 flags; + u64 addr; /* DMA address */ + u64 data; +}; + +struct ntb_edma_ring { + struct ntb_edma_desc desc[NTB_EDMA_RING_ENTRIES]; + u32 head; + u32 tail; +}; + +#define NTB_EDMA_DESC_OFF(i) ((size_t)(i) * sizeof(struct ntb_edma_desc)) + +#define __NTB_EDMA_CHECK_INDEX(_i) \ +({ \ + unsigned long __i =3D (unsigned long)(_i); \ + WARN_ONCE(__i >=3D (unsigned long)NTB_EDMA_RING_ENTRIES, \ + "ntb_edma: index i=3D%lu >=3D ring_entries=3D%lu\n", \ + __i, (unsigned long)NTB_EDMA_RING_ENTRIES); \ + __i; \ +}) + +#define NTB_EDMA_DESC_I(qp, i, n) \ +({ \ + typeof(qp) __qp =3D (qp); \ + unsigned long __i =3D __NTB_EDMA_CHECK_INDEX(i); \ + (struct ntb_edma_desc *) \ + ((char *)(__qp)->rx_buff + \ + (sizeof(struct ntb_edma_ring) * n) + \ + NTB_EDMA_DESC_OFF(__i)); \ +}) + +#define NTB_EDMA_DESC_O(qp, i, n) \ +({ \ + typeof(qp) __qp =3D (qp); \ + unsigned long __i =3D __NTB_EDMA_CHECK_INDEX(i); \ + (struct ntb_edma_desc __iomem *) \ + ((char __iomem *)(__qp)->tx_mw + \ + (sizeof(struct ntb_edma_ring) * n) + \ + NTB_EDMA_DESC_OFF(__i)); \ +}) + +#define NTB_EDMA_HEAD_I(qp, n) ((u32 *)((char *)qp->rx_buff + \ + (sizeof(struct ntb_edma_ring) * n) + \ + offsetof(struct ntb_edma_ring, head))) +#define NTB_EDMA_HEAD_O(qp, n) ((u32 *)((char __iomem *)qp->tx_mw + \ + (sizeof(struct ntb_edma_ring) * n) + \ + offsetof(struct ntb_edma_ring, head))) +#define NTB_EDMA_TAIL_I(qp, n) ((u32 *)((char *)qp->rx_buff + \ + (sizeof(struct ntb_edma_ring) * n) + \ + offsetof(struct ntb_edma_ring, tail))) +#define NTB_EDMA_TAIL_O(qp, n) ((u32 *)((char __iomem *)qp->tx_mw + \ + (sizeof(struct ntb_edma_ring) * n) + \ + offsetof(struct ntb_edma_ring, tail))) + +/* + * Macro naming rule: + * NTB_DESC_RD_EP_I (as an example) + * ^^ ^^ ^ + * : : `-- I(n) or O(ut). In =3D Read, Out =3D Write. + * : `----- Who uses this macro. + * `-------- DESC / HEAD / TAIL + * + * Read transfers (RC->EP): + * + * EP view (outbound, written via NTB): + * - descs: NTB_DESC_RD_EP_O(qp, i) / NTB_DESC_RD_EP_I(qp, i) + * [ len ][ flags ][ addr ][ data ] + * [ len ][ flags ][ addr ][ data ] + * : + * [ len ][ flags ][ addr ][ data ] + * - head: NTB_HEAD_RD_EP_O(qp) + * - tail: NTB_TAIL_RD_EP_I(qp) + * + * RC view (inbound, local mapping): + * - descs: NTB_DESC_RD_RC_I(qp, i) / NTB_DESC_RD_RC_O(qp, i) + * [ len ][ flags ][ addr ][ data ] + * [ len ][ flags ][ addr ][ data ] + * : + * [ len ][ flags ][ addr ][ data ] + * - head: NTB_HEAD_RD_RC_I(qp) + * - tail: NTB_TAIL_RD_RC_O(qp) + * + * Write transfers (EP -> RC) are analogous but use + * NTB_DESC_WR_{EP_O,RC_I}(), NTB_HEAD_WR_{EP_O,RC_I}(), + * and NTB_TAIL_WR_{EP_I,RC_O}(). + */ +#define NTB_DESC_RD_EP_I(qp, i) NTB_EDMA_DESC_I(qp, i, 0) +#define NTB_DESC_RD_EP_O(qp, i) NTB_EDMA_DESC_O(qp, i, 0) +#define NTB_DESC_WR_EP_I(qp, i) NTB_EDMA_DESC_I(qp, i, 1) +#define NTB_DESC_WR_EP_O(qp, i) NTB_EDMA_DESC_O(qp, i, 1) +#define NTB_DESC_RD_RC_I(qp, i) NTB_EDMA_DESC_I(qp, i, 0) +#define NTB_DESC_RD_RC_O(qp, i) NTB_EDMA_DESC_O(qp, i, 0) +#define NTB_DESC_WR_RC_I(qp, i) NTB_EDMA_DESC_I(qp, i, 1) +#define NTB_DESC_WR_RC_O(qp, i) NTB_EDMA_DESC_O(qp, i, 1) + +#define NTB_HEAD_RD_EP_O(qp) NTB_EDMA_HEAD_O(qp, 0) +#define NTB_HEAD_WR_EP_O(qp) NTB_EDMA_HEAD_O(qp, 1) +#define NTB_HEAD_RD_RC_I(qp) NTB_EDMA_HEAD_I(qp, 0) +#define NTB_HEAD_WR_RC_I(qp) NTB_EDMA_HEAD_I(qp, 1) + +#define NTB_TAIL_RD_EP_I(qp) NTB_EDMA_TAIL_I(qp, 0) +#define NTB_TAIL_WR_EP_I(qp) NTB_EDMA_TAIL_I(qp, 1) +#define NTB_TAIL_RD_RC_O(qp) NTB_EDMA_TAIL_O(qp, 0) +#define NTB_TAIL_WR_RC_O(qp) NTB_EDMA_TAIL_O(qp, 1) + +static inline bool ntb_qp_edma_is_rc(struct ntb_transport_qp *qp) +{ + return qp->transport->remote_edma_mode =3D=3D REMOTE_EDMA_RC; +} + +static inline bool ntb_qp_edma_is_ep(struct ntb_transport_qp *qp) +{ + return qp->transport->remote_edma_mode =3D=3D REMOTE_EDMA_EP; +} + +static inline bool ntb_qp_edma_enabled(struct ntb_transport_qp *qp) +{ + return ntb_qp_edma_is_rc(qp) || ntb_qp_edma_is_ep(qp); +} + +static unsigned int ntb_transport_edma_tx_free_entry(struct ntb_transport_= qp *qp) +{ + unsigned int head, tail; + + if (ntb_qp_edma_is_ep(qp)) { + scoped_guard(spinlock_irqsave, &qp->ep_tx_lock) { + /* In this scope, only 'head' might proceed */ + tail =3D READ_ONCE(qp->wr_cons); + head =3D READ_ONCE(qp->wr_prod); + } + return ntb_edma_ring_free_entry(head, tail); + } + + scoped_guard(spinlock_irqsave, &qp->rc_lock) { + /* In this scope, only 'head' might proceed */ + tail =3D READ_ONCE(qp->rd_issue); + head =3D READ_ONCE(*NTB_HEAD_RD_RC_I(qp)); + } + /* + * On RC side, 'used' amount indicates how much EP side + * has refilled, which are available for us to use for TX. + */ + return ntb_edma_ring_used_entry(head, tail); +} + +static void ntb_transport_edma_debugfs_stats_show(struct seq_file *s, + struct ntb_transport_qp *qp) +{ + seq_printf(s, "rx_bytes - \t%llu\n", qp->rx_bytes); + seq_printf(s, "rx_pkts - \t%llu\n", qp->rx_pkts); + seq_printf(s, "rx_err_no_buf - %llu\n", qp->rx_err_no_buf); + seq_printf(s, "rx_buff - \t0x%p\n", qp->rx_buff); + seq_printf(s, "rx_max_entry - \t%u\n", qp->rx_max_entry); + seq_printf(s, "rx_alloc_entry - \t%u\n\n", qp->rx_alloc_entry); + + seq_printf(s, "tx_bytes - \t%llu\n", qp->tx_bytes); + seq_printf(s, "tx_pkts - \t%llu\n", qp->tx_pkts); + seq_printf(s, "tx_ring_full - \t%llu\n", qp->tx_ring_full); + seq_printf(s, "tx_err_no_buf - %llu\n", qp->tx_err_no_buf); + seq_printf(s, "tx_mw - \t0x%p\n", qp->tx_mw); + seq_printf(s, "tx_max_entry - \t%u\n", qp->tx_max_entry); + seq_printf(s, "free tx - \t%u\n", ntb_transport_tx_free_entry(qp)); + seq_putc(s, '\n'); + + seq_puts(s, "Using Remote eDMA - Yes\n"); + seq_printf(s, "QP Link - \t%s\n", qp->link_is_up ? "Up" : "Down"); +} + +static void ntb_transport_edma_uninit(struct ntb_transport_ctx *nt) +{ + struct ntb_dev *ndev =3D nt->ndev; + + if (nt->remote_edma_mode =3D=3D REMOTE_EDMA_EP && ndev && ndev->pdev) + ntb_edma_teardown_isr(&ndev->pdev->dev); + + if (nt->wq) + destroy_workqueue(nt->wq); + nt->wq =3D NULL; +} + +static int ntb_transport_edma_init(struct ntb_transport_ctx *nt, + unsigned int *mw_count) +{ + struct ntb_dev *ndev =3D nt->ndev; + + /* + * We need at least one MW for the transport plus one MW reserved + * for the remote eDMA window (see ntb_edma_setup_mws/peer). + */ + if (*mw_count <=3D 1) { + dev_err(&ndev->dev, + "remote eDMA requires at least two MWS (have %u)\n", + *mw_count); + return -ENODEV; + } + + nt->wq =3D alloc_workqueue("ntb-edma-wq", WQ_UNBOUND | WQ_SYSFS, 0); + if (!nt->wq) { + ntb_transport_edma_uninit(nt); + return -ENOMEM; + } + + /* Reserve the last peer MW exclusively for the eDMA window. */ + *mw_count -=3D 1; + + return 0; +} + +static void ntb_transport_edma_db_work(struct work_struct *work) +{ + struct ntb_transport_qp *qp =3D + container_of(work, struct ntb_transport_qp, db_work); + + ntb_peer_db_set(qp->ndev, qp->qp_bit); +} + +static void ntb_transport_edma_notify_peer(struct ntb_transport_qp *qp) +{ + if (ntb_qp_edma_is_rc(qp)) + if (!ntb_edma_notify_peer(&qp->transport->edma, qp->qp_num)) + return; + + /* + * Called from contexts that may be atomic. Since ntb_peer_db_set() + * may sleep, delegate the actual doorbell write to a workqueue. + */ + queue_work(system_highpri_wq, &qp->db_work); +} + +static void ntb_transport_edma_isr(void *data, int qp_num) +{ + struct ntb_transport_ctx *nt =3D data; + struct ntb_transport_qp *qp; + + if (qp_num < 0 || qp_num >=3D nt->qp_count) + return; + + qp =3D &nt->qp_vec[qp_num]; + if (WARN_ON(!qp)) + return; + + queue_work(nt->wq, &qp->read_work); + queue_work(nt->wq, &qp->write_work); +} + +static int ntb_transport_edma_rc_init(struct ntb_transport_ctx *nt) +{ + struct ntb_dev *ndev =3D nt->ndev; + struct pci_dev *pdev =3D ndev->pdev; + int rc; + + if (!use_remote_edma || nt->remote_edma_mode !=3D REMOTE_EDMA_UNKNOWN) + return 0; + + rc =3D ntb_edma_setup_peer(ndev); + if (rc) { + dev_err(&pdev->dev, "Failed to enable remote eDMA: %d\n", rc); + return rc; + } + + rc =3D ntb_edma_setup_chans(get_dma_dev(ndev), &nt->edma); + if (rc) { + dev_err(&pdev->dev, "Failed to setup eDMA channels: %d\n", rc); + return rc; + } + + nt->remote_edma_mode =3D REMOTE_EDMA_RC; + return 0; +} + +static int ntb_transport_edma_ep_init(struct ntb_transport_ctx *nt) +{ + struct ntb_dev *ndev =3D nt->ndev; + struct pci_dev *pdev =3D ndev->pdev; + struct pci_epc *epc; + int rc; + + if (!use_remote_edma || nt->remote_edma_mode =3D=3D REMOTE_EDMA_EP) + return 0; + + /* Only EP side can return pci_epc */ + epc =3D ntb_get_pci_epc(ndev); + if (!epc) + return 0; + + rc =3D ntb_edma_setup_mws(ndev); + if (rc) { + dev_err(&pdev->dev, + "Failed to set up memory window for eDMA: %d\n", rc); + return rc; + } + + rc =3D ntb_edma_setup_isr(&pdev->dev, &epc->dev, ntb_transport_edma_isr, = nt); + if (rc) { + dev_err(&pdev->dev, "Failed to setup eDMA ISR (%d)\n", rc); + return rc; + } + + nt->remote_edma_mode =3D REMOTE_EDMA_EP; + return 0; +} + +static int ntb_transport_edma_setup_qp_mw(struct ntb_transport_ctx *nt, + unsigned int qp_num) +{ + struct ntb_transport_qp *qp =3D &nt->qp_vec[qp_num]; + struct ntb_dev *ndev =3D nt->ndev; + struct ntb_queue_entry *entry; + struct ntb_transport_mw *mw; + unsigned int mw_num, mw_count, qp_count; + unsigned int qp_offset, rx_info_offset; + unsigned int mw_size, mw_size_per_qp; + unsigned int num_qps_mw; + size_t edma_total; + unsigned int i; + int node; + + mw_count =3D nt->mw_count; + qp_count =3D nt->qp_count; + + mw_num =3D QP_TO_MW(nt, qp_num); + mw =3D &nt->mw_vec[mw_num]; + + if (!mw->virt_addr) + return -ENOMEM; + + if (mw_num < qp_count % mw_count) + num_qps_mw =3D qp_count / mw_count + 1; + else + num_qps_mw =3D qp_count / mw_count; + + mw_size =3D min(nt->mw_vec[mw_num].phys_size, mw->xlat_size); + if (max_mw_size && mw_size > max_mw_size) + mw_size =3D max_mw_size; + + mw_size_per_qp =3D round_down((unsigned int)mw_size / num_qps_mw, SZ_64); + qp_offset =3D mw_size_per_qp * (qp_num / mw_count); + rx_info_offset =3D mw_size_per_qp - sizeof(struct ntb_rx_info); + + qp->tx_mw_size =3D mw_size_per_qp; + qp->tx_mw =3D nt->mw_vec[mw_num].vbase + qp_offset; + if (!qp->tx_mw) + return -EINVAL; + qp->tx_mw_phys =3D nt->mw_vec[mw_num].phys_addr + qp_offset; + if (!qp->tx_mw_phys) + return -EINVAL; + qp->rx_info =3D qp->tx_mw + rx_info_offset; + qp->rx_buff =3D mw->virt_addr + qp_offset; + qp->remote_rx_info =3D qp->rx_buff + rx_info_offset; + + /* Due to housekeeping, there must be at least 2 buffs */ + qp->tx_max_frame =3D min(transport_mtu, mw_size_per_qp / 2); + qp->rx_max_frame =3D min(transport_mtu, mw_size_per_qp / 2); + + /* In eDMA mode, decouple from MW sizing and force ring-sized entries */ + edma_total =3D 2 * sizeof(struct ntb_edma_ring); + if (rx_info_offset < edma_total) { + dev_err(&ndev->dev, "Ring space requires %luB (>=3D%uB)\n", + edma_total, rx_info_offset); + return -EINVAL; + } + qp->tx_max_entry =3D NTB_EDMA_RING_ENTRIES; + qp->rx_max_entry =3D NTB_EDMA_RING_ENTRIES; + + /* + * Checking to see if we have more entries than the default. + * We should add additional entries if that is the case so we + * can be in sync with the transport frames. + */ + node =3D dev_to_node(&ndev->dev); + for (i =3D qp->rx_alloc_entry; i < qp->rx_max_entry; i++) { + entry =3D kzalloc_node(sizeof(*entry), GFP_KERNEL, node); + if (!entry) + return -ENOMEM; + + entry->qp =3D qp; + INIT_WORK(&entry->dma_work, ntb_transport_edma_rc_dma_work); + ntb_list_add(&qp->ntb_rx_q_lock, &entry->entry, + &qp->rx_free_q); + qp->rx_alloc_entry++; + } + + memset(qp->rx_buff, 0, edma_total); + + qp->rx_pkts =3D 0; + qp->tx_pkts =3D 0; + + return 0; +} + +static int ntb_transport_edma_ep_read_complete(struct ntb_transport_qp *qp) +{ + struct device *dma_dev =3D get_dma_dev(qp->ndev); + struct ntb_queue_entry *entry; + struct ntb_edma_desc *in; + unsigned int len; + u32 idx; + + if (ntb_edma_ring_used_entry(READ_ONCE(*NTB_TAIL_RD_EP_I(qp)), + qp->rd_cons) =3D=3D 0) + return 0; + + idx =3D ntb_edma_ring_idx(qp->rd_cons); + in =3D NTB_DESC_RD_EP_I(qp, idx); + if (!(in->flags & DESC_DONE_FLAG)) + return 0; + + in->flags =3D 0; + len =3D in->len; /* might be smaller than entry->len */ + + entry =3D (struct ntb_queue_entry *)(in->data); + if (WARN_ON(!entry)) + return 0; + + if (in->flags & LINK_DOWN_FLAG) { + ntb_qp_link_down(qp); + qp->rd_cons++; + ntb_list_add(&qp->ntb_rx_q_lock, &entry->entry, &qp->rx_free_q); + return 1; + } + + dma_unmap_single(dma_dev, entry->addr, entry->len, DMA_FROM_DEVICE); + + qp->rx_bytes +=3D len; + qp->rx_pkts++; + qp->rd_cons++; + + if (qp->rx_handler && qp->client_ready) + qp->rx_handler(qp, qp->cb_data, entry->cb_data, len); + + ntb_list_add(&qp->ntb_rx_q_lock, &entry->entry, &qp->rx_free_q); + return 1; +} + +static int ntb_transport_edma_ep_write_complete(struct ntb_transport_qp *q= p) +{ + struct ntb_queue_entry *entry; + struct ntb_edma_desc *in; + u32 idx; + + if (ntb_edma_ring_used_entry(READ_ONCE(*NTB_TAIL_WR_EP_I(qp)), + qp->wr_cons) =3D=3D 0) + return 0; + + idx =3D ntb_edma_ring_idx(qp->wr_cons); + in =3D NTB_DESC_WR_EP_I(qp, idx); + + entry =3D (struct ntb_queue_entry *)(in->data); + if (WARN_ON(!entry)) + return 0; + + qp->wr_cons++; + + if (qp->tx_handler) + qp->tx_handler(qp, qp->cb_data, entry->cb_data, entry->len); + + ntb_list_add(&qp->ntb_tx_free_q_lock, &entry->entry, &qp->tx_free_q); + return 1; +} + +static void ntb_transport_edma_ep_read_work(struct work_struct *work) +{ + struct ntb_transport_qp *qp =3D container_of( + work, struct ntb_transport_qp, read_work); + unsigned int i; + + for (i =3D 0; i < NTB_EDMA_MAX_POLL; i++) { + if (!ntb_transport_edma_ep_read_complete(qp)) + break; + } + + if (ntb_transport_edma_ep_read_complete(qp)) + queue_work(qp->transport->wq, &qp->read_work); +} + +static void ntb_transport_edma_ep_write_work(struct work_struct *work) +{ + struct ntb_transport_qp *qp =3D container_of( + work, struct ntb_transport_qp, write_work); + unsigned int i; + + for (i =3D 0; i < NTB_EDMA_MAX_POLL; i++) { + if (!ntb_transport_edma_ep_write_complete(qp)) + break; + } + + if (ntb_transport_edma_ep_write_complete(qp)) + queue_work(qp->transport->wq, &qp->write_work); +} + +static void ntb_transport_edma_rc_write_complete_work(struct work_struct *= work) +{ + struct ntb_transport_qp *qp =3D container_of( + work, struct ntb_transport_qp, write_work); + struct ntb_queue_entry *entry; + struct ntb_edma_desc *in; + unsigned int len; + void *cb_data; + u32 idx; + + while (ntb_edma_ring_used_entry(READ_ONCE(qp->wr_issue), + qp->wr_cons) !=3D 0) { + /* Paired with smp_wmb() in ntb_transport_edma_rc_poll() */ + smp_rmb(); + + idx =3D ntb_edma_ring_idx(qp->wr_cons); + in =3D NTB_DESC_WR_RC_I(qp, idx); + entry =3D (struct ntb_queue_entry *)READ_ONCE(in->data); + if (!entry || !(entry->flags & DESC_DONE_FLAG)) + break; + + in->data =3D 0; + + cb_data =3D entry->cb_data; + len =3D entry->len; + + iowrite32(++qp->wr_cons, NTB_TAIL_WR_RC_O(qp)); + + if (unlikely(entry->flags & LINK_DOWN_FLAG)) { + ntb_qp_link_down(qp); + continue; + } + + ntb_transport_edma_notify_peer(qp); + + ntb_list_add(&qp->ntb_rx_q_lock, &entry->entry, &qp->rx_free_q); + + if (qp->rx_handler && qp->client_ready) + qp->rx_handler(qp, qp->cb_data, cb_data, len); + + /* stat updates */ + qp->rx_bytes +=3D len; + qp->rx_pkts++; + } +} + +static void ntb_transport_edma_rc_write_cb(void *data, + const struct dmaengine_result *res) +{ + struct ntb_queue_entry *entry =3D data; + struct ntb_transport_qp *qp =3D entry->qp; + struct ntb_transport_ctx *nt =3D qp->transport; + enum dmaengine_tx_result dma_err =3D res->result; + struct device *dma_dev =3D get_dma_dev(qp->ndev); + + switch (dma_err) { + case DMA_TRANS_READ_FAILED: + case DMA_TRANS_WRITE_FAILED: + case DMA_TRANS_ABORTED: + entry->errors++; + entry->len =3D -EIO; + break; + case DMA_TRANS_NOERROR: + default: + break; + } + dma_unmap_sg(dma_dev, &entry->sgl, 1, DMA_FROM_DEVICE); + sg_dma_address(&entry->sgl) =3D 0; + + entry->flags |=3D DESC_DONE_FLAG; + + queue_work(nt->wq, &qp->write_work); +} + +static void ntb_transport_edma_rc_read_complete_work(struct work_struct *w= ork) +{ + struct ntb_transport_qp *qp =3D container_of( + work, struct ntb_transport_qp, read_work); + struct ntb_edma_desc *in, __iomem *out; + struct ntb_queue_entry *entry; + unsigned int len; + void *cb_data; + u32 idx; + + while (ntb_edma_ring_used_entry(READ_ONCE(qp->rd_issue), + qp->rd_cons) !=3D 0) { + /* Paired with smp_wmb() in ntb_transport_edma_rc_tx_enqueue() */ + smp_rmb(); + + idx =3D ntb_edma_ring_idx(qp->rd_cons); + in =3D NTB_DESC_RD_RC_I(qp, idx); + entry =3D (struct ntb_queue_entry *)in->data; + if (!entry || !(entry->flags & DESC_DONE_FLAG)) + break; + + in->data =3D 0; + + cb_data =3D entry->cb_data; + len =3D entry->len; + + out =3D NTB_DESC_RD_RC_O(qp, idx); + + WRITE_ONCE(qp->rd_cons, qp->rd_cons + 1); + + /* + * No need to add barrier in-between to enforce ordering here. + * The other side proceeds only after both flags and tail are + * updated. + */ + iowrite32(entry->flags, &out->flags); + iowrite32(qp->rd_cons, NTB_TAIL_RD_RC_O(qp)); + + ntb_transport_edma_notify_peer(qp); + + ntb_list_add(&qp->ntb_tx_free_q_lock, &entry->entry, + &qp->tx_free_q); + + if (qp->tx_handler) + qp->tx_handler(qp, qp->cb_data, cb_data, len); + + /* stat updates */ + qp->tx_bytes +=3D len; + qp->tx_pkts++; + } +} + +static void ntb_transport_edma_rc_read_cb(void *data, + const struct dmaengine_result *res) +{ + struct ntb_queue_entry *entry =3D data; + struct ntb_transport_qp *qp =3D entry->qp; + struct ntb_transport_ctx *nt =3D qp->transport; + struct device *dma_dev =3D get_dma_dev(qp->ndev); + enum dmaengine_tx_result dma_err =3D res->result; + + switch (dma_err) { + case DMA_TRANS_READ_FAILED: + case DMA_TRANS_WRITE_FAILED: + case DMA_TRANS_ABORTED: + entry->errors++; + entry->len =3D -EIO; + break; + case DMA_TRANS_NOERROR: + default: + break; + } + dma_unmap_sg(dma_dev, &entry->sgl, 1, DMA_TO_DEVICE); + sg_dma_address(&entry->sgl) =3D 0; + + entry->flags |=3D DESC_DONE_FLAG; + + queue_work(nt->wq, &qp->read_work); +} + +static int ntb_transport_edma_rc_write_start(struct device *d, + struct dma_chan *chan, size_t len, + dma_addr_t ep_src, void *rc_dst, + struct ntb_queue_entry *entry) +{ + struct scatterlist *sgl =3D &entry->sgl; + struct dma_async_tx_descriptor *txd; + struct dma_slave_config cfg; + dma_cookie_t cookie; + int nents, rc; + + if (!d) + return -ENODEV; + + if (!chan) + return -ENXIO; + + if (WARN_ON(!ep_src || !rc_dst)) + return -EINVAL; + + if (WARN_ON(sg_dma_address(sgl))) + return -EINVAL; + + sg_init_one(sgl, rc_dst, len); + nents =3D dma_map_sg(d, sgl, 1, DMA_FROM_DEVICE); + if (nents <=3D 0) + return -EIO; + + memset(&cfg, 0, sizeof(cfg)); + cfg.src_addr =3D ep_src; + cfg.src_addr_width =3D DMA_SLAVE_BUSWIDTH_4_BYTES; + cfg.dst_addr_width =3D DMA_SLAVE_BUSWIDTH_4_BYTES; + cfg.direction =3D DMA_DEV_TO_MEM; + rc =3D dmaengine_slave_config(chan, &cfg); + if (rc) + goto out_unmap; + + txd =3D dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM, + DMA_CTRL_ACK | DMA_PREP_INTERRUPT); + if (!txd) { + rc =3D -EIO; + goto out_unmap; + } + + txd->callback_result =3D ntb_transport_edma_rc_write_cb; + txd->callback_param =3D entry; + + cookie =3D dmaengine_submit(txd); + if (dma_submit_error(cookie)) { + rc =3D -EIO; + goto out_unmap; + } + dma_async_issue_pending(chan); + return 0; +out_unmap: + dma_unmap_sg(d, sgl, 1, DMA_FROM_DEVICE); + return rc; +} + +static int ntb_transport_edma_rc_read_start(struct device *d, + struct dma_chan *chan, size_t len, + void *rc_src, dma_addr_t ep_dst, + struct ntb_queue_entry *entry) +{ + struct scatterlist *sgl =3D &entry->sgl; + struct dma_async_tx_descriptor *txd; + struct dma_slave_config cfg; + dma_cookie_t cookie; + int nents, rc; + + if (!d) + return -ENODEV; + + if (!chan) + return -ENXIO; + + if (WARN_ON(!rc_src || !ep_dst)) + return -EINVAL; + + if (WARN_ON(sg_dma_address(sgl))) + return -EINVAL; + + sg_init_one(sgl, rc_src, len); + nents =3D dma_map_sg(d, sgl, 1, DMA_TO_DEVICE); + if (nents <=3D 0) + return -EIO; + + memset(&cfg, 0, sizeof(cfg)); + cfg.dst_addr =3D ep_dst; + cfg.src_addr_width =3D DMA_SLAVE_BUSWIDTH_4_BYTES; + cfg.dst_addr_width =3D DMA_SLAVE_BUSWIDTH_4_BYTES; + cfg.direction =3D DMA_MEM_TO_DEV; + rc =3D dmaengine_slave_config(chan, &cfg); + if (rc) + goto out_unmap; + + txd =3D dmaengine_prep_slave_sg(chan, sgl, 1, DMA_MEM_TO_DEV, + DMA_CTRL_ACK | DMA_PREP_INTERRUPT); + if (!txd) { + rc =3D -EIO; + goto out_unmap; + } + + txd->callback_result =3D ntb_transport_edma_rc_read_cb; + txd->callback_param =3D entry; + + cookie =3D dmaengine_submit(txd); + if (dma_submit_error(cookie)) { + rc =3D -EIO; + goto out_unmap; + } + dma_async_issue_pending(chan); + return 0; +out_unmap: + dma_unmap_sg(d, sgl, 1, DMA_TO_DEVICE); + return rc; +} + +static void ntb_transport_edma_rc_dma_work(struct work_struct *work) +{ + struct ntb_queue_entry *entry =3D container_of( + work, struct ntb_queue_entry, dma_work); + struct ntb_transport_qp *qp =3D entry->qp; + struct ntb_transport_ctx *nt =3D qp->transport; + struct device *dma_dev =3D get_dma_dev(qp->ndev); + struct dma_chan *chan; + int rc; + + chan =3D ntb_edma_pick_chan(&nt->edma, REMOTE_EDMA_WRITE); + rc =3D ntb_transport_edma_rc_write_start(dma_dev, chan, entry->len, + entry->addr, entry->buf, entry); + if (rc) { + entry->errors++; + entry->len =3D -EIO; + entry->flags |=3D DESC_DONE_FLAG; + queue_work(nt->wq, &qp->write_work); + return; + } +} + +static void ntb_transport_edma_rc_poll(struct ntb_transport_qp *qp) +{ + struct ntb_transport_ctx *nt =3D qp->transport; + unsigned int budget =3D NTB_EDMA_MAX_POLL; + struct ntb_queue_entry *entry; + struct ntb_edma_desc *in; + dma_addr_t ep_src; + u32 len, idx; + + while (budget--) { + if (ntb_edma_ring_used_entry(READ_ONCE(*NTB_HEAD_WR_RC_I(qp)), + qp->wr_issue) =3D=3D 0) + break; + + idx =3D ntb_edma_ring_idx(qp->wr_issue); + in =3D NTB_DESC_WR_RC_I(qp, idx); + + len =3D READ_ONCE(in->len); + ep_src =3D (dma_addr_t)READ_ONCE(in->addr); + + /* Prepare 'entry' for write completion */ + entry =3D ntb_list_rm(&qp->ntb_rx_q_lock, &qp->rx_pend_q); + if (!entry) { + qp->rx_err_no_buf++; + break; + } + if (WARN_ON(entry->flags & DESC_DONE_FLAG)) + entry->flags &=3D ~DESC_DONE_FLAG; + entry->len =3D len; /* NB. entry->len can be <=3D0 */ + entry->addr =3D ep_src; + + /* + * ntb_transport_edma_rc_write_complete_work() checks entry->flags + * so it needs to be set before wr_issue++. + */ + in->data =3D (uintptr_t)entry; + + /* Ensure in->data visible before wr_issue++ */ + smp_wmb(); + + WRITE_ONCE(qp->wr_issue, qp->wr_issue + 1); + + if (!len) { + entry->flags |=3D DESC_DONE_FLAG; + queue_work(nt->wq, &qp->write_work); + continue; + } + + if (in->flags & LINK_DOWN_FLAG) { + dev_dbg(&qp->ndev->pdev->dev, "link down flag set\n"); + entry->flags |=3D DESC_DONE_FLAG | LINK_DOWN_FLAG; + queue_work(nt->wq, &qp->write_work); + continue; + } + + queue_work(nt->wq, &entry->dma_work); + } + + if (!budget) + tasklet_schedule(&qp->rxc_db_work); +} + +static int ntb_transport_edma_rc_tx_enqueue(struct ntb_transport_qp *qp, + struct ntb_queue_entry *entry) +{ + struct device *dma_dev =3D get_dma_dev(qp->ndev); + struct ntb_transport_ctx *nt =3D qp->transport; + struct ntb_edma_desc *in, __iomem *out; + unsigned int len =3D entry->len; + struct dma_chan *chan; + u32 issue, idx, head; + dma_addr_t ep_dst; + int rc; + + WARN_ON_ONCE(entry->flags & DESC_DONE_FLAG); + + scoped_guard(spinlock_irqsave, &qp->rc_lock) { + head =3D READ_ONCE(*NTB_HEAD_RD_RC_I(qp)); + issue =3D qp->rd_issue; + if (ntb_edma_ring_used_entry(head, issue) =3D=3D 0) { + qp->tx_ring_full++; + return -ENOSPC; + } + + /* + * ntb_transport_edma_rc_read_complete_work() checks entry->flags + * so it needs to be set before rd_issue++. + */ + idx =3D ntb_edma_ring_idx(issue); + in =3D NTB_DESC_RD_RC_I(qp, idx); + in->data =3D (uintptr_t)entry; + + /* Make in->data visible before rd_issue++ */ + smp_wmb(); + + WRITE_ONCE(qp->rd_issue, qp->rd_issue + 1); + } + + /* Publish the final transfer length to the EP side */ + out =3D NTB_DESC_RD_RC_O(qp, idx); + iowrite32(len, &out->len); + ioread32(&out->len); + + if (unlikely(!len)) { + entry->flags |=3D DESC_DONE_FLAG; + queue_work(nt->wq, &qp->read_work); + return 0; + } + + /* Paired with dma_wmb() in ntb_transport_edma_ep_rx_enqueue() */ + dma_rmb(); + + /* kick remote eDMA read transfer */ + ep_dst =3D (dma_addr_t)in->addr; + chan =3D ntb_edma_pick_chan(&nt->edma, REMOTE_EDMA_READ); + rc =3D ntb_transport_edma_rc_read_start(dma_dev, chan, len, + entry->buf, ep_dst, entry); + if (rc) { + entry->errors++; + entry->len =3D -EIO; + entry->flags |=3D DESC_DONE_FLAG; + queue_work(nt->wq, &qp->read_work); + } + return 0; +} + +static int ntb_transport_edma_ep_tx_enqueue(struct ntb_transport_qp *qp, + struct ntb_queue_entry *entry) +{ + struct device *dma_dev =3D get_dma_dev(qp->ndev); + struct ntb_edma_desc *in, __iomem *out; + unsigned int len =3D entry->len; + dma_addr_t ep_src =3D 0; + u32 idx; + int rc; + + if (likely(len)) { + ep_src =3D dma_map_single(dma_dev, entry->buf, len, + DMA_TO_DEVICE); + rc =3D dma_mapping_error(dma_dev, ep_src); + if (rc) + return rc; + } + + scoped_guard(spinlock_irqsave, &qp->ep_tx_lock) { + if (ntb_edma_ring_full(qp->wr_prod, qp->wr_cons)) { + rc =3D -ENOSPC; + qp->tx_ring_full++; + goto out_unmap; + } + + idx =3D ntb_edma_ring_idx(qp->wr_prod); + in =3D NTB_DESC_WR_EP_I(qp, idx); + out =3D NTB_DESC_WR_EP_O(qp, idx); + + WARN_ON(in->flags & DESC_DONE_FLAG); + WARN_ON(entry->flags & DESC_DONE_FLAG); + in->flags =3D 0; + in->data =3D (uintptr_t)entry; + entry->addr =3D ep_src; + + iowrite32(len, &out->len); + iowrite32(entry->flags, &out->flags); + iowrite64(ep_src, &out->addr); + WRITE_ONCE(qp->wr_prod, qp->wr_prod + 1); + + dma_wmb(); + iowrite32(qp->wr_prod, NTB_HEAD_WR_EP_O(qp)); + + qp->tx_bytes +=3D len; + qp->tx_pkts++; + } + + ntb_transport_edma_notify_peer(qp); + + return 0; +out_unmap: + if (likely(len)) + dma_unmap_single(dma_dev, ep_src, len, DMA_TO_DEVICE); + return rc; +} + +static int ntb_transport_edma_tx_enqueue(struct ntb_transport_qp *qp, + struct ntb_queue_entry *entry, + void *cb, void *data, unsigned int len, + unsigned int flags) +{ + struct device *dma_dev; + + if (entry->addr) { + /* Deferred unmap */ + dma_dev =3D get_dma_dev(qp->ndev); + dma_unmap_single(dma_dev, entry->addr, entry->len, DMA_TO_DEVICE); + } + + entry->cb_data =3D cb; + entry->buf =3D data; + entry->len =3D len; + entry->flags =3D flags; + entry->errors =3D 0; + entry->addr =3D 0; + + WARN_ON_ONCE(!ntb_qp_edma_enabled(qp)); + + if (ntb_qp_edma_is_ep(qp)) + return ntb_transport_edma_ep_tx_enqueue(qp, entry); + else + return ntb_transport_edma_rc_tx_enqueue(qp, entry); +} + +static int ntb_transport_edma_ep_rx_enqueue(struct ntb_transport_qp *qp, + struct ntb_queue_entry *entry) +{ + struct device *dma_dev =3D get_dma_dev(qp->ndev); + struct ntb_edma_desc *in, __iomem *out; + unsigned int len =3D entry->len; + void *data =3D entry->buf; + dma_addr_t ep_dst; + u32 idx; + int rc; + + ep_dst =3D dma_map_single(dma_dev, data, len, DMA_FROM_DEVICE); + rc =3D dma_mapping_error(dma_dev, ep_dst); + if (rc) + return rc; + + scoped_guard(spinlock_bh, &qp->ep_rx_lock) { + if (ntb_edma_ring_full(READ_ONCE(qp->rd_prod), + READ_ONCE(qp->rd_cons))) { + rc =3D -ENOSPC; + goto out_unmap; + } + + idx =3D ntb_edma_ring_idx(qp->rd_prod); + in =3D NTB_DESC_RD_EP_I(qp, idx); + out =3D NTB_DESC_RD_EP_O(qp, idx); + + iowrite32(len, &out->len); + iowrite64(ep_dst, &out->addr); + + WARN_ON(in->flags & DESC_DONE_FLAG); + in->data =3D (uintptr_t)entry; + entry->addr =3D ep_dst; + + /* Ensure len/addr are visible before the head update */ + dma_wmb(); + + WRITE_ONCE(qp->rd_prod, qp->rd_prod + 1); + iowrite32(qp->rd_prod, NTB_HEAD_RD_EP_O(qp)); + } + return 0; +out_unmap: + dma_unmap_single(dma_dev, ep_dst, len, DMA_FROM_DEVICE); + return rc; +} + +static int ntb_transport_edma_rx_enqueue(struct ntb_transport_qp *qp, + struct ntb_queue_entry *entry) +{ + int rc; + + /* The behaviour is the same as the default backend for RC side */ + if (ntb_qp_edma_is_ep(qp)) { + rc =3D ntb_transport_edma_ep_rx_enqueue(qp, entry); + if (rc) { + ntb_list_add(&qp->ntb_rx_q_lock, &entry->entry, + &qp->rx_free_q); + return rc; + } + } + + ntb_list_add(&qp->ntb_rx_q_lock, &entry->entry, &qp->rx_pend_q); + + if (qp->active) + tasklet_schedule(&qp->rxc_db_work); + + return 0; +} + +static void ntb_transport_edma_rx_poll(struct ntb_transport_qp *qp) +{ + struct ntb_transport_ctx *nt =3D qp->transport; + + if (ntb_qp_edma_is_rc(qp)) + ntb_transport_edma_rc_poll(qp); + else if (ntb_qp_edma_is_ep(qp)) { + /* + * Make sure we poll the rings even if an eDMA interrupt is + * cleared on the RC side earlier. + */ + queue_work(nt->wq, &qp->read_work); + queue_work(nt->wq, &qp->write_work); + } else + /* Unreachable */ + WARN_ON_ONCE(1); +} + +static void ntb_transport_edma_read_work(struct work_struct *work) +{ + struct ntb_transport_qp *qp =3D container_of( + work, struct ntb_transport_qp, read_work); + + if (ntb_qp_edma_is_rc(qp)) + ntb_transport_edma_rc_read_complete_work(work); + else if (ntb_qp_edma_is_ep(qp)) + ntb_transport_edma_ep_read_work(work); + else + /* Unreachable */ + WARN_ON_ONCE(1); +} + +static void ntb_transport_edma_write_work(struct work_struct *work) +{ + struct ntb_transport_qp *qp =3D container_of( + work, struct ntb_transport_qp, write_work); + + if (ntb_qp_edma_is_rc(qp)) + ntb_transport_edma_rc_write_complete_work(work); + else if (ntb_qp_edma_is_ep(qp)) + ntb_transport_edma_ep_write_work(work); + else + /* Unreachable */ + WARN_ON_ONCE(1); +} + +static void ntb_transport_edma_init_queue(struct ntb_transport_ctx *nt, + unsigned int qp_num) +{ + struct ntb_transport_qp *qp =3D &nt->qp_vec[qp_num]; + + qp->wr_cons =3D 0; + qp->rd_cons =3D 0; + qp->wr_prod =3D 0; + qp->rd_prod =3D 0; + qp->wr_issue =3D 0; + qp->rd_issue =3D 0; + + INIT_WORK(&qp->db_work, ntb_transport_edma_db_work); + INIT_WORK(&qp->read_work, ntb_transport_edma_read_work); + INIT_WORK(&qp->write_work, ntb_transport_edma_write_work); +} + +static void ntb_transport_edma_create_queue(struct ntb_transport_ctx *nt, + struct ntb_transport_qp *qp) +{ + spin_lock_init(&qp->ep_tx_lock); + spin_lock_init(&qp->ep_rx_lock); + spin_lock_init(&qp->rc_lock); +} + +static const struct ntb_transport_backend_ops edma_backend_ops =3D { + .setup_qp_mw =3D ntb_transport_edma_setup_qp_mw, + .tx_free_entry =3D ntb_transport_edma_tx_free_entry, + .tx_enqueue =3D ntb_transport_edma_tx_enqueue, + .rx_enqueue =3D ntb_transport_edma_rx_enqueue, + .rx_poll =3D ntb_transport_edma_rx_poll, + .debugfs_stats_show =3D ntb_transport_edma_debugfs_stats_show, +}; +#endif /* CONFIG_NTB_TRANSPORT_EDMA */ + /** * ntb_transport_link_up - Notify NTB transport of client readiness to use= queue * @qp: NTB transport layer queue to be enabled --=20 2.48.1 From nobody Mon Dec 1 22:07:44 2025 Received: from TYVP286CU001.outbound.protection.outlook.com (mail-japaneastazon11011045.outbound.protection.outlook.com [52.101.125.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 908523164BC; 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Received: from TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:24c::11) by OS9P286MB4684.JPNP286.PROD.OUTLOOK.COM (2603:1096:604:2fa::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9366.17; Sat, 29 Nov 2025 16:04:40 +0000 Received: from TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM ([fe80::fb7e:f4ed:a580:9d03]) by TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM ([fe80::fb7e:f4ed:a580:9d03%5]) with mapi id 15.20.9366.012; Sat, 29 Nov 2025 16:04:40 +0000 From: Koichiro Den To: ntb@lists.linux.dev, linux-pci@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Frank.Li@nxp.com Cc: mani@kernel.org, kwilczynski@kernel.org, kishon@kernel.org, bhelgaas@google.com, corbet@lwn.net, vkoul@kernel.org, jdmason@kudzu.us, dave.jiang@intel.com, allenbh@gmail.com, Basavaraj.Natikar@amd.com, Shyam-sundar.S-k@amd.com, kurt.schwemmer@microsemi.com, logang@deltatee.com, jingoohan1@gmail.com, lpieralisi@kernel.org, robh@kernel.org, jbrunet@baylibre.com, fancer.lancer@gmail.com, arnd@arndb.de, pstanner@redhat.com, elfring@users.sourceforge.net Subject: [RFC PATCH v2 21/27] NTB: epf: Provide db_vector_count/db_vector_mask callbacks Date: Sun, 30 Nov 2025 01:03:59 +0900 Message-ID: <20251129160405.2568284-22-den@valinux.co.jp> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20251129160405.2568284-1-den@valinux.co.jp> References: <20251129160405.2568284-1-den@valinux.co.jp> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: TYCP286CA0196.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:385::7) To TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:24c::11) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TYWP286MB2697:EE_|OS9P286MB4684:EE_ X-MS-Office365-Filtering-Correlation-Id: cc1e461e-e19e-407f-92c2-08de2f6100c6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|366016|10070799003|1800799024; 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charset="utf-8" Provide db_vector_count() and db_vector_mask() implementations for both ntb_hw_epf and pci-epf-vntb so that ntb_transport can map MSI vectors to doorbell bits. Without them, the upper layer cannot identify which doorbell vector fired and ends up scheduling rxc_db_work() for all queue pairs, resulting in a thundering-herd effect when multiple queue pairs (QPs) are enabled. With this change, .peer_db_set() must honor the db_bits mask and raise all requested doorbell interrupts, so update those implementations accordingly. Signed-off-by: Koichiro Den --- drivers/ntb/hw/epf/ntb_hw_epf.c | 47 ++++++++++++------- drivers/pci/endpoint/functions/pci-epf-vntb.c | 40 +++++++++++++--- 2 files changed, 63 insertions(+), 24 deletions(-) diff --git a/drivers/ntb/hw/epf/ntb_hw_epf.c b/drivers/ntb/hw/epf/ntb_hw_ep= f.c index c94bf63d69ff..d9811da90599 100644 --- a/drivers/ntb/hw/epf/ntb_hw_epf.c +++ b/drivers/ntb/hw/epf/ntb_hw_epf.c @@ -363,7 +363,7 @@ static int ntb_epf_init_isr(struct ntb_epf_dev *ndev, i= nt msi_min, int msi_max) } } =20 - ndev->db_count =3D irq; + ndev->db_count =3D irq - 1; =20 ret =3D ntb_epf_send_command(ndev, CMD_CONFIGURE_DOORBELL, argument | irq); @@ -397,6 +397,22 @@ static u64 ntb_epf_db_valid_mask(struct ntb_dev *ntb) return ntb_ndev(ntb)->db_valid_mask; } =20 +static int ntb_epf_db_vector_count(struct ntb_dev *ntb) +{ + return ntb_ndev(ntb)->db_count; +} + +static u64 ntb_epf_db_vector_mask(struct ntb_dev *ntb, int db_vector) +{ + struct ntb_epf_dev *ndev =3D ntb_ndev(ntb); + + db_vector--; /* vector 0 is reserved for link events */ + if (db_vector < 0 || db_vector >=3D ndev->db_count) + return 0; + + return ndev->db_valid_mask & (1ULL << db_vector); +} + static int ntb_epf_db_set_mask(struct ntb_dev *ntb, u64 db_bits) { return 0; @@ -480,26 +496,21 @@ static int ntb_epf_peer_mw_get_addr(struct ntb_dev *n= tb, int idx, static int ntb_epf_peer_db_set(struct ntb_dev *ntb, u64 db_bits) { struct ntb_epf_dev *ndev =3D ntb_ndev(ntb); - u32 interrupt_num =3D ffs(db_bits) + 1; - struct device *dev =3D ndev->dev; + u32 interrupt_num; u32 db_entry_size; u32 db_offset; u32 db_data; - - if (interrupt_num >=3D ndev->db_count) { - dev_err(dev, "DB interrupt %d greater than Max Supported %d\n", - interrupt_num, ndev->db_count); - return -EINVAL; - } + int i; =20 db_entry_size =3D readl(ndev->ctrl_reg + NTB_EPF_DB_ENTRY_SIZE); =20 - db_data =3D readl(ndev->ctrl_reg + NTB_EPF_DB_DATA(interrupt_num)); - db_offset =3D readl(ndev->ctrl_reg + NTB_EPF_DB_OFFSET(interrupt_num)); - - writel(db_data, ndev->db_reg + (db_entry_size * interrupt_num) + - db_offset); - + for_each_set_bit(i, (unsigned long *)&db_bits, ndev->db_count) { + interrupt_num =3D i + 1; + db_data =3D readl(ndev->ctrl_reg + NTB_EPF_DB_DATA(interrupt_num)); + db_offset =3D readl(ndev->ctrl_reg + NTB_EPF_DB_OFFSET(interrupt_num)); + writel(db_data, ndev->db_reg + (db_entry_size * interrupt_num) + + db_offset); + } return 0; } =20 @@ -529,6 +540,8 @@ static const struct ntb_dev_ops ntb_epf_ops =3D { .spad_count =3D ntb_epf_spad_count, .peer_mw_count =3D ntb_epf_peer_mw_count, .db_valid_mask =3D ntb_epf_db_valid_mask, + .db_vector_count =3D ntb_epf_db_vector_count, + .db_vector_mask =3D ntb_epf_db_vector_mask, .db_set_mask =3D ntb_epf_db_set_mask, .mw_set_trans =3D ntb_epf_mw_set_trans, .mw_clear_trans =3D ntb_epf_mw_clear_trans, @@ -561,8 +574,8 @@ static int ntb_epf_init_dev(struct ntb_epf_dev *ndev) int ret; =20 /* One Link interrupt and rest doorbell interrupt */ - ret =3D ntb_epf_init_isr(ndev, NTB_EPF_MIN_DB_COUNT + NTB_EPF_IRQ_RESERVE, - NTB_EPF_MAX_DB_COUNT + NTB_EPF_IRQ_RESERVE); + ret =3D ntb_epf_init_isr(ndev, NTB_EPF_MIN_DB_COUNT + 1 + NTB_EPF_IRQ_RES= ERVE, + NTB_EPF_MAX_DB_COUNT + 1 + NTB_EPF_IRQ_RESERVE); if (ret) { dev_err(dev, "Failed to init ISR\n"); return ret; diff --git a/drivers/pci/endpoint/functions/pci-epf-vntb.c b/drivers/pci/en= dpoint/functions/pci-epf-vntb.c index 93fd724a8faa..af8753650051 100644 --- a/drivers/pci/endpoint/functions/pci-epf-vntb.c +++ b/drivers/pci/endpoint/functions/pci-epf-vntb.c @@ -1379,6 +1379,22 @@ static u64 vntb_epf_db_valid_mask(struct ntb_dev *nt= b) return BIT_ULL(ntb_ndev(ntb)->db_count) - 1; } =20 +static int vntb_epf_db_vector_count(struct ntb_dev *ntb) +{ + return ntb_ndev(ntb)->db_count; +} + +static u64 vntb_epf_db_vector_mask(struct ntb_dev *ntb, int db_vector) +{ + struct epf_ntb *ndev =3D ntb_ndev(ntb); + + db_vector--; /* vector 0 is reserved for link events */ + if (db_vector < 0 || db_vector >=3D ndev->db_count) + return 0; + + return 1ULL << db_vector; +} + static int vntb_epf_db_set_mask(struct ntb_dev *ntb, u64 db_bits) { return 0; @@ -1488,20 +1504,28 @@ static int vntb_epf_peer_spad_write(struct ntb_dev = *ndev, int pidx, int idx, u32 =20 static int vntb_epf_peer_db_set(struct ntb_dev *ndev, u64 db_bits) { - u32 interrupt_num =3D ffs(db_bits) + 1; struct epf_ntb *ntb =3D ntb_ndev(ndev); u8 func_no, vfunc_no; - int ret; + u64 failed =3D 0; + int i; =20 func_no =3D ntb->epf->func_no; vfunc_no =3D ntb->epf->vfunc_no; =20 - ret =3D pci_epc_raise_irq(ntb->epf->epc, func_no, vfunc_no, - PCI_IRQ_MSI, interrupt_num + 1); - if (ret) - dev_err(&ntb->ntb.dev, "Failed to raise IRQ\n"); + for_each_set_bit(i, (unsigned long *)&db_bits, ntb->db_count) { + /* + * DB bit i is MSI interrupt (i + 2). + * Vector 0 is used for link events and MSI vectors are + * 1-based for pci_epc_raise_irq(). + */ + if (pci_epc_raise_irq(ntb->epf->epc, func_no, vfunc_no, + PCI_IRQ_MSI, i + 2)) + failed |=3D BIT_ULL(i); + } + if (failed) + dev_err(&ntb->ntb.dev, "Failed to raise IRQ (0x%llx)\n", failed); =20 - return ret; + return failed ? -EIO : 0; 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Sat, 29 Nov 2025 16:04:41 +0000 From: Koichiro Den To: ntb@lists.linux.dev, linux-pci@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Frank.Li@nxp.com Cc: mani@kernel.org, kwilczynski@kernel.org, kishon@kernel.org, bhelgaas@google.com, corbet@lwn.net, vkoul@kernel.org, jdmason@kudzu.us, dave.jiang@intel.com, allenbh@gmail.com, Basavaraj.Natikar@amd.com, Shyam-sundar.S-k@amd.com, kurt.schwemmer@microsemi.com, logang@deltatee.com, jingoohan1@gmail.com, lpieralisi@kernel.org, robh@kernel.org, jbrunet@baylibre.com, fancer.lancer@gmail.com, arnd@arndb.de, pstanner@redhat.com, elfring@users.sourceforge.net Subject: [RFC PATCH v2 22/27] ntb_netdev: Multi-queue support Date: Sun, 30 Nov 2025 01:04:00 +0900 Message-ID: <20251129160405.2568284-23-den@valinux.co.jp> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20251129160405.2568284-1-den@valinux.co.jp> References: <20251129160405.2568284-1-den@valinux.co.jp> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: TYCP301CA0073.JPNP301.PROD.OUTLOOK.COM (2603:1096:405:7d::11) To TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:24c::11) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TYWP286MB2697:EE_|OS9P286MB4684:EE_ X-MS-Office365-Filtering-Correlation-Id: c0f1f13c-86b5-486c-1bba-08de2f610151 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|366016|10070799003|1800799024; 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charset="utf-8" ntb_transport can now scale throughput across multiple queue pairs when remote eDMA is enabled on ntb_transport (use_remote_edma=3D1). Teach ntb_netdev to allocate multiple ntb_transport queue pairs and expose them as a multi-queue net_device. In particular, when remote eDMA is enabled, each queue pair can be serviced in parallel by the eDMA engine. With this patch, up to N queue pairs are created, where N is chosen as follows: - By default, N is num_online_cpus(), to give each CPU its own queue. - If the ntb_num_queues module parameter is non-zero, it overrides the default and requests that many queues. - In both cases the requested value is capped at a fixed upper bound to avoid unbounded allocations, and by the number of queue pairs actually available from ntb_transport. If only one queue pair can be created (or ntb_num_queues=3D1 is set), the driver effectively falls back to the previous single-queue behaviour. Signed-off-by: Koichiro Den --- drivers/net/ntb_netdev.c | 341 ++++++++++++++++++++++++++++----------- 1 file changed, 243 insertions(+), 98 deletions(-) diff --git a/drivers/net/ntb_netdev.c b/drivers/net/ntb_netdev.c index fbeae05817e9..7aeca35b46c5 100644 --- a/drivers/net/ntb_netdev.c +++ b/drivers/net/ntb_netdev.c @@ -53,6 +53,8 @@ #include #include #include +#include +#include =20 #define NTB_NETDEV_VER "0.7" =20 @@ -70,26 +72,84 @@ static unsigned int tx_start =3D 10; /* Number of descriptors still available before stop upper layer tx */ static unsigned int tx_stop =3D 5; =20 +/* + * Upper bound on how many queue pairs we will try to create even if + * ntb_num_queues or num_online_cpus() is very large. This is an + * arbitrary safety cap to avoid unbounded allocations. + */ +#define NTB_NETDEV_MAX_QUEUES 64 + +/* + * ntb_num_queues =3D=3D 0 (default) means: + * - use num_online_cpus() as the desired queue count, capped by + * NTB_NETDEV_MAX_QUEUES. + * ntb_num_queues > 0: + * - try to create exactly ntb_num_queues queue pairs (again capped + * by NTB_NETDEV_MAX_QUEUES), but fall back to the number of queue + * pairs actually available from ntb_transport. + */ +static unsigned int ntb_num_queues; +module_param(ntb_num_queues, uint, 0644); +MODULE_PARM_DESC(ntb_num_queues, + "Number of NTB netdev queue pairs to use (0 =3D per-CPU)"); + +struct ntb_netdev; + +struct ntb_netdev_queue { + struct ntb_netdev *ntdev; + struct ntb_transport_qp *qp; + struct timer_list tx_timer; + u16 qid; +}; + struct ntb_netdev { struct pci_dev *pdev; struct net_device *ndev; - struct ntb_transport_qp *qp; - struct timer_list tx_timer; + unsigned int num_queues; + struct ntb_netdev_queue *queues; }; =20 #define NTB_TX_TIMEOUT_MS 1000 #define NTB_RXQ_SIZE 100 =20 +static unsigned int ntb_netdev_default_queues(void) +{ + unsigned int n; + + if (ntb_num_queues) + n =3D ntb_num_queues; + else + n =3D num_online_cpus(); + + if (!n) + n =3D 1; + + if (n > NTB_NETDEV_MAX_QUEUES) + n =3D NTB_NETDEV_MAX_QUEUES; + + return n; +} + static void ntb_netdev_event_handler(void *data, int link_is_up) { - struct net_device *ndev =3D data; - struct ntb_netdev *dev =3D netdev_priv(ndev); + struct ntb_netdev_queue *q =3D data; + struct ntb_netdev *dev =3D q->ntdev; + struct net_device *ndev =3D dev->ndev; + bool any_up =3D false; + unsigned int i; =20 - netdev_dbg(ndev, "Event %x, Link %x\n", link_is_up, - ntb_transport_link_query(dev->qp)); + netdev_dbg(ndev, "Event %x, Link %x, qp %u\n", link_is_up, + ntb_transport_link_query(q->qp), q->qid); =20 if (link_is_up) { - if (ntb_transport_link_query(dev->qp)) + for (i =3D 0; i < dev->num_queues; i++) { + if (ntb_transport_link_query(dev->queues[i].qp)) { + any_up =3D true; + break; + } + } + + if (any_up) netif_carrier_on(ndev); } else { netif_carrier_off(ndev); @@ -99,7 +159,9 @@ static void ntb_netdev_event_handler(void *data, int lin= k_is_up) static void ntb_netdev_rx_handler(struct ntb_transport_qp *qp, void *qp_da= ta, void *data, int len) { - struct net_device *ndev =3D qp_data; + struct ntb_netdev_queue *q =3D qp_data; + struct ntb_netdev *dev =3D q->ntdev; + struct net_device *ndev =3D dev->ndev; struct sk_buff *skb; int rc; =20 @@ -135,7 +197,8 @@ static void ntb_netdev_rx_handler(struct ntb_transport_= qp *qp, void *qp_data, } =20 enqueue_again: - rc =3D ntb_transport_rx_enqueue(qp, skb, skb->data, ndev->mtu + ETH_HLEN); + rc =3D ntb_transport_rx_enqueue(q->qp, skb, skb->data, + ndev->mtu + ETH_HLEN); if (rc) { dev_kfree_skb_any(skb); ndev->stats.rx_errors++; @@ -143,42 +206,37 @@ static void ntb_netdev_rx_handler(struct ntb_transpor= t_qp *qp, void *qp_data, } } =20 -static int __ntb_netdev_maybe_stop_tx(struct net_device *netdev, - struct ntb_transport_qp *qp, int size) +static int ntb_netdev_maybe_stop_tx(struct ntb_netdev_queue *q, int size) { - struct ntb_netdev *dev =3D netdev_priv(netdev); + struct net_device *ndev =3D q->ntdev->ndev; + + if (ntb_transport_tx_free_entry(q->qp) >=3D size) + return 0; + + netif_stop_subqueue(ndev, q->qid); =20 - netif_stop_queue(netdev); /* Make sure to see the latest value of ntb_transport_tx_free_entry() * since the queue was last started. */ smp_mb(); =20 - if (likely(ntb_transport_tx_free_entry(qp) < size)) { - mod_timer(&dev->tx_timer, jiffies + usecs_to_jiffies(tx_time)); + if (likely(ntb_transport_tx_free_entry(q->qp) < size)) { + mod_timer(&q->tx_timer, jiffies + usecs_to_jiffies(tx_time)); return -EBUSY; } =20 - netif_start_queue(netdev); - return 0; -} - -static int ntb_netdev_maybe_stop_tx(struct net_device *ndev, - struct ntb_transport_qp *qp, int size) -{ - if (netif_queue_stopped(ndev) || - (ntb_transport_tx_free_entry(qp) >=3D size)) - return 0; + netif_wake_subqueue(ndev, q->qid); =20 - return __ntb_netdev_maybe_stop_tx(ndev, qp, size); + return 0; } =20 static void ntb_netdev_tx_handler(struct ntb_transport_qp *qp, void *qp_da= ta, void *data, int len) { - struct net_device *ndev =3D qp_data; + struct ntb_netdev_queue *q =3D qp_data; + struct ntb_netdev *dev =3D q->ntdev; + struct net_device *ndev =3D dev->ndev; struct sk_buff *skb; - struct ntb_netdev *dev =3D netdev_priv(ndev); =20 skb =3D data; if (!skb || !ndev) @@ -194,13 +252,12 @@ static void ntb_netdev_tx_handler(struct ntb_transpor= t_qp *qp, void *qp_data, =20 dev_kfree_skb_any(skb); =20 - if (ntb_transport_tx_free_entry(dev->qp) >=3D tx_start) { + if (ntb_transport_tx_free_entry(qp) >=3D tx_start) { /* Make sure anybody stopping the queue after this sees the new * value of ntb_transport_tx_free_entry() */ smp_mb(); - if (netif_queue_stopped(ndev)) - netif_wake_queue(ndev); + netif_wake_subqueue(ndev, q->qid); } } =20 @@ -208,16 +265,26 @@ static netdev_tx_t ntb_netdev_start_xmit(struct sk_bu= ff *skb, struct net_device *ndev) { struct ntb_netdev *dev =3D netdev_priv(ndev); + u16 qid =3D skb_get_queue_mapping(skb); + struct ntb_netdev_queue *q; int rc; =20 - ntb_netdev_maybe_stop_tx(ndev, dev->qp, tx_stop); + if (unlikely(!dev->num_queues)) + goto err; + + if (unlikely(qid >=3D dev->num_queues)) + qid =3D qid % dev->num_queues; =20 - rc =3D ntb_transport_tx_enqueue(dev->qp, skb, skb->data, skb->len); + q =3D &dev->queues[qid]; + + ntb_netdev_maybe_stop_tx(q, tx_stop); + + rc =3D ntb_transport_tx_enqueue(q->qp, skb, skb->data, skb->len); if (rc) goto err; =20 /* check for next submit */ - ntb_netdev_maybe_stop_tx(ndev, dev->qp, tx_stop); + ntb_netdev_maybe_stop_tx(q, tx_stop); =20 return NETDEV_TX_OK; =20 @@ -229,80 +296,103 @@ static netdev_tx_t ntb_netdev_start_xmit(struct sk_b= uff *skb, =20 static void ntb_netdev_tx_timer(struct timer_list *t) { - struct ntb_netdev *dev =3D timer_container_of(dev, t, tx_timer); + struct ntb_netdev_queue *q =3D container_of(t, struct ntb_netdev_queue, t= x_timer); + struct ntb_netdev *dev =3D q->ntdev; struct net_device *ndev =3D dev->ndev; =20 - if (ntb_transport_tx_free_entry(dev->qp) < tx_stop) { - mod_timer(&dev->tx_timer, jiffies + usecs_to_jiffies(tx_time)); + if (ntb_transport_tx_free_entry(q->qp) < tx_stop) { + mod_timer(&q->tx_timer, jiffies + usecs_to_jiffies(tx_time)); } else { - /* Make sure anybody stopping the queue after this sees the new + /* + * Make sure anybody stopping the queue after this sees the new * value of ntb_transport_tx_free_entry() */ smp_mb(); - if (netif_queue_stopped(ndev)) - netif_wake_queue(ndev); + netif_wake_subqueue(ndev, q->qid); } } =20 static int ntb_netdev_open(struct net_device *ndev) { struct ntb_netdev *dev =3D netdev_priv(ndev); + struct ntb_netdev_queue *queue; struct sk_buff *skb; - int rc, i, len; - - /* Add some empty rx bufs */ - for (i =3D 0; i < NTB_RXQ_SIZE; i++) { - skb =3D netdev_alloc_skb(ndev, ndev->mtu + ETH_HLEN); - if (!skb) { - rc =3D -ENOMEM; - goto err; - } + int rc =3D 0, i, len; + unsigned int q; =20 - rc =3D ntb_transport_rx_enqueue(dev->qp, skb, skb->data, - ndev->mtu + ETH_HLEN); - if (rc) { - dev_kfree_skb(skb); - goto err; + /* Add some empty rx bufs for each queue */ + for (q =3D 0; q < dev->num_queues; q++) { + queue =3D &dev->queues[q]; + + for (i =3D 0; i < NTB_RXQ_SIZE; i++) { + skb =3D netdev_alloc_skb(ndev, ndev->mtu + ETH_HLEN); + if (!skb) { + rc =3D -ENOMEM; + goto err; + } + + rc =3D ntb_transport_rx_enqueue(queue->qp, skb, skb->data, + ndev->mtu + ETH_HLEN); + if (rc) { + dev_kfree_skb(skb); + goto err; + } } - } =20 - timer_setup(&dev->tx_timer, ntb_netdev_tx_timer, 0); + timer_setup(&queue->tx_timer, ntb_netdev_tx_timer, 0); + } =20 netif_carrier_off(ndev); - ntb_transport_link_up(dev->qp); - netif_start_queue(ndev); + + for (q =3D 0; q < dev->num_queues; q++) + ntb_transport_link_up(dev->queues[q].qp); + + netif_tx_start_all_queues(ndev); =20 return 0; =20 err: - while ((skb =3D ntb_transport_rx_remove(dev->qp, &len))) - dev_kfree_skb(skb); + for (q =3D 0; q < dev->num_queues; q++) { + queue =3D &dev->queues[q]; + + while ((skb =3D ntb_transport_rx_remove(queue->qp, &len))) + dev_kfree_skb(skb); + } return rc; } =20 static int ntb_netdev_close(struct net_device *ndev) { struct ntb_netdev *dev =3D netdev_priv(ndev); + struct ntb_netdev_queue *queue; struct sk_buff *skb; + unsigned int q; int len; =20 - ntb_transport_link_down(dev->qp); + netif_tx_stop_all_queues(ndev); + + for (q =3D 0; q < dev->num_queues; q++) { + queue =3D &dev->queues[q]; =20 - while ((skb =3D ntb_transport_rx_remove(dev->qp, &len))) - dev_kfree_skb(skb); + ntb_transport_link_down(queue->qp); =20 - timer_delete_sync(&dev->tx_timer); + while ((skb =3D ntb_transport_rx_remove(queue->qp, &len))) + dev_kfree_skb(skb); =20 + timer_delete_sync(&queue->tx_timer); + } return 0; } =20 static int ntb_netdev_change_mtu(struct net_device *ndev, int new_mtu) { struct ntb_netdev *dev =3D netdev_priv(ndev); + struct ntb_netdev_queue *queue; struct sk_buff *skb; - int len, rc; + unsigned int q, i; + int len, rc =3D 0; =20 - if (new_mtu > ntb_transport_max_size(dev->qp) - ETH_HLEN) + if (new_mtu > ntb_transport_max_size(dev->queues[0].qp) - ETH_HLEN) return -EINVAL; =20 if (!netif_running(ndev)) { @@ -311,41 +401,54 @@ static int ntb_netdev_change_mtu(struct net_device *n= dev, int new_mtu) } =20 /* Bring down the link and dispose of posted rx entries */ - ntb_transport_link_down(dev->qp); + for (q =3D 0; q < dev->num_queues; q++) + ntb_transport_link_down(dev->queues[0].qp); =20 if (ndev->mtu < new_mtu) { - int i; - - for (i =3D 0; (skb =3D ntb_transport_rx_remove(dev->qp, &len)); i++) - dev_kfree_skb(skb); + for (q =3D 0; q < dev->num_queues; q++) { + queue =3D &dev->queues[q]; =20 - for (; i; i--) { - skb =3D netdev_alloc_skb(ndev, new_mtu + ETH_HLEN); - if (!skb) { - rc =3D -ENOMEM; - goto err; - } - - rc =3D ntb_transport_rx_enqueue(dev->qp, skb, skb->data, - new_mtu + ETH_HLEN); - if (rc) { + for (i =3D 0; + (skb =3D ntb_transport_rx_remove(queue->qp, &len)); + i++) dev_kfree_skb(skb); - goto err; + + for (; i; i--) { + skb =3D netdev_alloc_skb(ndev, + new_mtu + ETH_HLEN); + if (!skb) { + rc =3D -ENOMEM; + goto err; + } + + rc =3D ntb_transport_rx_enqueue(queue->qp, skb, + skb->data, + new_mtu + + ETH_HLEN); + if (rc) { + dev_kfree_skb(skb); + goto err; + } } } } =20 WRITE_ONCE(ndev->mtu, new_mtu); =20 - ntb_transport_link_up(dev->qp); + for (q =3D 0; q < dev->num_queues; q++) + ntb_transport_link_up(dev->queues[q].qp); =20 return 0; =20 err: - ntb_transport_link_down(dev->qp); + for (q =3D 0; q < dev->num_queues; q++) { + struct ntb_netdev_queue *queue =3D &dev->queues[q]; + + ntb_transport_link_down(queue->qp); =20 - while ((skb =3D ntb_transport_rx_remove(dev->qp, &len))) - dev_kfree_skb(skb); + while ((skb =3D ntb_transport_rx_remove(queue->qp, &len))) + dev_kfree_skb(skb); + } =20 netdev_err(ndev, "Error changing MTU, device inoperable\n"); return rc; @@ -404,6 +507,7 @@ static int ntb_netdev_probe(struct device *client_dev) struct net_device *ndev; struct pci_dev *pdev; struct ntb_netdev *dev; + unsigned int q, desired_queues; int rc; =20 ntb =3D dev_ntb(client_dev->parent); @@ -411,7 +515,9 @@ static int ntb_netdev_probe(struct device *client_dev) if (!pdev) return -ENODEV; =20 - ndev =3D alloc_etherdev(sizeof(*dev)); + desired_queues =3D ntb_netdev_default_queues(); + + ndev =3D alloc_etherdev_mq(sizeof(*dev), desired_queues); if (!ndev) return -ENOMEM; =20 @@ -420,6 +526,15 @@ static int ntb_netdev_probe(struct device *client_dev) dev =3D netdev_priv(ndev); dev->ndev =3D ndev; dev->pdev =3D pdev; + dev->num_queues =3D 0; + + dev->queues =3D kcalloc(desired_queues, sizeof(*dev->queues), + GFP_KERNEL); + if (!dev->queues) { + rc =3D -ENOMEM; + goto err_free_netdev; + } + ndev->features =3D NETIF_F_HIGHDMA; =20 ndev->priv_flags |=3D IFF_LIVE_ADDR_CHANGE; @@ -436,26 +551,51 @@ static int ntb_netdev_probe(struct device *client_dev) ndev->min_mtu =3D 0; ndev->max_mtu =3D ETH_MAX_MTU; =20 - dev->qp =3D ntb_transport_create_queue(ndev, client_dev, - &ntb_netdev_handlers); - if (!dev->qp) { + for (q =3D 0; q < desired_queues; q++) { + struct ntb_netdev_queue *queue =3D &dev->queues[q]; + + queue->ntdev =3D dev; + queue->qid =3D q; + queue->qp =3D ntb_transport_create_queue(queue, client_dev, + &ntb_netdev_handlers); + if (!queue->qp) + break; + + dev->num_queues++; + } + + if (!dev->num_queues) { rc =3D -EIO; - goto err; + goto err_free_queues; } =20 - ndev->mtu =3D ntb_transport_max_size(dev->qp) - ETH_HLEN; + rc =3D netif_set_real_num_tx_queues(ndev, dev->num_queues); + if (rc) + goto err_free_qps; + + rc =3D netif_set_real_num_rx_queues(ndev, dev->num_queues); + if (rc) + goto err_free_qps; + + ndev->mtu =3D ntb_transport_max_size(dev->queues[0].qp) - ETH_HLEN; =20 rc =3D register_netdev(ndev); if (rc) - goto err1; + goto err_free_qps; =20 dev_set_drvdata(client_dev, ndev); - dev_info(&pdev->dev, "%s created\n", ndev->name); + dev_info(&pdev->dev, "%s created with %u queue pairs\n", + ndev->name, dev->num_queues); return 0; =20 -err1: - ntb_transport_free_queue(dev->qp); -err: +err_free_qps: + for (q =3D 0; q < dev->num_queues; q++) + ntb_transport_free_queue(dev->queues[q].qp); + +err_free_queues: + kfree(dev->queues); + +err_free_netdev: free_netdev(ndev); return rc; } @@ -464,9 +604,14 @@ static void ntb_netdev_remove(struct device *client_de= v) { struct net_device *ndev =3D dev_get_drvdata(client_dev); struct ntb_netdev *dev =3D netdev_priv(ndev); + unsigned int q; + =20 unregister_netdev(ndev); - ntb_transport_free_queue(dev->qp); + for (q =3D 0; q < dev->num_queues; q++) + ntb_transport_free_queue(dev->queues[q].qp); + + kfree(dev->queues); free_netdev(ndev); } =20 --=20 2.48.1 From nobody Mon Dec 1 22:07:44 2025 Received: from TY3P286CU002.outbound.protection.outlook.com (mail-japaneastazon11010018.outbound.protection.outlook.com [52.101.229.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5027F3191BD; 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Received: from TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:24c::11) by OS9P286MB4684.JPNP286.PROD.OUTLOOK.COM (2603:1096:604:2fa::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9366.17; Sat, 29 Nov 2025 16:04:42 +0000 Received: from TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM ([fe80::fb7e:f4ed:a580:9d03]) by TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM ([fe80::fb7e:f4ed:a580:9d03%5]) with mapi id 15.20.9366.012; Sat, 29 Nov 2025 16:04:42 +0000 From: Koichiro Den To: ntb@lists.linux.dev, linux-pci@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Frank.Li@nxp.com Cc: mani@kernel.org, kwilczynski@kernel.org, kishon@kernel.org, bhelgaas@google.com, corbet@lwn.net, vkoul@kernel.org, jdmason@kudzu.us, dave.jiang@intel.com, allenbh@gmail.com, Basavaraj.Natikar@amd.com, Shyam-sundar.S-k@amd.com, kurt.schwemmer@microsemi.com, logang@deltatee.com, jingoohan1@gmail.com, lpieralisi@kernel.org, robh@kernel.org, jbrunet@baylibre.com, fancer.lancer@gmail.com, arnd@arndb.de, pstanner@redhat.com, elfring@users.sourceforge.net Subject: [RFC PATCH v2 23/27] NTB: epf: Add per-SoC quirk to cap MRRS for DWC eDMA (128B for R-Car) Date: Sun, 30 Nov 2025 01:04:01 +0900 Message-ID: <20251129160405.2568284-24-den@valinux.co.jp> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20251129160405.2568284-1-den@valinux.co.jp> References: <20251129160405.2568284-1-den@valinux.co.jp> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: TYCP286CA0144.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:31b::8) To TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:24c::11) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TYWP286MB2697:EE_|OS9P286MB4684:EE_ X-MS-Office365-Filtering-Correlation-Id: 61b84d6e-addc-4f13-8244-08de2f6101fe X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|366016|10070799003|1800799024; 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charset="utf-8" Some R-Car platforms using Synopsys DesignWare PCIe with the integrated eDMA exhibit reproducible payload corruption in RC->EP remote DMA read traffic whenever the endpoint issues 256-byte Memory Read (MRd) TLPs. The eDMA injects multiple MRd requests of size less than or equal to min(MRRS, MPS), so constraining the endpoint's MRd request size removes 256-byte MRd TLPs and avoids the issue. This change adds a per-SoC knob in the ntb_hw_epf driver and sets MRRS=3D128 on R-Car. We intentionally do not change the endpoint's MPS. Per PCIe Base Specification, MPS limits the payload size of TLPs with data transmitted by the Function, while Max_Read_Request_Size limits the size of read requests produced by the Function as a Requester. Limiting MRRS is sufficient to constrain MRd Byte Count, while lowering MPS would also throttle unrelated traffic (e.g. endpoint-originated Posted Writes and Completions with Data) without being necessary for this fix. This quirk is scoped to the affected endpoint only and can be removed once the underlying issue is resolved in the controller/IP. Signed-off-by: Koichiro Den Reviewed-by: Frank Li --- drivers/ntb/hw/epf/ntb_hw_epf.c | 66 +++++++++++++++++++++++++++++---- 1 file changed, 58 insertions(+), 8 deletions(-) diff --git a/drivers/ntb/hw/epf/ntb_hw_epf.c b/drivers/ntb/hw/epf/ntb_hw_ep= f.c index d9811da90599..21eb26b2f7cc 100644 --- a/drivers/ntb/hw/epf/ntb_hw_epf.c +++ b/drivers/ntb/hw/epf/ntb_hw_epf.c @@ -51,6 +51,12 @@ =20 #define NTB_EPF_COMMAND_TIMEOUT 1000 /* 1 Sec */ =20 +struct ntb_epf_soc_data { + const enum pci_barno *barno_map; + /* non-zero to override MRRS for this SoC */ + int force_mrrs; +}; + enum epf_ntb_bar { BAR_CONFIG, BAR_PEER_SPAD, @@ -594,11 +600,12 @@ static int ntb_epf_init_dev(struct ntb_epf_dev *ndev) } =20 static int ntb_epf_init_pci(struct ntb_epf_dev *ndev, - struct pci_dev *pdev) + struct pci_dev *pdev, + const struct ntb_epf_soc_data *soc) { struct device *dev =3D ndev->dev; size_t spad_sz, spad_off; - int ret; + int ret, cur; =20 pci_set_drvdata(pdev, ndev); =20 @@ -616,6 +623,17 @@ static int ntb_epf_init_pci(struct ntb_epf_dev *ndev, =20 pci_set_master(pdev); =20 + if (soc && pci_is_pcie(pdev) && soc->force_mrrs) { + cur =3D pcie_get_readrq(pdev); + ret =3D pcie_set_readrq(pdev, soc->force_mrrs); + if (ret) + dev_warn(&pdev->dev, "failed to set MRRS=3D%d: %d\n", + soc->force_mrrs, ret); + else + dev_info(&pdev->dev, "capped MRRS: %d->%d for ntb-epf\n", + cur, soc->force_mrrs); + } + ret =3D dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); if (ret) { ret =3D dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); @@ -690,6 +708,7 @@ static void ntb_epf_cleanup_isr(struct ntb_epf_dev *nde= v) static int ntb_epf_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { + const struct ntb_epf_soc_data *soc =3D (const void *)id->driver_data; struct device *dev =3D &pdev->dev; struct ntb_epf_dev *ndev; int ret; @@ -701,16 +720,16 @@ static int ntb_epf_pci_probe(struct pci_dev *pdev, if (!ndev) return -ENOMEM; =20 - ndev->barno_map =3D (const enum pci_barno *)id->driver_data; - if (!ndev->barno_map) + if (!soc || !soc->barno_map) return -EINVAL; =20 + ndev->barno_map =3D soc->barno_map; ndev->dev =3D dev; =20 ntb_epf_init_struct(ndev, pdev); mutex_init(&ndev->cmd_lock); =20 - ret =3D ntb_epf_init_pci(ndev, pdev); + ret =3D ntb_epf_init_pci(ndev, pdev, soc); if (ret) { dev_err(dev, "Failed to init PCI\n"); return ret; @@ -778,21 +797,52 @@ static const enum pci_barno rcar_barno[NTB_BAR_NUM] = =3D { [BAR_MW4] =3D NO_BAR, }; =20 +static const struct ntb_epf_soc_data j721e_soc =3D { + .barno_map =3D j721e_map, +}; + +static const struct ntb_epf_soc_data mx8_soc =3D { + .barno_map =3D mx8_map, +}; + +static const struct ntb_epf_soc_data rcar_soc =3D { + .barno_map =3D rcar_barno, + /* + * On some R-Car platforms using the Synopsys DWC PCIe + eDMA we + * observe data corruption on RC->EP Remote DMA Read paths whenever + * the EP issues large MRd requests. The corruption consistently + * hits the tail of each 256-byte segment (e.g. offsets + * 0x00E0..0x00FF within a 256B block, and again at 0x01E0..0x01FF + * for larger transfers). + * + * The DMA injects multiple MRd requests of size less than or equal + * to the min(MRRS, MPS) into the outbound request path. By + * lowering MRRS to 128 we prevent 256B MRd TLPs from being + * generated and avoid the issue on the affected hardware. We + * intentionally keep MPS unchanged and scope this quirk to this + * endpoint to avoid impacting unrelated devices. + * + * Remove this once the issue is resolved (maybe controller/IP + * level) or a more preferable workaround becomes available. + */ + .force_mrrs =3D 128, +}; + static const struct pci_device_id ntb_epf_pci_tbl[] =3D { { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J721E), .class =3D PCI_CLASS_MEMORY_RAM << 8, .class_mask =3D 0xffff00, - .driver_data =3D (kernel_ulong_t)j721e_map, + .driver_data =3D (kernel_ulong_t)&j721e_soc, }, { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0x0809), .class =3D PCI_CLASS_MEMORY_RAM << 8, .class_mask =3D 0xffff00, - .driver_data =3D (kernel_ulong_t)mx8_map, + .driver_data =3D (kernel_ulong_t)&mx8_soc, }, { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, 0x0030), .class =3D PCI_CLASS_MEMORY_RAM << 8, .class_mask =3D 0xffff00, - .driver_data =3D (kernel_ulong_t)rcar_barno, + .driver_data =3D (kernel_ulong_t)&rcar_soc, }, { }, }; --=20 2.48.1 From nobody Mon Dec 1 22:07:44 2025 Received: from TYVP286CU001.outbound.protection.outlook.com (mail-japaneastazon11011045.outbound.protection.outlook.com [52.101.125.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F749319847; 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Received: from TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:24c::11) by OS9P286MB4684.JPNP286.PROD.OUTLOOK.COM (2603:1096:604:2fa::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9366.17; Sat, 29 Nov 2025 16:04:43 +0000 Received: from TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM ([fe80::fb7e:f4ed:a580:9d03]) by TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM ([fe80::fb7e:f4ed:a580:9d03%5]) with mapi id 15.20.9366.012; Sat, 29 Nov 2025 16:04:43 +0000 From: Koichiro Den To: ntb@lists.linux.dev, linux-pci@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Frank.Li@nxp.com Cc: mani@kernel.org, kwilczynski@kernel.org, kishon@kernel.org, bhelgaas@google.com, corbet@lwn.net, vkoul@kernel.org, jdmason@kudzu.us, dave.jiang@intel.com, allenbh@gmail.com, Basavaraj.Natikar@amd.com, Shyam-sundar.S-k@amd.com, kurt.schwemmer@microsemi.com, logang@deltatee.com, jingoohan1@gmail.com, lpieralisi@kernel.org, robh@kernel.org, jbrunet@baylibre.com, fancer.lancer@gmail.com, arnd@arndb.de, pstanner@redhat.com, elfring@users.sourceforge.net Subject: [RFC PATCH v2 24/27] iommu: ipmmu-vmsa: Add PCIe ch0 to devices_allowlist Date: Sun, 30 Nov 2025 01:04:02 +0900 Message-ID: <20251129160405.2568284-25-den@valinux.co.jp> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20251129160405.2568284-1-den@valinux.co.jp> References: <20251129160405.2568284-1-den@valinux.co.jp> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: TYCPR01CA0137.jpnprd01.prod.outlook.com (2603:1096:400:2b7::13) To TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:24c::11) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TYWP286MB2697:EE_|OS9P286MB4684:EE_ X-MS-Office365-Filtering-Correlation-Id: fd4c6f6d-31fc-443c-36d2-08de2f610290 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|366016|10070799003|1800799024; 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charset="utf-8" Add the PCIe ch0 to the ipmmu-vmsa devices_allowlist so that traffic routed through this PCIe instance can be translated by the IOMMU. Signed-off-by: Koichiro Den --- drivers/iommu/ipmmu-vmsa.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c index ca848288dbf2..724d67ad5ef2 100644 --- a/drivers/iommu/ipmmu-vmsa.c +++ b/drivers/iommu/ipmmu-vmsa.c @@ -743,7 +743,9 @@ static const char * const devices_allowlist[] =3D { "ee100000.mmc", "ee120000.mmc", "ee140000.mmc", - "ee160000.mmc" + "ee160000.mmc", + "e65d0000.pcie", + "e65d0000.pcie-ep", }; =20 static bool ipmmu_device_is_allowed(struct device *dev) --=20 2.48.1 From nobody Mon Dec 1 22:07:44 2025 Received: from TY3P286CU002.outbound.protection.outlook.com (mail-japaneastazon11010018.outbound.protection.outlook.com [52.101.229.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BD77930F814; Sat, 29 Nov 2025 16:04:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.229.18 ARC-Seal: i=2; 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charset="utf-8" Add support for reserved regions using iommu_dma_get_resv_regions(). Signed-off-by: Koichiro Den --- drivers/iommu/ipmmu-vmsa.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c index 724d67ad5ef2..4a89d95db0f8 100644 --- a/drivers/iommu/ipmmu-vmsa.c +++ b/drivers/iommu/ipmmu-vmsa.c @@ -25,6 +25,8 @@ #include #include =20 +#include "dma-iommu.h" + #if defined(CONFIG_ARM) && !defined(CONFIG_IOMMU_DMA) #include #else @@ -888,6 +890,7 @@ static const struct iommu_ops ipmmu_ops =3D { .device_group =3D IS_ENABLED(CONFIG_ARM) && !IS_ENABLED(CONFIG_IOMMU_DMA) ? generic_device_group : generic_single_device_group, .of_xlate =3D ipmmu_of_xlate, + .get_resv_regions =3D iommu_dma_get_resv_regions, .default_domain_ops =3D &(const struct iommu_domain_ops) { .attach_dev =3D ipmmu_attach_device, .map_pages =3D ipmmu_map, --=20 2.48.1 From nobody Mon Dec 1 22:07:44 2025 Received: from TYVP286CU001.outbound.protection.outlook.com (mail-japaneastazon11011045.outbound.protection.outlook.com [52.101.125.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0CB8D31A7E6; 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Received: from TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:24c::11) by OS9P286MB4684.JPNP286.PROD.OUTLOOK.COM (2603:1096:604:2fa::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9366.17; Sat, 29 Nov 2025 16:04:45 +0000 Received: from TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM ([fe80::fb7e:f4ed:a580:9d03]) by TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM ([fe80::fb7e:f4ed:a580:9d03%5]) with mapi id 15.20.9366.012; Sat, 29 Nov 2025 16:04:45 +0000 From: Koichiro Den To: ntb@lists.linux.dev, linux-pci@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Frank.Li@nxp.com Cc: mani@kernel.org, kwilczynski@kernel.org, kishon@kernel.org, bhelgaas@google.com, corbet@lwn.net, vkoul@kernel.org, jdmason@kudzu.us, dave.jiang@intel.com, allenbh@gmail.com, Basavaraj.Natikar@amd.com, Shyam-sundar.S-k@amd.com, kurt.schwemmer@microsemi.com, logang@deltatee.com, jingoohan1@gmail.com, lpieralisi@kernel.org, robh@kernel.org, jbrunet@baylibre.com, fancer.lancer@gmail.com, arnd@arndb.de, pstanner@redhat.com, elfring@users.sourceforge.net Subject: [RFC PATCH v2 26/27] arm64: dts: renesas: Add Spider RC/EP DTs for NTB with remote DW PCIe eDMA Date: Sun, 30 Nov 2025 01:04:04 +0900 Message-ID: <20251129160405.2568284-27-den@valinux.co.jp> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20251129160405.2568284-1-den@valinux.co.jp> References: <20251129160405.2568284-1-den@valinux.co.jp> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: TYCP301CA0057.JPNP301.PROD.OUTLOOK.COM (2603:1096:400:384::8) To TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:24c::11) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TYWP286MB2697:EE_|OS9P286MB4684:EE_ X-MS-Office365-Filtering-Correlation-Id: 2e8889ed-6ac5-426f-c617-08de2f6103c4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|366016|10070799003|1800799024; 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charset="utf-8" Add dedicated DTs for the Spider CPU+BreakOut boards when used in PCIe RC/EP mode with DW PCIe eDMA based NTB transport. * r8a779f0-spider-rc.dts describes the board in RC mode. It reserves 4 MiB of IOVA starting at 0xfe000000, which on this SoC is the ECAM/Config aperture of the PCIe host bridge. In stress testing with the remote eDMA, allowing generic DMA mappings to occupy this range led to immediate instability. The exact mechanism is under investigation, but reserving the range avoids the issue in practice. * r8a779f0-spider-ep.dts describes the board in EP mode. The RC interface is disabled and the EP interface is enabled. IPMMU usage matches the RC case. The base r8a779f0-spider.dts is intentionally left unchanged and continues to describe the default RC-only board configuration. Signed-off-by: Koichiro Den --- arch/arm64/boot/dts/renesas/Makefile | 2 + .../boot/dts/renesas/r8a779f0-spider-ep.dts | 46 ++++++++++++++++ .../boot/dts/renesas/r8a779f0-spider-rc.dts | 52 +++++++++++++++++++ 3 files changed, 100 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a779f0-spider-ep.dts create mode 100644 arch/arm64/boot/dts/renesas/r8a779f0-spider-rc.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/ren= esas/Makefile index 1fab1b50f20e..e8d312be515b 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -82,6 +82,8 @@ dtb-$(CONFIG_ARCH_R8A77995) +=3D r8a77995-draak-panel-aa1= 04xd12.dtb dtb-$(CONFIG_ARCH_R8A779A0) +=3D r8a779a0-falcon.dtb =20 dtb-$(CONFIG_ARCH_R8A779F0) +=3D r8a779f0-spider.dtb +dtb-$(CONFIG_ARCH_R8A779F0) +=3D r8a779f0-spider-ep.dtb +dtb-$(CONFIG_ARCH_R8A779F0) +=3D r8a779f0-spider-rc.dtb dtb-$(CONFIG_ARCH_R8A779F0) +=3D r8a779f4-s4sk.dtb =20 dtb-$(CONFIG_ARCH_R8A779G0) +=3D r8a779g0-white-hawk.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-ep.dts b/arch/arm6= 4/boot/dts/renesas/r8a779f0-spider-ep.dts new file mode 100644 index 000000000000..9c9e29226458 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-ep.dts @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/* + * Device Tree Source for the Spider CPU and BreakOut boards + * (PCIe EP mode with DW PCIe eDMA used for NTB transport) + * + * Based on the base r8a779f0-spider.dts. + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a779f0-spider-cpu.dtsi" +#include "r8a779f0-spider-ethernet.dtsi" + +/ { + model =3D "Renesas Spider CPU and Breakout boards based on r8a779f0"; + compatible =3D "renesas,spider-breakout", "renesas,spider-cpu", + "renesas,r8a779f0"; +}; + +&i2c4 { + eeprom@51 { + compatible =3D "rohm,br24g01", "atmel,24c01"; + label =3D "breakout-board"; + reg =3D <0x51>; + pagesize =3D <8>; + }; +}; + +&pciec0 { + status =3D "disabled"; +}; + +&pciec0_ep { + iommus =3D <&ipmmu_hc 32>; + status =3D "okay"; + /* Hide eDMA from generic EP users, it is driven by host side remotely */ + reg =3D <0 0xe65d0000 0 0x2000>, <0 0xe65d2000 0 0x1000>, + <0 0xe65d3000 0 0x2000>, <0 0xe65d6200 0 0x0e00>, + <0 0xe65d7000 0 0x0400>, <0 0xfe000000 0 0x400000>; + reg-names =3D "dbi", "dbi2", "atu", "app", "phy", "addr_space"; + interrupts =3D , + ; + interrupt-names =3D "sft_ce", "app"; + interrupt-parent =3D <&gic>; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-rc.dts b/arch/arm6= 4/boot/dts/renesas/r8a779f0-spider-rc.dts new file mode 100644 index 000000000000..c7112862e1e1 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-rc.dts @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree Source for the Spider CPU and BreakOut boards + * (PCIe RC mode with remote DW PCIe eDMA used for NTB transport) + * + * Based on the base r8a779f0-spider.dts. + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a779f0-spider-cpu.dtsi" +#include "r8a779f0-spider-ethernet.dtsi" + +/ { + model =3D "Renesas Spider CPU and Breakout boards based on r8a779f0"; + compatible =3D "renesas,spider-breakout", "renesas,spider-cpu", + "renesas,r8a779f0"; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + /* + * Reserve 4 MiB of IOVA starting at 0xfe000000. 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Received: from TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:24c::11) by OS9P286MB4684.JPNP286.PROD.OUTLOOK.COM (2603:1096:604:2fa::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9366.17; Sat, 29 Nov 2025 16:04:46 +0000 Received: from TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM ([fe80::fb7e:f4ed:a580:9d03]) by TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM ([fe80::fb7e:f4ed:a580:9d03%5]) with mapi id 15.20.9366.012; Sat, 29 Nov 2025 16:04:46 +0000 From: Koichiro Den To: ntb@lists.linux.dev, linux-pci@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Frank.Li@nxp.com Cc: mani@kernel.org, kwilczynski@kernel.org, kishon@kernel.org, bhelgaas@google.com, corbet@lwn.net, vkoul@kernel.org, jdmason@kudzu.us, dave.jiang@intel.com, allenbh@gmail.com, Basavaraj.Natikar@amd.com, Shyam-sundar.S-k@amd.com, kurt.schwemmer@microsemi.com, logang@deltatee.com, jingoohan1@gmail.com, lpieralisi@kernel.org, robh@kernel.org, jbrunet@baylibre.com, fancer.lancer@gmail.com, arnd@arndb.de, pstanner@redhat.com, elfring@users.sourceforge.net Subject: [RFC PATCH v2 27/27] NTB: epf: Add an additional memory window (MW2) barno mapping on Renesas R-Car Date: Sun, 30 Nov 2025 01:04:05 +0900 Message-ID: <20251129160405.2568284-28-den@valinux.co.jp> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20251129160405.2568284-1-den@valinux.co.jp> References: <20251129160405.2568284-1-den@valinux.co.jp> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: TY4PR01CA0105.jpnprd01.prod.outlook.com (2603:1096:405:378::19) To TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:24c::11) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TYWP286MB2697:EE_|OS9P286MB4684:EE_ X-MS-Office365-Filtering-Correlation-Id: 2248c63d-b741-4b4d-53a2-08de2f61047e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|366016|10070799003|1800799024; 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charset="utf-8" To enable remote eDMA mode on NTB transport, one additional memory window is required. Since a single BAR can now be split into multiple memory windows, add MW2 to BAR2 on R-Car. For pci_epf_vntb configfs settings, users who want to use MW2 (e.g. to enable remote eDMA mode for NTB transport as mentioned above) may configure as follows: $ echo 2 > functions/pci_epf_vntb/func1/pci_epf_vntb.0/num_mws $ echo 0xE0000 > functions/pci_epf_vntb/func1/pci_epf_vntb.0/mw1 $ echo 0x20000 > functions/pci_epf_vntb/func1/pci_epf_vntb.0/mw2 $ echo 0xE0000 > functions/pci_epf_vntb/func1/pci_epf_vntb.0/mw2_offset $ echo 2 > functions/pci_epf_vntb/func1/pci_epf_vntb.0/mw1_bar $ echo 2 > functions/pci_epf_vntb/func1/pci_epf_vntb.0/mw2_bar Signed-off-by: Koichiro Den --- drivers/ntb/hw/epf/ntb_hw_epf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ntb/hw/epf/ntb_hw_epf.c b/drivers/ntb/hw/epf/ntb_hw_ep= f.c index 21eb26b2f7cc..19a4c07bbc8f 100644 --- a/drivers/ntb/hw/epf/ntb_hw_epf.c +++ b/drivers/ntb/hw/epf/ntb_hw_epf.c @@ -792,7 +792,7 @@ static const enum pci_barno rcar_barno[NTB_BAR_NUM] =3D= { [BAR_PEER_SPAD] =3D BAR_0, [BAR_DB] =3D BAR_4, [BAR_MW1] =3D BAR_2, - [BAR_MW2] =3D NO_BAR, + [BAR_MW2] =3D BAR_2, [BAR_MW3] =3D NO_BAR, [BAR_MW4] =3D NO_BAR, }; --=20 2.48.1