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Fri, 28 Nov 2025 19:29:53 -0800 (PST) Received: from fedora ([172.59.162.202]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11dcb03cc7dsm26206743c88.5.2025.11.28.19.29.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Nov 2025 19:29:52 -0800 (PST) From: Alex Tran To: jani.nikula@linux.intel.com, joonas.lahtinen@linux.intel.com, rodrigo.vivi@intel.com, tursulin@ursulin.net Cc: airlied@gmail.com, simona@ffwll.ch, ville.syrjala@linux.intel.com, vinay.belgaumkar@intel.com, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Alex Tran Subject: [PATCH v1] drm: i915: gt: intel_rps: handle counter overflow by calculating delta for each register Date: Fri, 28 Nov 2025 19:29:21 -0800 Message-ID: <20251129032921.811332-1-alex.t.tran@gmail.com> X-Mailer: git-send-email 2.51.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The previous implementation calculated the power deltas by adding together the u32 energy counters DMIEC, DDREC, CSIEC into a u64 total and then subtracting from the previous total to obtain the delta. When any of the u32 counters overflowed and wrapped, the total would be less then previous total, causing incorrect delta calculations since u64 subtraction doesn't handle u32 counter wrapping correctly. This implementation tracks each counter individually, allowing their deltas to be calculated separately and then summed. This correctly handles u32 counter wraparound, fixing incorrect power calculations when counters overflow. Signed-off-by: Alex Tran --- drivers/gpu/drm/i915/gt/intel_rps.c | 40 +++++++++++++---------- drivers/gpu/drm/i915/gt/intel_rps_types.h | 6 ++-- 2 files changed, 27 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/= intel_rps.c index 4da94098bd3e..8247a8b16f18 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -324,8 +324,10 @@ __ips_chipset_val(struct intel_ips *ips) struct intel_uncore *uncore =3D rps_to_uncore(container_of(ips, struct intel_rps, ips)); unsigned long now =3D jiffies_to_msecs(jiffies), dt; + u32 dmiec_delta, ddrec_delta, csiec_delta; + u32 dmiec, ddrec, csiec; unsigned long result; - u64 total, delta; + u64 delta; =20 lockdep_assert_held(&mchdev_lock); =20 @@ -339,17 +341,21 @@ __ips_chipset_val(struct intel_ips *ips) if (dt <=3D 10) return ips->chipset_power; =20 - /* FIXME: handle per-counter overflow */ - total =3D intel_uncore_read(uncore, DMIEC); - total +=3D intel_uncore_read(uncore, DDREC); - total +=3D intel_uncore_read(uncore, CSIEC); + dmiec =3D intel_uncore_read(uncore, DMIEC); + ddrec =3D intel_uncore_read(uncore, DDREC); + csiec =3D intel_uncore_read(uncore, CSIEC); =20 - delta =3D total - ips->last_count1; + dmiec_delta =3D dmiec - ips->last_dmiec; + ddrec_delta =3D ddrec - ips->last_ddrec; + csiec_delta =3D csiec - ips->last_csiec; =20 + delta =3D dmiec_delta + ddrec_delta + csiec_delta; result =3D div_u64(div_u64(ips->m * delta, dt) + ips->c, 10); - - ips->last_count1 =3D total; + ips->last_time1 =3D now; + ips->last_dmiec =3D dmiec; + ips->last_ddrec =3D ddrec; + ips->last_csiec =3D csiec; =20 ips->chipset_power =3D result; =20 @@ -396,7 +402,7 @@ static void __gen5_ips_update(struct intel_ips *ips) struct intel_uncore *uncore =3D rps_to_uncore(container_of(ips, struct intel_rps, ips)); u64 now, delta, dt; - u32 count; + u32 gfxec; =20 lockdep_assert_held(&mchdev_lock); =20 @@ -408,10 +414,10 @@ static void __gen5_ips_update(struct intel_ips *ips) if (dt <=3D 10) return; =20 - count =3D intel_uncore_read(uncore, GFXEC); - delta =3D count - ips->last_count2; - - ips->last_count2 =3D count; + gfxec =3D intel_uncore_read(uncore, GFXEC); + delta =3D gfxec - ips->last_gfxec; + + ips->last_gfxec =3D gfxec; ips->last_time2 =3D now; =20 /* More magic constants... */ @@ -607,12 +613,12 @@ static bool gen5_rps_enable(struct intel_rps *rps) =20 __gen5_rps_set(rps, rps->cur_freq); =20 - rps->ips.last_count1 =3D intel_uncore_read(uncore, DMIEC); - rps->ips.last_count1 +=3D intel_uncore_read(uncore, DDREC); - rps->ips.last_count1 +=3D intel_uncore_read(uncore, CSIEC); + rps->ips.last_dmiec =3D intel_uncore_read(uncore, DMIEC); + rps->ips.last_ddrec =3D intel_uncore_read(uncore, DDREC); + rps->ips.last_csiec =3D intel_uncore_read(uncore, CSIEC); rps->ips.last_time1 =3D jiffies_to_msecs(jiffies); =20 - rps->ips.last_count2 =3D intel_uncore_read(uncore, GFXEC); + rps->ips.last_gfxec =3D intel_uncore_read(uncore, GFXEC); rps->ips.last_time2 =3D ktime_get_raw_ns(); =20 ilk_display_rps_enable(display); diff --git a/drivers/gpu/drm/i915/gt/intel_rps_types.h b/drivers/gpu/drm/i9= 15/gt/intel_rps_types.h index ece445109305..e275291787cf 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps_types.h +++ b/drivers/gpu/drm/i915/gt/intel_rps_types.h @@ -13,10 +13,12 @@ #include =20 struct intel_ips { - u64 last_count1; + u32 last_dmiec; + u32 last_ddrec; + u32 last_csiec; unsigned long last_time1; unsigned long chipset_power; - u64 last_count2; + u32 last_gfxec; u64 last_time2; unsigned long gfx_power; u8 corr; --=20 2.51.0