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charset="utf-8" Enable QoS configuration for master ports with predefined priority and urgency forwarding. Signed-off-by: Odelu Kukatla Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/interconnect/qcom/qcs8300.c | 375 ++++++++++++++++++++++++++++ 1 file changed, 375 insertions(+) diff --git a/drivers/interconnect/qcom/qcs8300.c b/drivers/interconnect/qco= m/qcs8300.c index 70a377bbcf29..3f4fe62148d3 100644 --- a/drivers/interconnect/qcom/qcs8300.c +++ b/drivers/interconnect/qcom/qcs8300.c @@ -186,6 +186,13 @@ static struct qcom_icc_node qxm_qup3 =3D { .name =3D "qxm_qup3", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x11000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -194,6 +201,13 @@ static struct qcom_icc_node xm_emac_0 =3D { .name =3D "xm_emac_0", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x12000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -202,6 +216,13 @@ static struct qcom_icc_node xm_sdc1 =3D { .name =3D "xm_sdc1", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x14000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -210,6 +231,13 @@ static struct qcom_icc_node xm_ufs_mem =3D { .name =3D "xm_ufs_mem", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x15000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -218,6 +246,13 @@ static struct qcom_icc_node xm_usb2_2 =3D { .name =3D "xm_usb2_2", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x16000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -226,6 +261,13 @@ static struct qcom_icc_node xm_usb3_0 =3D { .name =3D "xm_usb3_0", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x17000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -234,6 +276,13 @@ static struct qcom_icc_node qhm_qdss_bam =3D { .name =3D "qhm_qdss_bam", .channels =3D 1, .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x14000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; @@ -242,6 +291,13 @@ static struct qcom_icc_node qhm_qup0 =3D { .name =3D "qhm_qup0", .channels =3D 1, .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x17000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; @@ -250,6 +306,13 @@ static struct qcom_icc_node qhm_qup1 =3D { .name =3D "qhm_qup1", .channels =3D 1, .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x12000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; @@ -258,6 +321,13 @@ static struct qcom_icc_node qnm_cnoc_datapath =3D { .name =3D "qnm_cnoc_datapath", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x16000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; @@ -266,6 +336,13 @@ static struct qcom_icc_node qxm_crypto_0 =3D { .name =3D "qxm_crypto_0", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x18000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; @@ -274,6 +351,13 @@ static struct qcom_icc_node qxm_crypto_1 =3D { .name =3D "qxm_crypto_1", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x1a000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; @@ -282,6 +366,13 @@ static struct qcom_icc_node qxm_ipa =3D { .name =3D "qxm_ipa", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x11000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; @@ -290,6 +381,13 @@ static struct qcom_icc_node xm_qdss_etr_0 =3D { .name =3D "xm_qdss_etr_0", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x13000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; @@ -298,6 +396,13 @@ static struct qcom_icc_node xm_qdss_etr_1 =3D { .name =3D "xm_qdss_etr_1", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x19000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; @@ -390,6 +495,13 @@ static struct qcom_icc_node alm_gpu_tcu =3D { .name =3D "alm_gpu_tcu", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xaf000 }, + .prio_fwd_disable =3D 1, + .prio =3D 1, + .urg_fwd =3D 0, + }, .num_links =3D 2, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; @@ -398,6 +510,13 @@ static struct qcom_icc_node alm_pcie_tcu =3D { .name =3D "alm_pcie_tcu", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xb0000 }, + .prio_fwd_disable =3D 1, + .prio =3D 3, + .urg_fwd =3D 0, + }, .num_links =3D 2, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; @@ -406,6 +525,13 @@ static struct qcom_icc_node alm_sys_tcu =3D { .name =3D "alm_sys_tcu", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xb1000 }, + .prio_fwd_disable =3D 1, + .prio =3D 6, + .urg_fwd =3D 0, + }, .num_links =3D 2, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; @@ -423,6 +549,13 @@ static struct qcom_icc_node qnm_cmpnoc0 =3D { .name =3D "qnm_cmpnoc0", .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0xf6000, 0xf7000 }, + .prio_fwd_disable =3D 1, + .prio =3D 0, + .urg_fwd =3D 0, + }, .num_links =3D 2, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; @@ -448,6 +581,13 @@ static struct qcom_icc_node qnm_gpu =3D { .name =3D "qnm_gpu", .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0xf0000, 0xf1000 }, + .prio_fwd_disable =3D 1, + .prio =3D 0, + .urg_fwd =3D 0, + }, .num_links =3D 2, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; @@ -456,6 +596,13 @@ static struct qcom_icc_node qnm_mnoc_hf =3D { .name =3D "qnm_mnoc_hf", .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0xf2000, 0xf3000 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 2, .link_nodes =3D { &qns_llcc, &qns_pcie }, }; @@ -464,6 +611,13 @@ static struct qcom_icc_node qnm_mnoc_sf =3D { .name =3D "qnm_mnoc_sf", .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0xf4000, 0xf5000 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 3, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie }, @@ -473,6 +627,13 @@ static struct qcom_icc_node qnm_pcie =3D { .name =3D "qnm_pcie", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xb3000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 2, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; @@ -481,6 +642,13 @@ static struct qcom_icc_node qnm_snoc_gc =3D { .name =3D "qnm_snoc_gc", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xb4000 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_llcc }, }; @@ -489,6 +657,13 @@ static struct qcom_icc_node qnm_snoc_sf =3D { .name =3D "qnm_snoc_sf", .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xb5000 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 3, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie }, @@ -541,6 +716,13 @@ static struct qcom_icc_node qnm_camnoc_hf =3D { .name =3D "qnm_camnoc_hf", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xa000 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_hf }, }; @@ -549,6 +731,13 @@ static struct qcom_icc_node qnm_camnoc_icp =3D { .name =3D "qnm_camnoc_icp", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x2a000 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_sf }, }; @@ -557,6 +746,13 @@ static struct qcom_icc_node qnm_camnoc_sf =3D { .name =3D "qnm_camnoc_sf", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x2a080 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_sf }, }; @@ -565,6 +761,13 @@ static struct qcom_icc_node qnm_mdp0_0 =3D { .name =3D "qnm_mdp0_0", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xa080 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_hf }, }; @@ -573,6 +776,13 @@ static struct qcom_icc_node qnm_mdp0_1 =3D { .name =3D "qnm_mdp0_1", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xa180 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_hf }, }; @@ -597,6 +807,13 @@ static struct qcom_icc_node qnm_video0 =3D { .name =3D "qnm_video0", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x2a100 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_sf }, }; @@ -605,6 +822,13 @@ static struct qcom_icc_node qnm_video_cvp =3D { .name =3D "qnm_video_cvp", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x2a200 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_sf }, }; @@ -613,6 +837,13 @@ static struct qcom_icc_node qnm_video_v_cpu =3D { .name =3D "qnm_video_v_cpu", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x2a280 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_sf }, }; @@ -637,6 +868,13 @@ static struct qcom_icc_node xm_pcie3_0 =3D { .name =3D "xm_pcie3_0", .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xb000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_pcie_mem_noc }, }; @@ -645,6 +883,13 @@ static struct qcom_icc_node xm_pcie3_1 =3D { .name =3D "xm_pcie3_1", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xc000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_pcie_mem_noc }, }; @@ -653,6 +898,13 @@ static struct qcom_icc_node qhm_gic =3D { .name =3D "qhm_gic", .channels =3D 1, .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x14000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_gemnoc_sf }, }; @@ -677,6 +929,13 @@ static struct qcom_icc_node qnm_lpass_noc =3D { .name =3D "qnm_lpass_noc", .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x12000 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_gemnoc_sf }, }; @@ -693,6 +952,13 @@ static struct qcom_icc_node qxm_pimem =3D { .name =3D "qxm_pimem", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x13000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_gemnoc_gc }, }; @@ -701,6 +967,13 @@ static struct qcom_icc_node xm_gic =3D { .name =3D "xm_gic", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x15000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_gemnoc_gc }, }; @@ -1599,11 +1872,21 @@ static struct qcom_icc_node * const aggre1_noc_node= s[] =3D { [SLAVE_A1NOC_SNOC] =3D &qns_a1noc_snoc, }; =20 +static const struct regmap_config qcs8300_aggre1_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x17080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc qcs8300_aggre1_noc =3D { + .config =3D &qcs8300_aggre1_noc_regmap_config, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, .num_bcms =3D ARRAY_SIZE(aggre1_noc_bcms), + .qos_requires_clocks =3D true, }; =20 static struct qcom_icc_bcm * const aggre2_noc_bcms[] =3D { @@ -1624,11 +1907,21 @@ static struct qcom_icc_node * const aggre2_noc_node= s[] =3D { [SLAVE_A2NOC_SNOC] =3D &qns_a2noc_snoc, }; =20 +static const struct regmap_config qcs8300_aggre2_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x1a080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc qcs8300_aggre2_noc =3D { + .config =3D &qcs8300_aggre2_noc_regmap_config, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, .num_bcms =3D ARRAY_SIZE(aggre2_noc_bcms), + .qos_requires_clocks =3D true, }; =20 static struct qcom_icc_bcm * const clk_virt_bcms[] =3D { @@ -1740,7 +2033,16 @@ static struct qcom_icc_node * const config_noc_nodes= [] =3D { [SLAVE_TCU] =3D &xs_sys_tcu_cfg, }; =20 +static const struct regmap_config qcs8300_config_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x13080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc qcs8300_config_noc =3D { + .config =3D &qcs8300_config_noc_regmap_config, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, @@ -1753,7 +2055,16 @@ static struct qcom_icc_node * const dc_noc_nodes[] = =3D { [SLAVE_GEM_NOC_CFG] =3D &qns_gemnoc, }; =20 +static const struct regmap_config qcs8300_dc_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x5080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc qcs8300_dc_noc =3D { + .config =3D &qcs8300_dc_noc_regmap_config, .nodes =3D dc_noc_nodes, .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), }; @@ -1786,11 +2097,21 @@ static struct qcom_icc_node * const gem_noc_nodes[]= =3D { [SLAVE_SERVICE_GEM_NOC2] =3D &srvc_sys_gemnoc_2, }; =20 +static const struct regmap_config qcs8300_gem_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xf7080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc qcs8300_gem_noc =3D { + .config =3D &qcs8300_gem_noc_regmap_config, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, .num_bcms =3D ARRAY_SIZE(gem_noc_bcms), + .qos_requires_clocks =3D true, }; =20 static struct qcom_icc_bcm * const gpdsp_anoc_bcms[] =3D { @@ -1803,7 +2124,16 @@ static struct qcom_icc_node * const gpdsp_anoc_nodes= [] =3D { [SLAVE_GP_DSP_SAIL_NOC] =3D &qns_gp_dsp_sail_noc, }; =20 +static const struct regmap_config qcs8300_gpdsp_anoc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xd080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc qcs8300_gpdsp_anoc =3D { + .config =3D &qcs8300_gpdsp_anoc_regmap_config, .nodes =3D gpdsp_anoc_nodes, .num_nodes =3D ARRAY_SIZE(gpdsp_anoc_nodes), .bcms =3D gpdsp_anoc_bcms, @@ -1826,7 +2156,16 @@ static struct qcom_icc_node * const lpass_ag_noc_nod= es[] =3D { [SLAVE_SERVICE_LPASS_AG_NOC] =3D &srvc_niu_lpass_agnoc, }; =20 +static const struct regmap_config qcs8300_lpass_ag_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x17200, + .fast_io =3D true, +}; + static const struct qcom_icc_desc qcs8300_lpass_ag_noc =3D { + .config =3D &qcs8300_lpass_ag_noc_regmap_config, .nodes =3D lpass_ag_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_ag_noc_nodes), .bcms =3D lpass_ag_noc_bcms, @@ -1872,7 +2211,16 @@ static struct qcom_icc_node * const mmss_noc_nodes[]= =3D { [SLAVE_SERVICE_MNOC_SF] =3D &srvc_mnoc_sf, }; =20 +static const struct regmap_config qcs8300_mmss_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x40000, + .fast_io =3D true, +}; + static const struct qcom_icc_desc qcs8300_mmss_noc =3D { + .config =3D &qcs8300_mmss_noc_regmap_config, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -1892,7 +2240,16 @@ static struct qcom_icc_node * const nspa_noc_nodes[]= =3D { [SLAVE_SERVICE_NSP_NOC] =3D &service_nsp_noc, }; =20 +static const struct regmap_config qcs8300_nspa_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x16080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc qcs8300_nspa_noc =3D { + .config =3D &qcs8300_nspa_noc_regmap_config, .nodes =3D nspa_noc_nodes, .num_nodes =3D ARRAY_SIZE(nspa_noc_nodes), .bcms =3D nspa_noc_bcms, @@ -1909,7 +2266,16 @@ static struct qcom_icc_node * const pcie_anoc_nodes[= ] =3D { [SLAVE_ANOC_PCIE_GEM_NOC] =3D &qns_pcie_mem_noc, }; =20 +static const struct regmap_config qcs8300_pcie_anoc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xc080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc qcs8300_pcie_anoc =3D { + .config =3D &qcs8300_pcie_anoc_regmap_config, .nodes =3D pcie_anoc_nodes, .num_nodes =3D ARRAY_SIZE(pcie_anoc_nodes), .bcms =3D pcie_anoc_bcms, @@ -1937,7 +2303,16 @@ static struct qcom_icc_node * const system_noc_nodes= [] =3D { [SLAVE_SERVICE_SNOC] =3D &srvc_snoc, }; =20 +static const struct regmap_config qcs8300_system_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x15080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc qcs8300_system_noc =3D { + .config =3D &qcs8300_system_noc_regmap_config, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, --=20 2.17.1