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Fri, 28 Nov 2025 07:01:50 -0800 (PST) Received: from hu-okukatla-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29bceb7cf89sm48930635ad.99.2025.11.28.07.01.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Nov 2025 07:01:49 -0800 (PST) From: Odelu Kukatla To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: Raviteja Laggyshetty , Odelu Kukatla , Dmitry Baryshkov , Bartosz Golaszewski , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mike Tipton Subject: [PATCH 1/3] dt-bindings: interconnect: add clocks property to enable QoS on qcs8300 Date: Fri, 28 Nov 2025 20:31:04 +0530 Message-Id: <20251128150106.13849-2-odelu.kukatla@oss.qualcomm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20251128150106.13849-1-odelu.kukatla@oss.qualcomm.com> References: <20251128150106.13849-1-odelu.kukatla@oss.qualcomm.com> X-Authority-Analysis: v=2.4 cv=TItIilla c=1 sm=1 tr=0 ts=6929b961 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=O0wWR00VUJuU98rPFccA:9 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-GUID: P4GapeXaXerkooMjt8puqwRWF4peFL4s X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTI4MDExMCBTYWx0ZWRfX+ID/zH4oxO/o ruwFl7oJimRFmanGLqgNeWRwAyDI0XfT2F0+MfMN1SV/l/c9fEYO2QJoCuHguVcF5ih3AV+c4Xj qni63q+LS2HX2xLAOBDWtuEyONRWJ3/KKa8O2TOoIHybwtxZU3PwKWkeZhkAo5BMuzVyocW+YxA tzQTsXhqNMH4/llQzof+wVLkaX0/35m9uYH9uLDPRQKbGErwKMVUwRwsfIY1iw+Xa5uwDml4yar korRtH+EmRSDE+aGhvGaTteo6eN5TRgu4AD1E9hm+Pvge4qiSJNcxzCI+m5jF4WXernl5CccVAl ZtxNrOhUm54n3qmnU8Msm7DLXmdiwFBLgIrD/Cp1aBlOOMY761tdHXhR5eCmr2zw7/KzjcIj8sS U5uO6+p53C4vRY0vbjf4/dHE6LsSXg== X-Proofpoint-ORIG-GUID: P4GapeXaXerkooMjt8puqwRWF4peFL4s X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-28_03,2025-11-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 adultscore=0 suspectscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 spamscore=0 malwarescore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511280110 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add 'clocks' property to enable QoS configuration. This property enables the necessary clocks for QoS configuration. QoS configuration is essential for ensuring that latency sensitive components such as CPUs and multimedia engines receive prioritized access to memory and interconnect resources. This helps to manage bandwidth and latency across subsystems, improving system responsiveness and performance in concurrent workloads. Both 'reg' and 'clocks' properties are optional. If either is missing, QoS configuration will be skipped. This behavior is controlled by the 'qos_requires_clocks' flag in the driver, which ensures that QoS configuration is bypassed when required clocks are not defined. Signed-off-by: Odelu Kukatla --- .../interconnect/qcom,qcs8300-rpmh.yaml | 53 ++++++++++++++++--- 1 file changed, 47 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,qcs8300-rp= mh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,qcs8300-rpmh.= yaml index e9f528d6d9a8..594e835d1845 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,qcs8300-rpmh.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,qcs8300-rpmh.yaml @@ -35,6 +35,10 @@ properties: reg: maxItems: 1 =20 + clocks: + minItems: 1 + maxItems: 4 + required: - compatible =20 @@ -45,14 +49,39 @@ allOf: compatible: contains: enum: - - qcom,qcs8300-clk-virt - - qcom,qcs8300-mc-virt + - qcom,qcs8300-aggre1-noc then: properties: - reg: false - else: - required: - - reg + clocks: + items: + - description: aggre UFS PHY AXI clock + - description: aggre QUP PRIM AXI clock + - description: aggre USB2 PRIM AXI clock + - description: aggre USB3 PRIM AXI clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,qcs8300-aggre2-noc + then: + properties: + clocks: + items: + - description: RPMH CC IPA clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,qcs8300-gem-noc + then: + properties: + clocks: + items: + - description: GCC DDRSS GPU AXI clock =20 unevaluatedProperties: false =20 @@ -63,6 +92,7 @@ examples: reg =3D <0x9100000 0xf7080>; #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; + clocks =3D <&gcc_ddrss_gpu_axi_clk>; }; =20 clk_virt: interconnect-0 { @@ -70,3 +100,14 @@ examples: #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; }; + + aggre1_noc: interconnect@16c0000 { + compatible =3D "qcom,qcs8300-aggre1-noc"; + reg =3D <0x016c0000 0x17080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + clocks =3D <&gcc_aggre_ufs_phy_axi_clk>, + <&gcc_aggre_noc_qupv3_axi_clk>, + <&gcc_aggre_usb2_prim_axi_clk>, + <&gcc_aggre_usb3_prim_axi_clk>; + }; --=20 2.17.1