From nobody Mon Dec 1 22:07:45 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3683235360 for ; Fri, 28 Nov 2025 15:01:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764342116; cv=none; b=W0KOo8bjcUrUNj1q8Mg/zAvbcIMswzh2OEnZDCsmZV5MMwkZ/4wgG5V5UZdRS9lxv79sxcyRpOOsh/wAcTtZtThmpjWGJJ6q/WIJiQ/zN5sL1kBLUVsZ3F8CxWvS63QPYeAr3PsCyEaiNWJmclYNsTpC0TPBGkGgglFnXyZIeMk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764342116; c=relaxed/simple; bh=IMYLUe/iqCxNsBq51GotezbgyJ7h4uIKdZod+cjUFxY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=LgwuGdIBU+T09V3L1dM4M5RETRXx1pPqESVE4O3qvRBRYzVU5oQx03t0N8XoPnwqr7AXHu8j69YfdLgj7rZPlcRC23XWxh9sjFh3upBhsT+5G+svBNmK8kNtTXT4NuMb/3UJlCUs+keBVkqKoDog7T62OqKBfi4dk96DZjZkNdQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=YHoP52BX; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=ZUo2jUQx; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="YHoP52BX"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="ZUo2jUQx" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5ASEcVB9400159 for ; Fri, 28 Nov 2025 15:01:53 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:date:from:in-reply-to:message-id:references:subject:to; s= qcppdkim1; bh=nt1h8lj2PaJc9NFcbOupOH+PeDoPeb4OA7HSdoQp9n0=; b=YH oP52BXzMnOvpuZ8XtdN9RRSyQ5wwd0+6jSblJK8OAE1MReqPF1BJaEz0YkypQFQu OlpqjAE8YhE+rWhQUxSHeNLbDmeg0RGhn9dv5jknCTb4UQWcIdFPQCSNi6yroU2+ VakleBu8vs2jDGZJLQevtOg48lieNxvsli5QvIK2UKpHlvx1uGJMzpBJFmlgkk8g jpxJZhGH9u67N7EA1vRh+gpIq9lUXHp69BiGZj9Aqfi+FJLI0ta48YFyTPKhJfyQ lIJD22dkzNffQ2sIfNBsHHqiNH/Hf0hMfTTBYYrtoQXqHYktRGcK4UH0cWQtO/Sn +qi7i3kRVtMCq3vvIoRA== Received: from mail-pl1-f199.google.com (mail-pl1-f199.google.com [209.85.214.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4aqdnn01y6-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 28 Nov 2025 15:01:53 +0000 (GMT) Received: by mail-pl1-f199.google.com with SMTP id d9443c01a7336-295595cd102so30692405ad.3 for ; Fri, 28 Nov 2025 07:01:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1764342112; x=1764946912; darn=vger.kernel.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=nt1h8lj2PaJc9NFcbOupOH+PeDoPeb4OA7HSdoQp9n0=; b=ZUo2jUQxFSzkUvJfP85dFtYQ/Px9mhAFZF/utX4DMz8/+OJauhN2rLl6tbITgq3CVB QGCWJ/Wvhz51GtSQNWhESll+cosPJejh6Vqy6O6260ZMFr1zFdzaO/w4B8ZLJOFEwkOg eO/iZVX+4bJR9w7OvanKCCWKZzbZMEeGtCKlvs8ttdSKoUsXxyZSZ7OIFx4ToPEnulVY /TKWS9tm7ELYXm8MPiSOSuQfhe7vK99G0mh418u+fhpEPt87WutBTDgFKqvBUSWFwXTE rcHm1gf2P69CkXqIDDjXLq/GU3O6MDrD6HFe71ti4fM4uH0qMg6Kpeh1hBiGYHvRxUX7 a0Tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764342112; x=1764946912; h=references:in-reply-to:message-id:date:subject:cc:to:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=nt1h8lj2PaJc9NFcbOupOH+PeDoPeb4OA7HSdoQp9n0=; b=mIf5ZrMowRAUl2t4mOv9oG4IkcL/hLJ6xpjWZU5i7QagIPPIqX6N+Sk32dWudk4biF H/wPf77jdkVbaWyRhT7WbNZRQFrlya/QhhGKL9mYzgeMyMVenKMmxnMRr00r7uafXdRf qPz65K3x7gPuyisgp6APYraekL+2Ahasq4IzPCJjacWgLTfBzTehhux0dt2RflGxTbfA jXfcFvutD9ivFplfa6w5lhr6DRtX8dxndUpDyt7JOS//dGTofyJpzWIddjKFdTmikpRk mGr/T1qy2nOSJKrniLEVfB5qe4gaH7nQY1HcQSVxNVYXDkrrQLwn1Z8/CW44lmNqpHka blEg== X-Forwarded-Encrypted: i=1; AJvYcCWZ9GRZUmUlnyJ+hxWA4UuF1oR7CwyVAC2/IJWuPHzQG3XgTPA3xbNJrTAKfVUZnnmWSfDsGY530m3GXQo=@vger.kernel.org X-Gm-Message-State: AOJu0YysXhDzCN+w1aMV2koaWeWWUHfpaNV7dBJ2xGcbm0sEatNyoHcS kdBavpJd6/G5ihu/qsQvCOtyRrmGiLEdOKvmLQRWvRbk+uyivmcIoyqvTBqMc3TnHfoTtcCWaUj G05pUVgyoEiDhRpFcAwss9BhtT9d8eaI8osdQNXAvV4IOuZRO/9rWWrK/mKNjZl7WX6c= X-Gm-Gg: ASbGncvINM9UxEgrmvAiJ7KotZryP5ETakpghXvWOgp6H+vvdv1NozgQ+qubhWo96GE 60TQQGPrt/1TH66s0mYm4Lsf5sClf0OIyqNMRxbxvFhne7f2DLg3l+bd0nhSWvCWBH1xdLMNePR N+Yh1VqLLnBGlJS7wtHrYTGiy3hC85GNWrRVFQH1sTuJZCUc9UFiJ6VEQo8fxldzn1/lzl7A8vE e2b5BoBf2PjjUQo3jaJVn0HLCojhWLWvTUKF18Yt/6GsuhiY+ESpf/ie40qsM2alZkW/wk5WqR9 kPLFXRh8wze5PEacnlxulnlgjQRb3rjtobKt23iJ5vOMnfGqMryPkmN9AtJC+1B/vakq96t08ck KYiNY6xkMfwnIiDccZYnhZEU0mMS71wszGhs+d6KJDoA= X-Received: by 2002:a17:903:38c5:b0:298:1f9c:e0a2 with SMTP id d9443c01a7336-29b6bf804b1mr326588935ad.54.1764342112230; Fri, 28 Nov 2025 07:01:52 -0800 (PST) X-Google-Smtp-Source: AGHT+IFrtoujn21Vz/n9fhB13s7On3iyOdgYLySngto6d4fsckx3iVqGAF6Nw8puhsnZX3EyxbIbSg== X-Received: by 2002:a17:903:38c5:b0:298:1f9c:e0a2 with SMTP id d9443c01a7336-29b6bf804b1mr326586855ad.54.1764342110020; Fri, 28 Nov 2025 07:01:50 -0800 (PST) Received: from hu-okukatla-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29bceb7cf89sm48930635ad.99.2025.11.28.07.01.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Nov 2025 07:01:49 -0800 (PST) From: Odelu Kukatla To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: Raviteja Laggyshetty , Odelu Kukatla , Dmitry Baryshkov , Bartosz Golaszewski , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mike Tipton Subject: [PATCH 1/3] dt-bindings: interconnect: add clocks property to enable QoS on qcs8300 Date: Fri, 28 Nov 2025 20:31:04 +0530 Message-Id: <20251128150106.13849-2-odelu.kukatla@oss.qualcomm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20251128150106.13849-1-odelu.kukatla@oss.qualcomm.com> References: <20251128150106.13849-1-odelu.kukatla@oss.qualcomm.com> X-Authority-Analysis: v=2.4 cv=TItIilla c=1 sm=1 tr=0 ts=6929b961 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=O0wWR00VUJuU98rPFccA:9 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-GUID: P4GapeXaXerkooMjt8puqwRWF4peFL4s X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTI4MDExMCBTYWx0ZWRfX+ID/zH4oxO/o ruwFl7oJimRFmanGLqgNeWRwAyDI0XfT2F0+MfMN1SV/l/c9fEYO2QJoCuHguVcF5ih3AV+c4Xj qni63q+LS2HX2xLAOBDWtuEyONRWJ3/KKa8O2TOoIHybwtxZU3PwKWkeZhkAo5BMuzVyocW+YxA tzQTsXhqNMH4/llQzof+wVLkaX0/35m9uYH9uLDPRQKbGErwKMVUwRwsfIY1iw+Xa5uwDml4yar korRtH+EmRSDE+aGhvGaTteo6eN5TRgu4AD1E9hm+Pvge4qiSJNcxzCI+m5jF4WXernl5CccVAl ZtxNrOhUm54n3qmnU8Msm7DLXmdiwFBLgIrD/Cp1aBlOOMY761tdHXhR5eCmr2zw7/KzjcIj8sS U5uO6+p53C4vRY0vbjf4/dHE6LsSXg== X-Proofpoint-ORIG-GUID: P4GapeXaXerkooMjt8puqwRWF4peFL4s X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-28_03,2025-11-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 adultscore=0 suspectscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 spamscore=0 malwarescore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511280110 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add 'clocks' property to enable QoS configuration. This property enables the necessary clocks for QoS configuration. QoS configuration is essential for ensuring that latency sensitive components such as CPUs and multimedia engines receive prioritized access to memory and interconnect resources. This helps to manage bandwidth and latency across subsystems, improving system responsiveness and performance in concurrent workloads. Both 'reg' and 'clocks' properties are optional. If either is missing, QoS configuration will be skipped. This behavior is controlled by the 'qos_requires_clocks' flag in the driver, which ensures that QoS configuration is bypassed when required clocks are not defined. Signed-off-by: Odelu Kukatla --- .../interconnect/qcom,qcs8300-rpmh.yaml | 53 ++++++++++++++++--- 1 file changed, 47 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,qcs8300-rp= mh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,qcs8300-rpmh.= yaml index e9f528d6d9a8..594e835d1845 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,qcs8300-rpmh.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,qcs8300-rpmh.yaml @@ -35,6 +35,10 @@ properties: reg: maxItems: 1 =20 + clocks: + minItems: 1 + maxItems: 4 + required: - compatible =20 @@ -45,14 +49,39 @@ allOf: compatible: contains: enum: - - qcom,qcs8300-clk-virt - - qcom,qcs8300-mc-virt + - qcom,qcs8300-aggre1-noc then: properties: - reg: false - else: - required: - - reg + clocks: + items: + - description: aggre UFS PHY AXI clock + - description: aggre QUP PRIM AXI clock + - description: aggre USB2 PRIM AXI clock + - description: aggre USB3 PRIM AXI clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,qcs8300-aggre2-noc + then: + properties: + clocks: + items: + - description: RPMH CC IPA clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,qcs8300-gem-noc + then: + properties: + clocks: + items: + - description: GCC DDRSS GPU AXI clock =20 unevaluatedProperties: false =20 @@ -63,6 +92,7 @@ examples: reg =3D <0x9100000 0xf7080>; #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; + clocks =3D <&gcc_ddrss_gpu_axi_clk>; }; =20 clk_virt: interconnect-0 { @@ -70,3 +100,14 @@ examples: #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; }; + + aggre1_noc: interconnect@16c0000 { + compatible =3D "qcom,qcs8300-aggre1-noc"; + reg =3D <0x016c0000 0x17080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + clocks =3D <&gcc_aggre_ufs_phy_axi_clk>, + <&gcc_aggre_noc_qupv3_axi_clk>, + <&gcc_aggre_usb2_prim_axi_clk>, + <&gcc_aggre_usb3_prim_axi_clk>; + }; --=20 2.17.1 From nobody Mon Dec 1 22:07:45 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E9A2532F748 for ; Fri, 28 Nov 2025 15:01:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764342120; cv=none; b=HznxNoTEDXz/ijQsrI1qYR+Ba96IuordndgjE3+30Ycg5Cf5NmlvBSV8oKpgKwTTogHcm+wMgG3Q242ifCElaJs/DvPtMYU1EgVBn39MZ2PibyIIj9quAzWSHm/mJeySVEB5jonnMwxd8g1Dve0DFTbmGVeermIe66UwZq4dDSM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764342120; c=relaxed/simple; bh=9km1I2pgcMQ/91FFoTJHoH798zlB7m1AcKvuKFLa6oI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=B0enqoWlMLvi7xSLG/I3WhiOSSXLsjDhrvYJZa/zqQXf4fT000IYpRnfsr8r0gw8YsUqL9/qnKKGyZCnlBjzl8CqzEq+NPycrkrlyrxzvxWUynYS38yiSj/qn1gnAfcvWb12plkm3rx8X7OAoseiiMq/9bw7jD4l+lAcWAfmTmQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=LB0GeDGH; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=KZyang7N; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="LB0GeDGH"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="KZyang7N" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5AS8NvDA4191722 for ; Fri, 28 Nov 2025 15:01:56 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:date:from:in-reply-to:message-id:references:subject:to; s= qcppdkim1; bh=5smLdyW+9D5/Ow32GcC7gR3VsO37MrITtebluZTL3kE=; b=LB 0GeDGH2tZVHp6krPk774BZAZIRC3jch0pmDlN379fuauRydIFq5gHKjmMOr0JcpA /f952lmRaCAV5PbPmW0KBEYVhfIM+e2YI/4KtXViO8euEK9rFhrP17AznFDvnVcc ENvYYXz4/w+nCvpLdsdAnbG5+OSKj6DwVkl13nthg+jKBhEstdd83dQl7rS2mPIG YuRvt+1l2cvijR5vrbrAwoSY89Dh+QjAVu1j6z2ulwy5kPz/xecGFwftzU5K5V1n 9G418CHUyqk9yHHm5qNVuKcYOjyMnhBGTrKdGQVukDGl/xnXUxt0hUSaUreyDckk YF88ZOGpWU3cyNR/zJGg== Received: from mail-pl1-f200.google.com (mail-pl1-f200.google.com [209.85.214.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4aq58fhhup-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 28 Nov 2025 15:01:56 +0000 (GMT) Received: by mail-pl1-f200.google.com with SMTP id d9443c01a7336-2956a694b47so25661005ad.1 for ; Fri, 28 Nov 2025 07:01:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1764342116; x=1764946916; darn=vger.kernel.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=5smLdyW+9D5/Ow32GcC7gR3VsO37MrITtebluZTL3kE=; b=KZyang7NQRqPVi+hcJFNIG5N1c1wQD9wa7/k8aibcChSWFZjapWeikhp0o4I3t0hIF x11jd9Q72/OwQocxWT95V67k5ixNUcaeDNUknJHmrzmPHhiY2v/ODOCSsMVFoeQEdzyZ CTv9spqXxqS5b3j2YnwaYFvgN2Qv0BCt7hbTj4eEkPwPvXk983/bBIy0CUbFvwb+jcda DVQT0RLUocv4oH1uPTYgnOhlVaTIGOB2FasDogab/p2Pt/JDhRZXz9gBEOJr7DIS+p8k LDCuvHD0cc0TvmiWxg4rLaZcts7Vz6ykTkd/sHXLIR4MkS0ygs00LD5UMamr8rGAl/Sm z7uQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764342116; x=1764946916; h=references:in-reply-to:message-id:date:subject:cc:to:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=5smLdyW+9D5/Ow32GcC7gR3VsO37MrITtebluZTL3kE=; b=jCL2aA79/JbQh/iq4FQj/Lqba5WEVrXLkWMGXkWeK1btPNOzOTJAYyMxcojZXQ/fe3 3/m11HUzzlNIAVkNRQS3lmqW9JDxSP6pGpKv9FdivE0tGQz1AQK0rFrO3PhTZ5epZiUc RCUa/+xFnvclaSJLPHExU1kdVvvSe7KpxF5ECSo1L40a2+vy1oE/Tghhnrfj7N7zC8ys ltfzmVmFR+prIaBPMF7+JjuknGhWgdAY2QFCCb4gon2QgJDvos9zp9lOC/oRHmwTYVhF dSyS/1xSa0u2XSN5OPCfmFpw5oyfBj8mwsDNmWkt81k6pm7tVcGhnVQfeEqBVnLcR8rI wyxw== X-Forwarded-Encrypted: i=1; AJvYcCUtev4gVmIi+YV9EJRI63mUFXaIAwiyE0K4G+THNH1XZ6WK5Dwns5OJkuwBbP3fbjw8iISjIxmIyPFTbvU=@vger.kernel.org X-Gm-Message-State: AOJu0YzC5c2AbI+kmjyXR9t2vzpUowUdonUCesU792ug3KXlXcfYpxOi KxAnm5q1GSfWk6JcK1CdI4IC9BF+eGQaJn4q66blZtSYM6TUCwlC8rGR472snQA80t9a1IvSbrA kN5Q/MCr3HsEGJKnkwrQVj/eYwXfe3ychEBEAoGThnxA1zPFxzVbZGpyEwxtVExv9xOY= X-Gm-Gg: ASbGncubRe4/q98wOUCOVbJS5UNflOQnXh4AjvOkHCPr+M1zpnAMTYG0A8W3oiWA23k /+mgrsX5JND+SUTVOTyCwSfMVor9TIXF/8d5CnBBz3o8ppJ1tlduprQlSESsWEnhdmK7uk6Nn8q DIvW08xoxnaBapDBeyhyZ6gHkQHy4KuvLRzAiyCoiYsokrbS+/Z9WB9bfUbPNOOIfyDbtUyUFsh m4gE0jsuEjqBnPmaRyAiAyMRGl0iOsQp3EF7IcKnuBbqAa76+lanFBzi5opB71RghsqluBf4O/P tuu/uVyXenqeSLtTOFhq6r6zrGi6Jd/+g12lhbZuAGRbecanxuPoGKosUzEj4+WSNmL+H/UhzCx 5fBoJGRXqtJDmn2Q2ExRPLQllvUEJ X-Received: by 2002:a17:902:f612:b0:295:557e:746d with SMTP id d9443c01a7336-29bab2f5310mr184664905ad.57.1764342115234; Fri, 28 Nov 2025 07:01:55 -0800 (PST) X-Google-Smtp-Source: AGHT+IEg1BvFuOzfuWovnbrO5J2BcJOIyPe/nmdguPIrpfX5VmA/D36JkC3ND0qIeGhX+4fBxzZeOg== X-Received: by 2002:a17:902:f612:b0:295:557e:746d with SMTP id d9443c01a7336-29bab2f5310mr184663885ad.57.1764342114379; Fri, 28 Nov 2025 07:01:54 -0800 (PST) Received: from hu-okukatla-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29bceb7cf89sm48930635ad.99.2025.11.28.07.01.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Nov 2025 07:01:54 -0800 (PST) From: Odelu Kukatla To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: Raviteja Laggyshetty , Odelu Kukatla , Dmitry Baryshkov , Bartosz Golaszewski , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mike Tipton Subject: [PATCH 2/3] interconnect: qcom: qcs8300: enable QoS configuration Date: Fri, 28 Nov 2025 20:31:05 +0530 Message-Id: <20251128150106.13849-3-odelu.kukatla@oss.qualcomm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20251128150106.13849-1-odelu.kukatla@oss.qualcomm.com> References: <20251128150106.13849-1-odelu.kukatla@oss.qualcomm.com> X-Proofpoint-GUID: XmD5vJvu8n1KpRrY5_nP3DeIjaukjsH4 X-Proofpoint-ORIG-GUID: XmD5vJvu8n1KpRrY5_nP3DeIjaukjsH4 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTI4MDExMCBTYWx0ZWRfX5VnucQuTqRJm K7ePxnyzQkbhMcirEkZcRi7XaoV9Vw1oqwIZ9HxQrVgW1n3OMp6n/fVUQX/awW5ce2hY9vO8HDJ 8hzsjJ2Owbe3p9KQnnvJQtpLVZ8bzsNGy6HMyaHq+k4DXiIfSenUFa8WQxKHm8JlGugPVFjSTS9 i79PASY3ww3JcSQ8WkOL2RP3aERP26JTIyMMxGxrtkYkWcz1Y1eFpqqwdgWUTUCh70m9fSInGj2 vCfucgRyd5ZYfRROfK+gjYX53NVnDd3NSAedfHNhduUuyfMPwCh0toGpNq1Plh327DbeTZJWVju X3OEUQxPtRpgMO3f3gS+xIxZZcqFilqNJh1jN8ySYVdy4XJ5D9TL5CyCGem6OaeKupZo9VzvMNC 0WQoaydtcy++ZxrSv+mEV7l/DL7tkQ== X-Authority-Analysis: v=2.4 cv=E6DAZKdl c=1 sm=1 tr=0 ts=6929b964 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=XWZIYzOgiBrVy7gtqr4A:9 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-28_03,2025-11-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 phishscore=0 adultscore=0 lowpriorityscore=0 spamscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511280110 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Enable QoS configuration for master ports with predefined priority and urgency forwarding. Signed-off-by: Odelu Kukatla Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/interconnect/qcom/qcs8300.c | 375 ++++++++++++++++++++++++++++ 1 file changed, 375 insertions(+) diff --git a/drivers/interconnect/qcom/qcs8300.c b/drivers/interconnect/qco= m/qcs8300.c index 70a377bbcf29..3f4fe62148d3 100644 --- a/drivers/interconnect/qcom/qcs8300.c +++ b/drivers/interconnect/qcom/qcs8300.c @@ -186,6 +186,13 @@ static struct qcom_icc_node qxm_qup3 =3D { .name =3D "qxm_qup3", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x11000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -194,6 +201,13 @@ static struct qcom_icc_node xm_emac_0 =3D { .name =3D "xm_emac_0", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x12000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -202,6 +216,13 @@ static struct qcom_icc_node xm_sdc1 =3D { .name =3D "xm_sdc1", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x14000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -210,6 +231,13 @@ static struct qcom_icc_node xm_ufs_mem =3D { .name =3D "xm_ufs_mem", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x15000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -218,6 +246,13 @@ static struct qcom_icc_node xm_usb2_2 =3D { .name =3D "xm_usb2_2", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x16000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -226,6 +261,13 @@ static struct qcom_icc_node xm_usb3_0 =3D { .name =3D "xm_usb3_0", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x17000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -234,6 +276,13 @@ static struct qcom_icc_node qhm_qdss_bam =3D { .name =3D "qhm_qdss_bam", .channels =3D 1, .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x14000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; @@ -242,6 +291,13 @@ static struct qcom_icc_node qhm_qup0 =3D { .name =3D "qhm_qup0", .channels =3D 1, .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x17000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; @@ -250,6 +306,13 @@ static struct qcom_icc_node qhm_qup1 =3D { .name =3D "qhm_qup1", .channels =3D 1, .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x12000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; @@ -258,6 +321,13 @@ static struct qcom_icc_node qnm_cnoc_datapath =3D { .name =3D "qnm_cnoc_datapath", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x16000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; @@ -266,6 +336,13 @@ static struct qcom_icc_node qxm_crypto_0 =3D { .name =3D "qxm_crypto_0", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x18000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; @@ -274,6 +351,13 @@ static struct qcom_icc_node qxm_crypto_1 =3D { .name =3D "qxm_crypto_1", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x1a000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; @@ -282,6 +366,13 @@ static struct qcom_icc_node qxm_ipa =3D { .name =3D "qxm_ipa", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x11000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; @@ -290,6 +381,13 @@ static struct qcom_icc_node xm_qdss_etr_0 =3D { .name =3D "xm_qdss_etr_0", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x13000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; @@ -298,6 +396,13 @@ static struct qcom_icc_node xm_qdss_etr_1 =3D { .name =3D "xm_qdss_etr_1", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x19000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; @@ -390,6 +495,13 @@ static struct qcom_icc_node alm_gpu_tcu =3D { .name =3D "alm_gpu_tcu", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xaf000 }, + .prio_fwd_disable =3D 1, + .prio =3D 1, + .urg_fwd =3D 0, + }, .num_links =3D 2, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; @@ -398,6 +510,13 @@ static struct qcom_icc_node alm_pcie_tcu =3D { .name =3D "alm_pcie_tcu", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xb0000 }, + .prio_fwd_disable =3D 1, + .prio =3D 3, + .urg_fwd =3D 0, + }, .num_links =3D 2, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; @@ -406,6 +525,13 @@ static struct qcom_icc_node alm_sys_tcu =3D { .name =3D "alm_sys_tcu", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xb1000 }, + .prio_fwd_disable =3D 1, + .prio =3D 6, + .urg_fwd =3D 0, + }, .num_links =3D 2, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; @@ -423,6 +549,13 @@ static struct qcom_icc_node qnm_cmpnoc0 =3D { .name =3D "qnm_cmpnoc0", .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0xf6000, 0xf7000 }, + .prio_fwd_disable =3D 1, + .prio =3D 0, + .urg_fwd =3D 0, + }, .num_links =3D 2, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; @@ -448,6 +581,13 @@ static struct qcom_icc_node qnm_gpu =3D { .name =3D "qnm_gpu", .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0xf0000, 0xf1000 }, + .prio_fwd_disable =3D 1, + .prio =3D 0, + .urg_fwd =3D 0, + }, .num_links =3D 2, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; @@ -456,6 +596,13 @@ static struct qcom_icc_node qnm_mnoc_hf =3D { .name =3D "qnm_mnoc_hf", .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0xf2000, 0xf3000 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 2, .link_nodes =3D { &qns_llcc, &qns_pcie }, }; @@ -464,6 +611,13 @@ static struct qcom_icc_node qnm_mnoc_sf =3D { .name =3D "qnm_mnoc_sf", .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0xf4000, 0xf5000 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 3, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie }, @@ -473,6 +627,13 @@ static struct qcom_icc_node qnm_pcie =3D { .name =3D "qnm_pcie", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xb3000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 2, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; @@ -481,6 +642,13 @@ static struct qcom_icc_node qnm_snoc_gc =3D { .name =3D "qnm_snoc_gc", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xb4000 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_llcc }, }; @@ -489,6 +657,13 @@ static struct qcom_icc_node qnm_snoc_sf =3D { .name =3D "qnm_snoc_sf", .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xb5000 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 3, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie }, @@ -541,6 +716,13 @@ static struct qcom_icc_node qnm_camnoc_hf =3D { .name =3D "qnm_camnoc_hf", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xa000 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_hf }, }; @@ -549,6 +731,13 @@ static struct qcom_icc_node qnm_camnoc_icp =3D { .name =3D "qnm_camnoc_icp", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x2a000 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_sf }, }; @@ -557,6 +746,13 @@ static struct qcom_icc_node qnm_camnoc_sf =3D { .name =3D "qnm_camnoc_sf", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x2a080 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_sf }, }; @@ -565,6 +761,13 @@ static struct qcom_icc_node qnm_mdp0_0 =3D { .name =3D "qnm_mdp0_0", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xa080 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_hf }, }; @@ -573,6 +776,13 @@ static struct qcom_icc_node qnm_mdp0_1 =3D { .name =3D "qnm_mdp0_1", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xa180 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_hf }, }; @@ -597,6 +807,13 @@ static struct qcom_icc_node qnm_video0 =3D { .name =3D "qnm_video0", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x2a100 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_sf }, }; @@ -605,6 +822,13 @@ static struct qcom_icc_node qnm_video_cvp =3D { .name =3D "qnm_video_cvp", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x2a200 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_sf }, }; @@ -613,6 +837,13 @@ static struct qcom_icc_node qnm_video_v_cpu =3D { .name =3D "qnm_video_v_cpu", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x2a280 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_sf }, }; @@ -637,6 +868,13 @@ static struct qcom_icc_node xm_pcie3_0 =3D { .name =3D "xm_pcie3_0", .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xb000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_pcie_mem_noc }, }; @@ -645,6 +883,13 @@ static struct qcom_icc_node xm_pcie3_1 =3D { .name =3D "xm_pcie3_1", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xc000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_pcie_mem_noc }, }; @@ -653,6 +898,13 @@ static struct qcom_icc_node qhm_gic =3D { .name =3D "qhm_gic", .channels =3D 1, .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x14000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_gemnoc_sf }, }; @@ -677,6 +929,13 @@ static struct qcom_icc_node qnm_lpass_noc =3D { .name =3D "qnm_lpass_noc", .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x12000 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_gemnoc_sf }, }; @@ -693,6 +952,13 @@ static struct qcom_icc_node qxm_pimem =3D { .name =3D "qxm_pimem", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x13000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_gemnoc_gc }, }; @@ -701,6 +967,13 @@ static struct qcom_icc_node xm_gic =3D { .name =3D "xm_gic", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x15000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_gemnoc_gc }, }; @@ -1599,11 +1872,21 @@ static struct qcom_icc_node * const aggre1_noc_node= s[] =3D { [SLAVE_A1NOC_SNOC] =3D &qns_a1noc_snoc, }; =20 +static const struct regmap_config qcs8300_aggre1_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x17080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc qcs8300_aggre1_noc =3D { + .config =3D &qcs8300_aggre1_noc_regmap_config, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, .num_bcms =3D ARRAY_SIZE(aggre1_noc_bcms), + .qos_requires_clocks =3D true, }; =20 static struct qcom_icc_bcm * const aggre2_noc_bcms[] =3D { @@ -1624,11 +1907,21 @@ static struct qcom_icc_node * const aggre2_noc_node= s[] =3D { [SLAVE_A2NOC_SNOC] =3D &qns_a2noc_snoc, }; =20 +static const struct regmap_config qcs8300_aggre2_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x1a080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc qcs8300_aggre2_noc =3D { + .config =3D &qcs8300_aggre2_noc_regmap_config, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, .num_bcms =3D ARRAY_SIZE(aggre2_noc_bcms), + .qos_requires_clocks =3D true, }; =20 static struct qcom_icc_bcm * const clk_virt_bcms[] =3D { @@ -1740,7 +2033,16 @@ static struct qcom_icc_node * const config_noc_nodes= [] =3D { [SLAVE_TCU] =3D &xs_sys_tcu_cfg, }; =20 +static const struct regmap_config qcs8300_config_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x13080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc qcs8300_config_noc =3D { + .config =3D &qcs8300_config_noc_regmap_config, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, @@ -1753,7 +2055,16 @@ static struct qcom_icc_node * const dc_noc_nodes[] = =3D { [SLAVE_GEM_NOC_CFG] =3D &qns_gemnoc, }; =20 +static const struct regmap_config qcs8300_dc_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x5080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc qcs8300_dc_noc =3D { + .config =3D &qcs8300_dc_noc_regmap_config, .nodes =3D dc_noc_nodes, .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), }; @@ -1786,11 +2097,21 @@ static struct qcom_icc_node * const gem_noc_nodes[]= =3D { [SLAVE_SERVICE_GEM_NOC2] =3D &srvc_sys_gemnoc_2, }; =20 +static const struct regmap_config qcs8300_gem_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xf7080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc qcs8300_gem_noc =3D { + .config =3D &qcs8300_gem_noc_regmap_config, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, .num_bcms =3D ARRAY_SIZE(gem_noc_bcms), + .qos_requires_clocks =3D true, }; =20 static struct qcom_icc_bcm * const gpdsp_anoc_bcms[] =3D { @@ -1803,7 +2124,16 @@ static struct qcom_icc_node * const gpdsp_anoc_nodes= [] =3D { [SLAVE_GP_DSP_SAIL_NOC] =3D &qns_gp_dsp_sail_noc, }; =20 +static const struct regmap_config qcs8300_gpdsp_anoc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xd080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc qcs8300_gpdsp_anoc =3D { + .config =3D &qcs8300_gpdsp_anoc_regmap_config, .nodes =3D gpdsp_anoc_nodes, .num_nodes =3D ARRAY_SIZE(gpdsp_anoc_nodes), .bcms =3D gpdsp_anoc_bcms, @@ -1826,7 +2156,16 @@ static struct qcom_icc_node * const lpass_ag_noc_nod= es[] =3D { [SLAVE_SERVICE_LPASS_AG_NOC] =3D &srvc_niu_lpass_agnoc, }; =20 +static const struct regmap_config qcs8300_lpass_ag_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x17200, + .fast_io =3D true, +}; + static const struct qcom_icc_desc qcs8300_lpass_ag_noc =3D { + .config =3D &qcs8300_lpass_ag_noc_regmap_config, .nodes =3D lpass_ag_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_ag_noc_nodes), .bcms =3D lpass_ag_noc_bcms, @@ -1872,7 +2211,16 @@ static struct qcom_icc_node * const mmss_noc_nodes[]= =3D { [SLAVE_SERVICE_MNOC_SF] =3D &srvc_mnoc_sf, }; =20 +static const struct regmap_config qcs8300_mmss_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x40000, + .fast_io =3D true, +}; + static const struct qcom_icc_desc qcs8300_mmss_noc =3D { + .config =3D &qcs8300_mmss_noc_regmap_config, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -1892,7 +2240,16 @@ static struct qcom_icc_node * const nspa_noc_nodes[]= =3D { [SLAVE_SERVICE_NSP_NOC] =3D &service_nsp_noc, }; =20 +static const struct regmap_config qcs8300_nspa_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x16080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc qcs8300_nspa_noc =3D { + .config =3D &qcs8300_nspa_noc_regmap_config, .nodes =3D nspa_noc_nodes, .num_nodes =3D ARRAY_SIZE(nspa_noc_nodes), .bcms =3D nspa_noc_bcms, @@ -1909,7 +2266,16 @@ static struct qcom_icc_node * const pcie_anoc_nodes[= ] =3D { [SLAVE_ANOC_PCIE_GEM_NOC] =3D &qns_pcie_mem_noc, }; =20 +static const struct regmap_config qcs8300_pcie_anoc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xc080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc qcs8300_pcie_anoc =3D { + .config =3D &qcs8300_pcie_anoc_regmap_config, .nodes =3D pcie_anoc_nodes, .num_nodes =3D ARRAY_SIZE(pcie_anoc_nodes), .bcms =3D pcie_anoc_bcms, @@ -1937,7 +2303,16 @@ static struct qcom_icc_node * const system_noc_nodes= [] =3D { [SLAVE_SERVICE_SNOC] =3D &srvc_snoc, }; =20 +static const struct regmap_config qcs8300_system_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x15080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc qcs8300_system_noc =3D { + .config =3D &qcs8300_system_noc_regmap_config, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, --=20 2.17.1 From nobody Mon Dec 1 22:07:45 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C31632F778 for ; Fri, 28 Nov 2025 15:02:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764342122; cv=none; b=bZuNqudSK4+yp3tzRQBEni3bJDqYLMnW3n5EbbvC72mlWt7Ehzq3GMt0wRhFUvAnxBCkC1bmkjdzsPWPuVsRYDMxoVNjMoyRJ4Ld11Gbf4Sy2fR3afiEbhXBc9AxWXn219n2+zpIJPlGGxOga2FoOJF8DrXx+kL6rBf9Msl791g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764342122; c=relaxed/simple; bh=UU33rsjB6cwkxiQZjs9flKSwaQBjR62L8vGfNNoDXYE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=Wu+06E7rUY7KS6sfXK6pmPNiSArJEKEe48wKcY6W3SraIFynwN2pFqv/rCFlxM0zFGG6+aMeAOGCXh97oRTX91nt2/WYAE8OilCISkkCcjpIHvIHYrnse+lBy6FV0WzrZA88r3BRVeWt/DRKhGYlF3PLYBeU7j49NkMCziRwbkE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=m3P8P2oh; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=VlqqHRj7; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="m3P8P2oh"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="VlqqHRj7" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5ASC2I814006005 for ; Fri, 28 Nov 2025 15:02:00 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:date:from:in-reply-to:message-id:references:subject:to; s= qcppdkim1; bh=poPZ6JaN1QNodsl/vhNAHQ1cQ2m75xykuLF0QgSfxXw=; b=m3 P8P2ohFmef2Ja/2/+q2JtZ17oPf1GLNl6AP+1MiloBWs/7PLA6tOonf3L2Qxb2Q+ dt1ZN5LVqBemcqo8yoDx+gS/H14NdSGrdizQh1I+koTHNnqb5smt93IuhY1bdnyi BxpTWQ+xC7xyAphoxOR7Ht6M3oiPzPa8bAuhJ/AcR0Q+4o/g+/ZjHc6SdaEUstip UQQtl4cDJLnLX4Qw2MjSHdWG2Gg8l2LuyHs9VLpViN6TVuHskGkHxRK6e4UiSJll 32dTdZvI+36savujiuWiOg176qrNiEl2+Jm/XoaGJ74EyyMOrIzWii+yYgd0RN4f 8+QzpG0G/WOQJG0lat6g== Received: from mail-pl1-f200.google.com (mail-pl1-f200.google.com [209.85.214.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4aqbd28euu-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 28 Nov 2025 15:02:00 +0000 (GMT) Received: by mail-pl1-f200.google.com with SMTP id d9443c01a7336-29845b18d1aso35184525ad.1 for ; Fri, 28 Nov 2025 07:02:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1764342120; x=1764946920; darn=vger.kernel.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=poPZ6JaN1QNodsl/vhNAHQ1cQ2m75xykuLF0QgSfxXw=; b=VlqqHRj7PWZjgQySBwoOiEP/nExUmfmAlYqRhBd8LPqYlu0JvnR4aPIDorryC+bmOn o6NlpwsNaGM1zgeq2qRTfEooM7ogwO5s6erjxIBeAoU0UuWAAEjxNBGMXqWrMZQemfRZ t533OMH6eOZl6U65p5yu96AGgfNrdUIOAPTqXYLnd8YRCQs1l39B2IrKN2iM1wr/I43f dH4auKXMXn3kk/YonCjMqfQXyn+jOMOElGFCUnHVtJ4Em4viEk3LJ1NsMcibX9tIsJ4m NwN1N1wtNqNX24pXiE/ZhBRO6GET4uDAUX6ylV7hgWtvlocC4z3XbVmX/xK9+MKf9yax hFtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764342120; x=1764946920; h=references:in-reply-to:message-id:date:subject:cc:to:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=poPZ6JaN1QNodsl/vhNAHQ1cQ2m75xykuLF0QgSfxXw=; b=ZYtu8iVcxzf2+uE4TNz31a1fjUkseQuosqzin4jvgzcH0YUegJdlwdTOscj+c+/kK7 TvhrmQ55zRJVb1lSHtb8t/ZnsY1vuDAeuqwhFNpRXJdjkA/V1R5jTgsy+EcdNWrMJw8o 3xtXzF7L70BDhz+sVwhYxlUSUM3u88n7mz26/w4MX1B+M1U6tGOLQnvMvdu9zotxSsXc L/EMAN0cG270kFaoAS3/CW3kJ0uNPGj6+hHoRbPSZG2Pv6kOoIGcK1aJB4X3X+pkMS9S qH0O0q9GevmAg5kfzPOgwHUKetlcPImFPZ4UR3qEnvioh9XRPgBN5fnd54Va6QPUtQ+L Ve+w== X-Forwarded-Encrypted: i=1; AJvYcCU3gT7MmV5ZzYKqrvHrcD6DcevY0AnXrQUoYAylW2qNtwJj0Ny38tYYeDygPKBX2lLEeuwp4J9FUKobCDk=@vger.kernel.org X-Gm-Message-State: AOJu0YxKoWxcTuF/Q++GvVpm3DLsu5RgnwXtxpJwi/c5hLv+cq/1gtak NkMQfTBlc+sQjxKbMOCpRcrvFjteO6EXstiijRCbxVsOAMeTYQfqrcFMKB1dJqpMuRy1bTA7LFP IpHYGPOlK7lSUWwPL9xA4gPVkw185x6/CLms9lpFubjBiBi4hhot+3ohQdCD28mTnRjql5Kaj+Y 0= X-Gm-Gg: ASbGncvaXTmgXrPVv0m9iVYzDMDYOs6idzdZW57MI77xs7QvW1+BgKxKsdU4dvRW+hz dTSXf+zdgAnQqtm4INvBqnpIACUFWwlqMxYNyvmTpuJGvG5Iz2vlkfut38Z0CaysEgVP3ve+nou gn83fbGTJMV5ZOyMiShrKlXGt+J3WGnOFPiOnoIrXum6+RBxhFK2x8GZXfeQtLwtGWQaxN4MPRR Ae02xLVgvnej3k+gq5NG4FC919vC9QL/LUNMSknUyAC1+QKD+18pkPy0GutvZRlPo9ioJL64TvX 3ktM3/D3nJ1aHXIrAhxhz/CnkPox2h38GlWdhq2UR8yLqdidi+uiXAzM+GuXfAa5R0BmZtnflZg SU0YkjHQJAIPuo4EbhaBEe4+NiPj9dRH49W44LAj7ZyE= X-Received: by 2002:a17:903:2349:b0:296:3f23:b909 with SMTP id d9443c01a7336-29b6c5767d4mr358754235ad.39.1764342119352; Fri, 28 Nov 2025 07:01:59 -0800 (PST) X-Google-Smtp-Source: AGHT+IFW3/L7cLZ+hDAXvD8QfActpsccZMuajQkivaccixnsOCM/x9NoRUUj+OFFkquvpAv6OgjhJg== X-Received: by 2002:a17:903:2349:b0:296:3f23:b909 with SMTP id d9443c01a7336-29b6c5767d4mr358753595ad.39.1764342118720; Fri, 28 Nov 2025 07:01:58 -0800 (PST) Received: from hu-okukatla-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29bceb7cf89sm48930635ad.99.2025.11.28.07.01.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Nov 2025 07:01:58 -0800 (PST) From: Odelu Kukatla To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: Raviteja Laggyshetty , Odelu Kukatla , Dmitry Baryshkov , Bartosz Golaszewski , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mike Tipton Subject: [PATCH 3/3] arm64: dts: qcom: qcs8300: Add clocks for QoS configuration Date: Fri, 28 Nov 2025 20:31:06 +0530 Message-Id: <20251128150106.13849-4-odelu.kukatla@oss.qualcomm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20251128150106.13849-1-odelu.kukatla@oss.qualcomm.com> References: <20251128150106.13849-1-odelu.kukatla@oss.qualcomm.com> X-Authority-Analysis: v=2.4 cv=comWUl4i c=1 sm=1 tr=0 ts=6929b968 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=lpgrqeBui4GLTciQF88A:9 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-ORIG-GUID: ydJ9M8hohrneDScmHlxvOFDrRE4rZszk X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTI4MDExMCBTYWx0ZWRfX4LHrEYTMHJ+z DFgxAInbhGacMTQQBijoZIETn1E+ypHDFnYC5y0v1oIRI2iuMQlg7GIcs8kPKjSPjL+Yp+Ehc/L b1xoeoj/sbx2LQT4zRMo8VHK+JcmkImdUkInFW0opa9ChVdFoNnqsyAWEapi4jCUc4z76XwrUzO AeKJwQLqGgbmvJiuLG0HCK29CTXu1zVPEy3dlSwTX4niKU2gPqQx5suRidaoefXVrOTDgWqrXEu XICLqMm2QuaApu2ngFawOGW9uRMDbVR82lPfN2A07ySG2KT0ad5m1QvrsoHn46XVHt3ndahjFlu PNkCi/Xlcb6nn2B/NZEdopL+LbrqxOHISTuaGiXNqN5BbmFItO3iywsD74EvSTiNWmLZ+RVrbqA cpTB1wpwgyGwuYsMfXlOH9qvzBq05g== X-Proofpoint-GUID: ydJ9M8hohrneDScmHlxvOFDrRE4rZszk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-28_03,2025-11-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 adultscore=0 priorityscore=1501 suspectscore=0 phishscore=0 impostorscore=0 malwarescore=0 spamscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511280110 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add clocks which need to be enabled for configuring QoS on qcs8300 SoC. Signed-off-by: Odelu Kukatla Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/monaco.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qco= m/monaco.dtsi index 816fa2af8a9a..6139511ea525 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -2226,6 +2226,10 @@ reg =3D <0x0 0x016c0000 0x0 0x17080>; #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; + clocks =3D <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_QUPV3_AXI_CLK>, + <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; }; =20 aggre2_noc: interconnect@1700000 { @@ -2233,6 +2237,7 @@ reg =3D <0x0 0x01700000 0x0 0x1a080>; #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; + clocks =3D <&rpmhcc RPMH_IPA_CLK>; }; =20 pcie_anoc: interconnect@1760000 { @@ -4560,6 +4565,7 @@ reg =3D <0x0 0x9100000 0x0 0xf7080>; #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; + clocks =3D <&gcc GCC_DDRSS_GPU_AXI_CLK>; }; =20 llcc: system-cache-controller@9200000 { --=20 2.17.1