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charset="utf-8" Add configurations in devicetree for PCIe0, board related gpios, PMIC regulators, etc for qcs8300-ride board. Reviewed-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 42 +++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dt= s/qcom/qcs8300-ride.dts index 9bcb869dd270..7ab01dc3bbc9 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -317,6 +317,25 @@ &iris { status =3D "okay"; }; =20 +&pcie0 { + pinctrl-0 =3D <&pcie0_default_state>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcieport0 { + reset-gpios =3D <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 0 GPIO_ACTIVE_HIGH>; +}; + +&pcie0_phy { + vdda-phy-supply =3D <&vreg_l6a>; + vdda-pll-supply =3D <&vreg_l5a>; + + status =3D "okay"; +}; + &qupv3_id_0 { status =3D "okay"; }; @@ -377,6 +396,29 @@ ethernet0_mdio: ethernet0-mdio-pins { bias-pull-up; }; }; + + pcie0_default_state: pcie0-default-state { + wake-pins { + pins =3D "gpio0"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + clkreq-pins { + pins =3D "gpio1"; + function =3D "pcie0_clkreq"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-pins { + pins =3D "gpio2"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; }; =20 &uart7 { --=20 2.34.1