From nobody Mon Dec 1 22:37:45 2025 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 406132C21DC; Fri, 28 Nov 2025 09:11:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764321084; cv=none; b=eLfN3dog9FmvjM0GbrTGoGDBiM7HeRbxf9Ik9arnKVkw8JS6EVJsq0TLs9hRKNwS6drGjC1Q+ZdFA07j7yzUG8KH89xAUCu4pZyrtkkW63mrDfWBzt1MKyr18Qv+miPSEooLolQAikWanNJlX2Snok9xs4tBXB/eUGdglxgj1WA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764321084; c=relaxed/simple; bh=TrxiDGAb+CACXfI7SQ8F0AWThOUb/X1YHD+7xxs0u9s=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=QRXtT7PSMAttNxWLyn476FyBxx28/C7sY/qqt/2jgHt5gQV1T5m8jDFEqZ/3pvc5JFM5iuvJcFYtWyMISj0eGXhuJ4X6wBkYg5+cRLn9gLfSZRFU4yfLOLx8dzYV03aG4vUpzg1nAyjJjmbcxKQ8cHk00XcG+0w0KVeaxT2yBU0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com; spf=pass smtp.mailfrom=realtek.com; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b=pJeB7ZHB; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realtek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b="pJeB7ZHB" X-SpamFilter-By: ArmorX SpamTrap 5.80 with qID 5AS98QHa8394709, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=realtek.com; s=dkim; t=1764320906; bh=UIiprcjgq2lecYZK2AZBwF2o0KKwZPjW0iWNG/O03pU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=pJeB7ZHBjQwNzbmY9bU8WT03J03sDyh1ch9laW4sUNMI5Pn+nwKSiVWlGxFQLysIN e/r8UYZfmvztrtMoCBeVRRGiBm6qk57Cr+aoSaxLwM1fkGn1CqFCzkbGjJdRi7KWSh aB4WY5vRtkW8CPsrFKBvSJIizAToYtpulm3hjZSyYsZ0Rb6GvD0gDSZ5d2AetWT20v ngoko0kKoAa3asQGjRN7QymUVyBLwf4QuIQjl7PUjXEuad4L3wsjRUENGXFlyf2hyr 97KtOjQIqvFtmBNDoo2meB7XelDoim6oT7slgGcCBeQJb+K6vAkbUr71b4X3CIgPy2 WvQTlwW+Nr2Ug== Received: from mail.realtek.com (rtkexhmbs03.realtek.com.tw[10.21.1.53]) by rtits2.realtek.com.tw (8.15.2/3.21/5.94) with ESMTPS id 5AS98QHa8394709 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 28 Nov 2025 17:08:26 +0800 Received: from RTKEXHMBS06.realtek.com.tw (10.21.1.56) by RTKEXHMBS03.realtek.com.tw (10.21.1.53) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.27; Fri, 28 Nov 2025 17:08:27 +0800 Received: from RTKEXHMBS04.realtek.com.tw (10.21.1.54) by RTKEXHMBS06.realtek.com.tw (10.21.1.56) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.27; Fri, 28 Nov 2025 17:08:26 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS04.realtek.com.tw (10.21.1.54) with Microsoft SMTP Server id 15.2.1544.27 via Frontend Transport; Fri, 28 Nov 2025 17:08:26 +0800 From: Yu-Chun Lin To: , , , , , CC: , , , , , , Subject: [PATCH v3 2/2 RESEND] arm64: dts: realtek: Add Kent SoC and EVB device trees Date: Fri, 28 Nov 2025 17:08:25 +0800 Message-ID: <20251128090825.27365-3-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251128090825.27365-1-eleanor.lin@realtek.com> References: <20251128090825.27365-1-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add Device Tree hierarchy for Realtek Kent SoC family: - kent.dtsi: base SoC layer - rtd.dtsi: SoC variant layer - rtd-.dtsi: board layer - rtd--.dts: board configuration layer Include RTD1501s Phantom EVB (8GB), RTD1861B Krypton EVB (8GB), and RTD1920s Smallville EVB (4GB). Signed-off-by: Yu-Chun Lin --- arch/arm64/boot/dts/realtek/Makefile | 7 +- arch/arm64/boot/dts/realtek/kent.dtsi | 166 ++++++++++++++++++ arch/arm64/boot/dts/realtek/rtd1501.dtsi | 12 ++ .../boot/dts/realtek/rtd1501s-phantom-8gb.dts | 25 +++ .../boot/dts/realtek/rtd1501s-phantom.dtsi | 118 +++++++++++++ arch/arm64/boot/dts/realtek/rtd1861.dtsi | 12 ++ .../boot/dts/realtek/rtd1861b-krypton-8gb.dts | 25 +++ .../boot/dts/realtek/rtd1861b-krypton.dtsi | 72 ++++++++ arch/arm64/boot/dts/realtek/rtd1920.dtsi | 12 ++ .../dts/realtek/rtd1920s-smallville-4gb.dts | 23 +++ .../boot/dts/realtek/rtd1920s-smallville.dtsi | 128 ++++++++++++++ 11 files changed, 596 insertions(+), 4 deletions(-) create mode 100644 arch/arm64/boot/dts/realtek/kent.dtsi create mode 100644 arch/arm64/boot/dts/realtek/rtd1501.dtsi create mode 100644 arch/arm64/boot/dts/realtek/rtd1501s-phantom-8gb.dts create mode 100644 arch/arm64/boot/dts/realtek/rtd1501s-phantom.dtsi create mode 100644 arch/arm64/boot/dts/realtek/rtd1861.dtsi create mode 100644 arch/arm64/boot/dts/realtek/rtd1861b-krypton-8gb.dts create mode 100644 arch/arm64/boot/dts/realtek/rtd1861b-krypton.dtsi create mode 100644 arch/arm64/boot/dts/realtek/rtd1920.dtsi create mode 100644 arch/arm64/boot/dts/realtek/rtd1920s-smallville-4gb.dts create mode 100644 arch/arm64/boot/dts/realtek/rtd1920s-smallville.dtsi diff --git a/arch/arm64/boot/dts/realtek/Makefile b/arch/arm64/boot/dts/rea= ltek/Makefile index ef8d8fcbaa05..60a37d5a948c 100644 --- a/arch/arm64/boot/dts/realtek/Makefile +++ b/arch/arm64/boot/dts/realtek/Makefile @@ -1,15 +1,14 @@ # SPDX-License-Identifier: GPL-2.0-only =20 dtb-$(CONFIG_ARCH_REALTEK) +=3D rtd1293-ds418j.dtb - dtb-$(CONFIG_ARCH_REALTEK) +=3D rtd1295-mele-v9.dtb dtb-$(CONFIG_ARCH_REALTEK) +=3D rtd1295-probox2-ava.dtb dtb-$(CONFIG_ARCH_REALTEK) +=3D rtd1295-xnano-x5.dtb dtb-$(CONFIG_ARCH_REALTEK) +=3D rtd1295-zidoo-x9s.dtb - dtb-$(CONFIG_ARCH_REALTEK) +=3D rtd1296-ds418.dtb - dtb-$(CONFIG_ARCH_REALTEK) +=3D rtd1395-bpi-m4.dtb dtb-$(CONFIG_ARCH_REALTEK) +=3D rtd1395-lionskin.dtb - +dtb-$(CONFIG_ARCH_REALTEK) +=3D rtd1501s-phantom-8gb.dtb dtb-$(CONFIG_ARCH_REALTEK) +=3D rtd1619-mjolnir.dtb +dtb-$(CONFIG_ARCH_REALTEK) +=3D rtd1861b-krypton-8gb.dtb +dtb-$(CONFIG_ARCH_REALTEK) +=3D rtd1920s-smallville-4gb.dtb diff --git a/arch/arm64/boot/dts/realtek/kent.dtsi b/arch/arm64/boot/dts/re= altek/kent.dtsi new file mode 100644 index 000000000000..ae006ce24420 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/kent.dtsi @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Realtek Kent SoC family + * + * Copyright (c) 2024 Realtek Semiconductor Corp. + */ + +#include +#include + +/ { + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + aliases { + serial0 =3D &uart0; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + , + ; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78"; + reg =3D <0x0>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_0>; + dynamic-power-coefficient =3D <454>; + #cooling-cells =3D <2>; + + l2_0: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-line-size =3D <64>; + cache-sets =3D <256>; + cache-size =3D <0x40000>; + cache-unified; + next-level-cache =3D <&l3>; + }; + }; + + cpu1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78"; + reg =3D <0x100>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_1>; + dynamic-power-coefficient =3D <454>; + #cooling-cells =3D <2>; + + l2_1: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-line-size =3D <64>; + cache-sets =3D <256>; + cache-size =3D <0x40000>; + cache-unified; + next-level-cache =3D <&l3>; + }; + }; + + cpu2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78"; + reg =3D <0x200>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_2>; + dynamic-power-coefficient =3D <454>; + #cooling-cells =3D <2>; + + l2_2: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-line-size =3D <64>; + cache-sets =3D <256>; + cache-size =3D <0x40000>; + cache-unified; + next-level-cache =3D <&l3>; + }; + }; + + cpu3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78"; + reg =3D <0x300>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_3>; + dynamic-power-coefficient =3D <454>; + #cooling-cells =3D <2>; + + l2_3: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-line-size =3D <64>; + cache-sets =3D <256>; + cache-size =3D <0x40000>; + cache-unified; + next-level-cache =3D <&l3>; + }; + }; + + l3: l3-cache { + compatible =3D "cache"; + cache-level =3D <3>; + cache-line-size =3D <64>; + cache-sets =3D <512>; + cache-size =3D <0x200000>; + cache-unified; + }; + }; + + psci: psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + soc@0 { + compatible =3D "simple-bus"; + ranges =3D <0x0 0x0 0x0 0x40000>, /* boot code */ + <0x98000000 0x0 0x98000000 0xef0000>, /* rbus */ + <0xa0000000 0x0 0xa0000000 0x10000000>, /* PCIE */ + <0xff000000 0x0 0xff000000 0x200000>; /* GIC */ + #address-cells =3D <1>; + #size-cells =3D <1>; + + rbus: bus@98000000 { + compatible =3D "simple-bus"; + ranges =3D <0x0 0x98000000 0xef0000>, + <0xa0000000 0xa0000000 0x10000000>; /* PCIE */ + #address-cells =3D <1>; + #size-cells =3D <1>; + + uart0: serial@7800 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x7800 0x100>; + clock-frequency =3D <432000000>; + interrupts =3D ; + reg-io-width =3D <4>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + }; + + gic: interrupt-controller@ff100000 { + compatible =3D "arm,gic-v3"; + reg =3D <0xff100000 0x10000>, + <0xff140000 0x80000>; + interrupt-controller; + interrupts =3D ; + #address-cells =3D <1>; + #interrupt-cells =3D <3>; + #size-cells =3D <1>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd1501.dtsi b/arch/arm64/boot/dts= /realtek/rtd1501.dtsi new file mode 100644 index 000000000000..65f7ede3df73 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1501.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Realtek RTD1501 SoC + * + * Copyright (c) 2024 Realtek Semiconductor Corp. + */ + +#include "kent.dtsi" + +&uart0 { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd1501s-phantom-8gb.dts b/arch/ar= m64/boot/dts/realtek/rtd1501s-phantom-8gb.dts new file mode 100644 index 000000000000..09e544acfd34 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1501s-phantom-8gb.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Realtek RTD1501S Phantom EVB + * + * Copyright (c) 2024 Realtek Semiconductor Corp. + */ + +/dts-v1/; + +#include "rtd1501s-phantom.dtsi" + +/ { + compatible =3D "realtek,phantom", "realtek,rtd1501s"; + model =3D "Realtek Phantom EVB Chromium (8GB)"; + + memory@40000 { + device_type =3D "memory"; + reg =3D <0x0 0x50000 0x0 0x7ffb0000>, + <0x0 0x8a100000 0x0 0xdef0000>, + <0x0 0x98700000 0x0 0x7900000>, + <0x0 0xa0600000 0x0 0x5ea00000>, + <0x1 0x0 0x0 0xa0000000>, + <0x1 0xa0600000 0x0 0x5fa00000>; + }; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd1501s-phantom.dtsi b/arch/arm64= /boot/dts/realtek/rtd1501s-phantom.dtsi new file mode 100644 index 000000000000..bcfb96799671 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1501s-phantom.dtsi @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Realtek RTD1501S Phantom EVB + * + * Copyright (c) 2024 Realtek Semiconductor Corp. + */ + +/dts-v1/; + +#include +#include "rtd1501.dtsi" + +/ { + chosen { + stdout-path =3D "serial0:460800n8"; + }; + + reserved_memory: reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + linux,cma { + compatible =3D "shared-dma-pool"; + alignment =3D <0x0 0x400000>; + alloc-ranges =3D <0x0 0x0 0x0 0x20000000>; + size =3D <0x0 0x2000000>; + reusable; + linux,cma-default; + }; + }; + + cpu_opps: opp-table-cpu { + compatible =3D "operating-points-v2"; + opp-shared; + + opp800: opp-800000000 { + opp-hz =3D /bits/ 64 <800000000>; + opp-microvolt =3D <830000 830000 1100000>; + }; + + opp900: opp-900000000 { + opp-hz =3D /bits/ 64 <900000000>; + opp-microvolt =3D <850000 850000 1100000>; + }; + + opp1000: opp-1000000000 { + opp-hz =3D /bits/ 64 <1000000000>; + opp-microvolt =3D <870000 870000 1100000>; + }; + + opp1100: opp-1100000000 { + opp-hz =3D /bits/ 64 <1100000000>; + opp-microvolt =3D <890000 890000 1100000>; + }; + + opp1200: opp-1200000000 { + opp-hz =3D /bits/ 64 <1200000000>; + opp-microvolt =3D <910000 910000 1100000>; + }; + + opp1300: opp-1300000000 { + opp-hz =3D /bits/ 64 <1300000000>; + opp-microvolt =3D <930000 930000 1100000>; + }; + + opp1400: opp-1400000000 { + opp-hz =3D /bits/ 64 <1400000000>; + opp-microvolt =3D <950000 950000 1100000>; + }; + + opp1500: opp-1500000000 { + opp-hz =3D /bits/ 64 <1500000000>; + opp-microvolt =3D <970000 970000 1100000>; + }; + + opp1600: opp-1600000000 { + opp-hz =3D /bits/ 64 <1600000000>; + opp-microvolt =3D <990000 990000 1100000>; + opp-suspend; + }; + + opp1700: opp-1700000000 { + opp-hz =3D /bits/ 64 <1700000000>; + opp-microvolt =3D <1010000 1010000 1100000>; + }; + + opp1800: opp-1800000000 { + opp-hz =3D /bits/ 64 <1800000000>; + opp-microvolt =3D <1030000 1030000 1100000>; + }; + + opp1900: opp-1900000000 { + opp-hz =3D /bits/ 64 <1900000000>; + opp-microvolt =3D <1050000 1050000 1100000>; + }; + }; +}; + +&cpu0 { + operating-points-v2 =3D <&cpu_opps>; + #cooling-cells =3D <2>; +}; + +&cpu1 { + operating-points-v2 =3D <&cpu_opps>; + #cooling-cells =3D <2>; +}; + +&cpu2 { + operating-points-v2 =3D <&cpu_opps>; + #cooling-cells =3D <2>; +}; + +&cpu3 { + operating-points-v2 =3D <&cpu_opps>; + #cooling-cells =3D <2>; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd1861.dtsi b/arch/arm64/boot/dts= /realtek/rtd1861.dtsi new file mode 100644 index 000000000000..44c3de8f1f48 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1861.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Realtek RTD1861 SoC + * + * Copyright (c) 2024 Realtek Semiconductor Corp. + */ + +#include "kent.dtsi" + +&uart0 { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd1861b-krypton-8gb.dts b/arch/ar= m64/boot/dts/realtek/rtd1861b-krypton-8gb.dts new file mode 100644 index 000000000000..9c23d901c49c --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1861b-krypton-8gb.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Realtek RTD1861B Krypton EVB + * + * Copyright (c) 2024 Realtek Semiconductor Corp. + */ + +/dts-v1/; + +#include "rtd1861b-krypton.dtsi" + +/ { + compatible =3D "realtek,krypton", "realtek,rtd1861b"; + model =3D "Realtek Krypton EVB (8GB)"; + + memory@40000 { + device_type =3D "memory"; + reg =3D <0x0 0x50000 0x0 0x7ffb0000>, + <0x0 0x8a100000 0x0 0xdef0000>, + <0x0 0x98700000 0x0 0x7900000>, + <0x0 0xa0600000 0x0 0x5ea00000>, + <0x1 0x0 0x0 0xa0000000>, + <0x1 0xa0600000 0x0 0x5fa00000>; + }; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd1861b-krypton.dtsi b/arch/arm64= /boot/dts/realtek/rtd1861b-krypton.dtsi new file mode 100644 index 000000000000..b500f4d2c502 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1861b-krypton.dtsi @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Realtek RTD1861B Krypton EVB + * + * Copyright (c) 2024 Realtek Semiconductor Corp. + */ + +/dts-v1/; + +#include "rtd1861.dtsi" + +/ { + chosen { + stdout-path =3D "serial0:460800n8"; + }; + + reserved_memory: reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + linux,cma { + compatible =3D "shared-dma-pool"; + alignment =3D <0x0 0x400000>; + alloc-ranges =3D <0x0 0x0 0x0 0x20000000>; + size =3D <0x0 0x2000000>; + reusable; + linux,cma-default; + }; + }; + + cpu_opps: opp-table-cpu { + compatible =3D "operating-points-v2"; + opp-shared; + + opp1200: opp-1200000000 { + opp-hz =3D /bits/ 64 <1200000000>; + opp-microvolt =3D <900000>; + }; + + opp1600: opp-1600000000 { + opp-hz =3D /bits/ 64 <1600000000>; + opp-microvolt =3D <1000000>; + opp-suspend; + }; + + opp1800: opp-1800000000 { + opp-hz =3D /bits/ 64 <1800000000>; + opp-microvolt =3D <1050000>; + }; + }; +}; + +&cpu0 { + operating-points-v2 =3D <&cpu_opps>; + #cooling-cells =3D <2>; +}; + +&cpu1 { + operating-points-v2 =3D <&cpu_opps>; + #cooling-cells =3D <2>; +}; + +&cpu2 { + operating-points-v2 =3D <&cpu_opps>; + #cooling-cells =3D <2>; +}; + +&cpu3 { + operating-points-v2 =3D <&cpu_opps>; + #cooling-cells =3D <2>; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd1920.dtsi b/arch/arm64/boot/dts= /realtek/rtd1920.dtsi new file mode 100644 index 000000000000..becf546216e9 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1920.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Realtek RTD1920 SoC + * + * Copyright (c) 2024 Realtek Semiconductor Corp. + */ + +#include "kent.dtsi" + +&uart0 { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd1920s-smallville-4gb.dts b/arch= /arm64/boot/dts/realtek/rtd1920s-smallville-4gb.dts new file mode 100644 index 000000000000..9fd6976e0d9b --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1920s-smallville-4gb.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Realtek RTD1920S Smallville EVB + * + * Copyright (c) 2024 Realtek Semiconductor Corp. + */ + +/dts-v1/; + +#include "rtd1920s-smallville.dtsi" + +/ { + compatible =3D "realtek,smallville", "realtek,rtd1920s"; + model =3D "Realtek Smallville EVB (4GB)"; + + memory@40000 { + device_type =3D "memory"; + reg =3D <0x0 0x50000 0x0 0x7ffb0000>, + <0x0 0x8a100000 0x0 0xdef0000>, + <0x0 0x98700000 0x0 0x7900000>, + <0x0 0xa1000000 0x0 0x5e000000>; + }; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd1920s-smallville.dtsi b/arch/ar= m64/boot/dts/realtek/rtd1920s-smallville.dtsi new file mode 100644 index 000000000000..3db8fcea6447 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1920s-smallville.dtsi @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Realtek RTD1920S Smallville EVB + * + * Copyright (c) 2024 Realtek Semiconductor Corp. + */ + +/dts-v1/; + +#include +#include "rtd1920.dtsi" + +/ { + chosen { + stdout-path =3D "serial0:460800n8"; + }; + + reserved_memory: reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + protected_mem: protected-mem@50000 { + reg =3D <0x0 0x50000 0x0 0xbf0000>; + no-map; + }; + + metadata: metadata@c40000 { + reg =3D <0x0 0xc40000 0x0 0x3c4000>; + no-map; + }; + + linux,cma { + compatible =3D "shared-dma-pool"; + alignment =3D <0x0 0x400000>; + alloc-ranges =3D <0x0 0x0 0x0 0x20000000>; + size =3D <0x0 0x2000000>; + reusable; + linux,cma-default; + }; + }; + + cpu_opps: opp-table-cpu { + compatible =3D "operating-points-v2"; + opp-shared; + + opp800: opp-800000000 { + opp-hz =3D /bits/ 64 <800000000>; + opp-microvolt =3D <830000 830000 1100000>; + }; + + opp900: opp-900000000 { + opp-hz =3D /bits/ 64 <900000000>; + opp-microvolt =3D <850000 850000 1100000>; + }; + + opp1000: opp-1000000000 { + opp-hz =3D /bits/ 64 <1000000000>; + opp-microvolt =3D <870000 870000 1100000>; + }; + + opp1100: opp-1100000000 { + opp-hz =3D /bits/ 64 <1100000000>; + opp-microvolt =3D <890000 890000 1100000>; + }; + + opp1200: opp-1200000000 { + opp-hz =3D /bits/ 64 <1200000000>; + opp-microvolt =3D <910000 910000 1100000>; + }; + + opp1300: opp-1300000000 { + opp-hz =3D /bits/ 64 <1300000000>; + opp-microvolt =3D <930000 930000 1100000>; + }; + + opp1400: opp-1400000000 { + opp-hz =3D /bits/ 64 <1400000000>; + opp-microvolt =3D <950000 950000 1100000>; + }; + + opp1500: opp-1500000000 { + opp-hz =3D /bits/ 64 <1500000000>; + opp-microvolt =3D <970000 970000 1100000>; + }; + + opp1600: opp-1600000000 { + opp-hz =3D /bits/ 64 <1600000000>; + opp-microvolt =3D <990000 990000 1100000>; + opp-suspend; + }; + + opp1700: opp-1700000000 { + opp-hz =3D /bits/ 64 <1700000000>; + opp-microvolt =3D <1010000 1010000 1100000>; + }; + + opp1800: opp-1800000000 { + opp-hz =3D /bits/ 64 <1800000000>; + opp-microvolt =3D <1030000 1030000 1100000>; + }; + + opp1900: opp-1900000000 { + opp-hz =3D /bits/ 64 <1900000000>; + opp-microvolt =3D <1050000 1050000 1100000>; + }; + }; +}; + +&cpu0 { + operating-points-v2 =3D <&cpu_opps>; + #cooling-cells =3D <2>; +}; + +&cpu1 { + operating-points-v2 =3D <&cpu_opps>; + #cooling-cells =3D <2>; +}; + +&cpu2 { + operating-points-v2 =3D <&cpu_opps>; + #cooling-cells =3D <2>; +}; + +&cpu3 { + operating-points-v2 =3D <&cpu_opps>; + #cooling-cells =3D <2>; +}; --=20 2.34.1