From nobody Mon Dec 1 22:03:57 2025 Received: from mail-ej1-f50.google.com (mail-ej1-f50.google.com [209.85.218.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B8A92E7F32 for ; Fri, 28 Nov 2025 08:06:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764317209; cv=none; b=suZhl3pfdjOpdkx8gYZgdoWNMW7yS8q8Yvs6pU7//BpmrDbJRhwQg5wUH14pQRCVgkieAeuunCEX+5o8i2/xC0PJnH/M4PnknulYCsP41G6sXc4UO3pbUYEc+r9kyqk64EN0xx7b5j2bibdv8gZ8KoJrY3XQEc326n0h+wwh1r0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764317209; c=relaxed/simple; bh=YoEpu4LLgmyvg6uR8vGP8DRlBZ1dUR7rfJAUV0XOx/E=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HweK+apARED/zHW2/nuyEPP37Gf82xMtgvLthi0dGPXWTNdPtoHWnwwc/wmczlakLvDj3tlxgLSp79bhndsJwNuGSVt2tSfdgI2QBgmTwVa4cOxLBvujFkcUTzCWFhTdEjTmM/zY39Wc7qEgkY0cfn2ASZS81lOoxJ3+n/a5nio= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=FMveoSW7; arc=none smtp.client-ip=209.85.218.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="FMveoSW7" Received: by mail-ej1-f50.google.com with SMTP id a640c23a62f3a-b72bf7e703fso283244266b.2 for ; Fri, 28 Nov 2025 00:06:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1764317206; x=1764922006; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KTeNK2aPj9lGYXJg2ZeiumJ8UHiV1+byQcRUQv3qjGw=; b=FMveoSW7cjuAV27pfw84g+2ES7E37oyhvymDNDULRlG1prq9ZXUHbkUnQS8CDpEypt q/qwG+7/TSEHUuf3O+6RojWcU4UHaDBVkHD1kYp6y/35YZ1oqwR1LHzIfqBLGl4AUvcc fyyG8rAd2MA1/+qyH37wD2GggPXgOWGYwD3ZKqtopwYjMVCS1aVciYck50glxESbdvb6 OqnELxxmV9K1JcKLte1PbdwQ2yERhc0+oZK7RaU+Tfx+ST6hjrtd5JwcmsmAB51UglbX 9uiR9+Mi/2sKRnyQo+208xYMGlPuxRtQWi/u8aSghY0J9p7a5feDKk/DS4O8JeumSOc0 qz0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764317206; x=1764922006; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=KTeNK2aPj9lGYXJg2ZeiumJ8UHiV1+byQcRUQv3qjGw=; b=KPCbSlEGEgA5W4Q/vx9BEAeWo+6b+oFa6eb3veBGJtQ2Um1er6H/scwWeH/8fsvhfX f/CeHh9NE0hfphWaL5VsMI7eQLMMviqsNxW1QCUFJXUUwknpdg4IuL77sBoSKZBEsy3v 2r7s5tNFFcqt9p5VT9BNXr5USq//fxMjWuPRbTp94BTxzh78eBQDQOjtEUdLuXXtcDZ7 G7jr+1KlBl9sxAIiLrC5rX+2VMJ9t4OlPAUdSu4oW6ZsfIgiE3CnCCgAYWZ2l7OsrS2Y XWZ3aPh3szCOFhft8/J6H8BF+VK8kxcGd8zjkqfD+Qq9hSLgQ5/gVIXcCHk+ditwAHO7 FVzQ== X-Forwarded-Encrypted: i=1; AJvYcCWMYf8gJlz1FHujACenhUCWwU5rv40hW+1EeqE7ugEKUV4Xtb8ZgFSjozo8o9i9SGL4+5XxWe5zuyANrec=@vger.kernel.org X-Gm-Message-State: AOJu0Yw3zjJbcTv2FEDsZ+AkY7OL3ZWkhrEZ5VSnq+VZ9A/wkt3Zai+9 npgYW4er/9/6tb5vEXcQY4wwsJdvdUJ7pcftUAvj76wp5pT6nU9VdybX X-Gm-Gg: ASbGnctK7zsz4WNu1yjracg6mLci9eEuCFcmQfQ642FTn1+7fJ1Q5WpjokA3LNnBiCH u2ZqNaQoGAOC+Ch4Kw5G6fUJUzIVt6VNQubb+LKRUZVcN3YMVlF8Ak4tpXl4WQUAI5w7mAZP4UP 0kS+YkfyAt8jOJiIzRz1u+nfY4GGVy0uXipZ6bs6xyAAA9VnNkdDZABWOivtaJX/icylthtUb2H qeYBwodT4Q59rReZ5yjRoFVAh3L31znGlp23pUx20EVAhrCwixWePs0W0v7Ps96juXZrW/rjEQY 7krRzHO/erpsq8rYczR+Rc3thHzEvWn9cLRJ2AdXH75r5FuzTEUjkiovyUVL9iAD+Ry3TYPsGM0 G+PMihFdeeWpspdKZ5e4Xqs8Qp1JCriIbmA4v7dQhWa82QEDy4dae5oOplYS7TcS0JB6U6mr2FE YDenmpJv1KLXTfxMLZswn08+s7CCkTFN6DccN4chAMexthHvpHf4k6BTC4OSLH0JrgvPo= X-Google-Smtp-Source: AGHT+IH7nU8AOL5x+a/3Q11acHdLE+U/kwyWxUsIRL445ue9LpTHuAxa2dyVH8VJRBHo6dsCGgbXtg== X-Received: by 2002:a17:907:1b02:b0:b40:b54d:e687 with SMTP id a640c23a62f3a-b7671acc2d5mr2970835666b.47.1764317205840; Fri, 28 Nov 2025 00:06:45 -0800 (PST) Received: from localhost (dslb-002-205-018-238.002.205.pools.vodafone-ip.de. [2.205.18.238]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b76f5162bb6sm389506866b.12.2025.11.28.00.06.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Nov 2025 00:06:45 -0800 (PST) From: Jonas Gorski To: Florian Fainelli , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Cc: Florian Fainelli , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next v2 5/7] net: dsa: b53: fix BCM5325/65 ARL entry multicast port masks Date: Fri, 28 Nov 2025 09:06:23 +0100 Message-ID: <20251128080625.27181-6-jonas.gorski@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251128080625.27181-1-jonas.gorski@gmail.com> References: <20251128080625.27181-1-jonas.gorski@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" We currently use the mask 0xf for writing and reading b53_entry::port, but this is only correct for unicast ARL entries. Multicast ARL entries use a bitmask, and 0xf is not enough space for ports > 3, which includes the CPU port. So extend the mask accordingly to also fit port 4 (bit 4) and MII (bit 5). According to the datasheet the multicast port mask is [60:48], making it 12 bit wide, but bits 60-55 are reserved anyway, and collide with the priority field at [60:59], so I am not sure if this is valid. Therefore leave it at the actual used range, [53:48]. The ARL search result register differs a bit, and there the mask is only [52:48], so only spanning the user ports. The MII port bit is contained in the Search Result Extension register. So create a separate search result parse function that properly handles this. Fixes: c45655386e53 ("net: dsa: b53: add support for FDB operations on 5325= /5365") Reviewed-by: Florian Fainelli Signed-off-by: Jonas Gorski --- v1 -> v2: * added Review tag from Florian drivers/net/dsa/b53/b53_common.c | 4 +++- drivers/net/dsa/b53/b53_priv.h | 25 +++++++++++++++++++++---- drivers/net/dsa/b53/b53_regs.h | 8 +++++++- 3 files changed, 31 insertions(+), 6 deletions(-) diff --git a/drivers/net/dsa/b53/b53_common.c b/drivers/net/dsa/b53/b53_com= mon.c index 91b0b4de475f..09a64812cd84 100644 --- a/drivers/net/dsa/b53/b53_common.c +++ b/drivers/net/dsa/b53/b53_common.c @@ -2119,10 +2119,12 @@ static void b53_arl_search_read_25(struct b53_devic= e *dev, u8 idx, struct b53_arl_entry *ent) { u64 mac_vid; + u8 ext; =20 + b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSLT_EXT_25, &ext); b53_read64(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSTL_0_MACVID_25, &mac_vid); - b53_arl_to_entry_25(ent, mac_vid); + b53_arl_search_to_entry_25(ent, mac_vid, ext); } =20 static void b53_arl_search_read_89(struct b53_device *dev, u8 idx, diff --git a/drivers/net/dsa/b53/b53_priv.h b/drivers/net/dsa/b53/b53_priv.h index ae2c615c088e..f4afbfcc345e 100644 --- a/drivers/net/dsa/b53/b53_priv.h +++ b/drivers/net/dsa/b53/b53_priv.h @@ -348,8 +348,8 @@ static inline void b53_arl_to_entry_25(struct b53_arl_e= ntry *ent, ent->is_age =3D !!(mac_vid & ARLTBL_AGE_25); ent->is_static =3D !!(mac_vid & ARLTBL_STATIC_25); u64_to_ether_addr(mac_vid, ent->mac); - ent->port =3D (mac_vid >> ARLTBL_DATA_PORT_ID_S_25) & - ARLTBL_DATA_PORT_ID_MASK_25; + ent->port =3D (mac_vid & ARLTBL_DATA_PORT_ID_MASK_25) >> + ARLTBL_DATA_PORT_ID_S_25; if (is_unicast_ether_addr(ent->mac) && ent->port =3D=3D B53_CPU_PORT) ent->port =3D B53_CPU_PORT_25; ent->vid =3D (mac_vid >> ARLTBL_VID_S_65) & ARLTBL_VID_MASK_25; @@ -388,8 +388,8 @@ static inline void b53_arl_from_entry_25(u64 *mac_vid, if (is_unicast_ether_addr(ent->mac) && ent->port =3D=3D B53_CPU_PORT_25) *mac_vid |=3D (u64)B53_CPU_PORT << ARLTBL_DATA_PORT_ID_S_25; else - *mac_vid |=3D (u64)(ent->port & ARLTBL_DATA_PORT_ID_MASK_25) << - ARLTBL_DATA_PORT_ID_S_25; + *mac_vid |=3D ((u64)ent->port << ARLTBL_DATA_PORT_ID_S_25) & + ARLTBL_DATA_PORT_ID_MASK_25; *mac_vid |=3D (u64)(ent->vid & ARLTBL_VID_MASK_25) << ARLTBL_VID_S_65; if (ent->is_valid) @@ -414,6 +414,23 @@ static inline void b53_arl_from_entry_89(u64 *mac_vid,= u32 *fwd_entry, *fwd_entry |=3D ARLTBL_AGE_89; } =20 +static inline void b53_arl_search_to_entry_25(struct b53_arl_entry *ent, + u64 mac_vid, u8 ext) +{ + memset(ent, 0, sizeof(*ent)); + ent->is_valid =3D !!(mac_vid & ARLTBL_VALID_25); + ent->is_age =3D !!(mac_vid & ARLTBL_AGE_25); + ent->is_static =3D !!(mac_vid & ARLTBL_STATIC_25); + u64_to_ether_addr(mac_vid, ent->mac); + ent->vid =3D (mac_vid >> ARLTBL_VID_S_65) & ARLTBL_VID_MASK_25; + ent->port =3D (mac_vid & ARL_SRCH_RSLT_PORT_ID_MASK_25) >> + ARL_SRCH_RSLT_PORT_ID_S_25; + if (is_multicast_ether_addr(ent->mac) && (ext & ARL_SRCH_RSLT_EXT_MC_MII)) + ent->port |=3D BIT(B53_CPU_PORT_25); + else if (!is_multicast_ether_addr(ent->mac) && ent->port =3D=3D B53_CPU_P= ORT) + ent->port =3D B53_CPU_PORT_25; +} + static inline void b53_arl_search_to_entry_63xx(struct b53_arl_entry *ent, u64 mac_vid, u16 fwd_entry) { diff --git a/drivers/net/dsa/b53/b53_regs.h b/drivers/net/dsa/b53/b53_regs.h index 505979102ed5..54b1016eb7eb 100644 --- a/drivers/net/dsa/b53/b53_regs.h +++ b/drivers/net/dsa/b53/b53_regs.h @@ -332,7 +332,7 @@ #define ARLTBL_VID_MASK_25 0xff #define ARLTBL_VID_MASK 0xfff #define ARLTBL_DATA_PORT_ID_S_25 48 -#define ARLTBL_DATA_PORT_ID_MASK_25 0xf +#define ARLTBL_DATA_PORT_ID_MASK_25 GENMASK_ULL(53, 48) #define ARLTBL_VID_S_65 53 #define ARLTBL_AGE_25 BIT_ULL(61) #define ARLTBL_STATIC_25 BIT_ULL(62) @@ -378,6 +378,12 @@ =20 /* Single register search result on 5325/5365 */ #define B53_ARL_SRCH_RSTL_0_MACVID_25 0x24 +#define ARL_SRCH_RSLT_PORT_ID_S_25 48 +#define ARL_SRCH_RSLT_PORT_ID_MASK_25 GENMASK_ULL(52, 48) + +/* BCM5325/5365 Search result extend register (8 bit) */ +#define B53_ARL_SRCH_RSLT_EXT_25 0x2c +#define ARL_SRCH_RSLT_EXT_MC_MII BIT(2) =20 /* ARL Search Data Result (32 bit) */ #define B53_ARL_SRCH_RSTL_0 0x68 --=20 2.43.0