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[177.69.253.233]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11dcaee7076sm12404561c88.4.2025.11.27.16.39.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Nov 2025 16:39:11 -0800 (PST) From: "Rafael V. Volkmer" To: ukleinek@kernel.org Cc: linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, rafael.v.volkmer@gmail.com Subject: [PATCH v7 7/9] pwm: tiehrpwm: unify AQ setup and cover compare-down events Date: Thu, 27 Nov 2025 21:36:32 -0300 Message-ID: <20251128003634.247529-8-rafael.v.volkmer@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251128003634.247529-1-rafael.v.volkmer@gmail.com> References: <20251128003634.247529-1-rafael.v.volkmer@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Refactor ehrpwm_pwm_config() to share the Action-Qualifier setup between channels A and B. Select the channel-specific compare register, AQCTL register and polarity presets (up/down, normal/inverse) once, then derive the AQCTL value from the requested polarity. While doing so, extend the AQCTL mask to include both up- and down-compare fields (CAU/CAD for channel A, CBU/CBD for channel B) and clear all compare actions when the duty cycle exceeds the period, instead of only masking CAU/CBU. For the currently used up-count mode this does not change the effective output waveform, but it keeps the compare-down configuration consistent with the compare-up presets and makes the logic easier to extend (e.g. to up-down modes) in future changes. No functional change intended. Signed-off-by: Rafael V. Volkmer --- drivers/pwm/pwm-tiehrpwm.c | 52 ++++++++++++++++++++------------------ 1 file changed, 27 insertions(+), 25 deletions(-) diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c index e8bcf1ffa770..6a792faa62ce 100644 --- a/drivers/pwm/pwm-tiehrpwm.c +++ b/drivers/pwm/pwm-tiehrpwm.c @@ -242,6 +242,8 @@ static int ehrpwm_pwm_config(struct pwm_chip *chip, str= uct pwm_device *pwm, unsigned int i, cmp_reg; unsigned long long c; u16 aqctl_val, aqctl_mask; + u16 up_normal, up_inverse; + u16 dn_normal, dn_inverse; unsigned int aqctl_reg; =20 if (period_ns > NSEC_PER_SEC) @@ -299,39 +301,39 @@ static int ehrpwm_pwm_config(struct pwm_chip *chip, s= truct pwm_device *pwm, /* Update clock prescaler values */ ehrpwm_modify(pc->mmio_base, TIEHRPWM_TBCTL, TIEHRPWM_TBCTL_PRESCALE_MAS= K, tb_divval); =20 + /* Select channel-specific registers and presets once */ if (pwm->hwpwm =3D=3D 1) { - /* Channel 1 configured with compare B register */ - cmp_reg =3D TIEHRPWM_CMPB; - + /* Channel B uses CMPB and AQCTLB */ + cmp_reg =3D TIEHRPWM_CMPB; aqctl_reg =3D TIEHRPWM_AQCTLB; - aqctl_mask =3D TIEHRPWM_AQCTL_CBU_MASK; - - if (polarity =3D=3D PWM_POLARITY_INVERSED) - aqctl_val =3D TIEHRPWM_AQCTL_CHB_UP_POLINVERSE; - else - aqctl_val =3D TIEHRPWM_AQCTL_CHB_UP_POLNORMAL; - - /* if duty_cycle is big, don't toggle on CBU */ - if (duty_cycles > period_cycles) - aqctl_val &=3D ~TIEHRPWM_AQCTL_CBU_MASK; + aqctl_mask =3D TIEHRPWM_AQCTL_CBU_MASK | TIEHRPWM_AQCTL_CBD_MASK; =20 + up_normal =3D TIEHRPWM_AQCTL_CHB_UP_POLNORMAL; + up_inverse =3D TIEHRPWM_AQCTL_CHB_UP_POLINVERSE; + dn_normal =3D TIEHRPWM_AQCTL_CHB_DN_POLNORMAL; + dn_inverse =3D TIEHRPWM_AQCTL_CHB_DN_POLINVERSE; } else { - /* Channel 0 configured with compare A register */ - cmp_reg =3D TIEHRPWM_CMPA; - + /* Channel A uses CMPA and AQCTLA */ + cmp_reg =3D TIEHRPWM_CMPA; aqctl_reg =3D TIEHRPWM_AQCTLA; - aqctl_mask =3D TIEHRPWM_AQCTL_CAU_MASK; + aqctl_mask =3D TIEHRPWM_AQCTL_CAU_MASK | TIEHRPWM_AQCTL_CAD_MASK; =20 - if (polarity =3D=3D PWM_POLARITY_INVERSED) - aqctl_val =3D TIEHRPWM_AQCTL_CHA_UP_POLINVERSE; - else - aqctl_val =3D TIEHRPWM_AQCTL_CHA_UP_POLNORMAL; - - /* if duty_cycle is big, don't toggle on CAU */ - if (duty_cycles > period_cycles) - aqctl_val &=3D ~TIEHRPWM_AQCTL_CAU_MASK; + up_normal =3D TIEHRPWM_AQCTL_CHA_UP_POLNORMAL; + up_inverse =3D TIEHRPWM_AQCTL_CHA_UP_POLINVERSE; + dn_normal =3D TIEHRPWM_AQCTL_CHA_DN_POLNORMAL; + dn_inverse =3D TIEHRPWM_AQCTL_CHA_DN_POLINVERSE; } =20 + /* Select polarity (up + down) */ + if (polarity =3D=3D PWM_POLARITY_INVERSED) + aqctl_val =3D up_inverse | dn_inverse; + else + aqctl_val =3D up_normal | dn_normal; + + /* If duty is larger than period, don't toggle on compare events */ + if (duty_cycles > period_cycles) + aqctl_val &=3D ~aqctl_mask; + aqctl_mask |=3D TIEHRPWM_AQCTL_PRD_MASK | TIEHRPWM_AQCTL_ZRO_MASK; ehrpwm_modify(pc->mmio_base, aqctl_reg, aqctl_mask, aqctl_val); =20 --=20 2.43.0