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[177.69.253.233]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11dcaee7076sm12404561c88.4.2025.11.27.16.39.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Nov 2025 16:39:09 -0800 (PST) From: "Rafael V. Volkmer" To: ukleinek@kernel.org Cc: linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, rafael.v.volkmer@gmail.com Subject: [PATCH v7 6/9] pwm: tiehrpwm: factor out AQ force codes and polarity presets Date: Thu, 27 Nov 2025 21:36:31 -0300 Message-ID: <20251128003634.247529-7-rafael.v.volkmer@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251128003634.247529-1-rafael.v.volkmer@gmail.com> References: <20251128003634.247529-1-rafael.v.volkmer@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce named constants for the Action-Qualifier force action codes and use them to build the CAU/CAD/CBU/CBD/PRD/ZRO bitfield helpers instead of repeating hard-coded numeric values in each field. While at it, split the channel polarity presets into explicit up-count and down-count variants for both channels. This keeps the resulting AQCTL programming unchanged but makes the configuration easier to read and extend. No functional change intended. Signed-off-by: Rafael V. Volkmer --- drivers/pwm/pwm-tiehrpwm.c | 85 +++++++++++++++++++++++++++++--------- 1 file changed, 65 insertions(+), 20 deletions(-) diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c index 41af1bf74cbb..e8bcf1ffa770 100644 --- a/drivers/pwm/pwm-tiehrpwm.c +++ b/drivers/pwm/pwm-tiehrpwm.c @@ -52,33 +52,78 @@ #define TIEHRPWM_AQSFRC 0x1A #define TIEHRPWM_AQCSFRC 0x1C =20 +/* Action-Qualifier force action codes (per 2-bit field) */ +#define TIEHRPWM_AQCTL_FRCLOW 0x1 +#define TIEHRPWM_AQCTL_FRCHIGH 0x2 +#define TIEHRPWM_AQCTL_FRCTOGGLE 0x3 + +/* Action-Qualifier bitfields for compare/period/zero events */ #define TIEHRPWM_AQCTL_CBU_MASK GENMASK(9, 8) -#define TIEHRPWM_AQCTL_CBU_FRCLOW FIELD_PREP(TIEHRPWM_AQCTL_CBU_MASK, 1) -#define TIEHRPWM_AQCTL_CBU_FRCHIGH FIELD_PREP(TIEHRPWM_AQCTL_CBU_MASK, 2) -#define TIEHRPWM_AQCTL_CBU_FRCTOGGLE FIELD_PREP(TIEHRPWM_AQCTL_CBU_MASK, = 3) +#define TIEHRPWM_AQCTL_CBU_FRCLOW FIELD_PREP(TIEHRPWM_AQCTL_CBU_MASK, \ + TIEHRPWM_AQCTL_FRCLOW) +#define TIEHRPWM_AQCTL_CBU_FRCHIGH FIELD_PREP(TIEHRPWM_AQCTL_CBU_MASK, \ + TIEHRPWM_AQCTL_FRCHIGH) +#define TIEHRPWM_AQCTL_CBU_FRCTOGGLE FIELD_PREP(TIEHRPWM_AQCTL_CBU_MASK, \ + TIEHRPWM_AQCTL_FRCTOGGLE) + +#define TIEHRPWM_AQCTL_CBD_MASK GENMASK(11, 10) +#define TIEHRPWM_AQCTL_CBD_FRCLOW FIELD_PREP(TIEHRPWM_AQCTL_CBD_MASK, \ + TIEHRPWM_AQCTL_FRCLOW) +#define TIEHRPWM_AQCTL_CBD_FRCHIGH FIELD_PREP(TIEHRPWM_AQCTL_CBD_MASK, \ + TIEHRPWM_AQCTL_FRCHIGH) +#define TIEHRPWM_AQCTL_CBD_FRCTOGGLE FIELD_PREP(TIEHRPWM_AQCTL_CBD_MASK, \ + TIEHRPWM_AQCTL_FRCTOGGLE) =20 #define TIEHRPWM_AQCTL_CAU_MASK GENMASK(5, 4) -#define TIEHRPWM_AQCTL_CAU_FRCLOW FIELD_PREP(TIEHRPWM_AQCTL_CAU_MASK, 1) -#define TIEHRPWM_AQCTL_CAU_FRCHIGH FIELD_PREP(TIEHRPWM_AQCTL_CAU_MASK, 2) -#define TIEHRPWM_AQCTL_CAU_FRCTOGGLE FIELD_PREP(TIEHRPWM_AQCTL_CAU_MASK, = 3) +#define TIEHRPWM_AQCTL_CAU_FRCLOW FIELD_PREP(TIEHRPWM_AQCTL_CAU_MASK, \ + TIEHRPWM_AQCTL_FRCLOW) +#define TIEHRPWM_AQCTL_CAU_FRCHIGH FIELD_PREP(TIEHRPWM_AQCTL_CAU_MASK, \ + TIEHRPWM_AQCTL_FRCHIGH) +#define TIEHRPWM_AQCTL_CAU_FRCTOGGLE FIELD_PREP(TIEHRPWM_AQCTL_CAU_MASK, \ + TIEHRPWM_AQCTL_FRCTOGGLE) + +#define TIEHRPWM_AQCTL_CAD_MASK GENMASK(7, 6) +#define TIEHRPWM_AQCTL_CAD_FRCLOW FIELD_PREP(TIEHRPWM_AQCTL_CAD_MASK, \ + TIEHRPWM_AQCTL_FRCLOW) +#define TIEHRPWM_AQCTL_CAD_FRCHIGH FIELD_PREP(TIEHRPWM_AQCTL_CAD_MASK, \ + TIEHRPWM_AQCTL_FRCHIGH) +#define TIEHRPWM_AQCTL_CAD_FRCTOGGLE FIELD_PREP(TIEHRPWM_AQCTL_CAD_MASK, \ + TIEHRPWM_AQCTL_FRCTOGGLE) =20 #define TIEHRPWM_AQCTL_PRD_MASK GENMASK(3, 2) -#define TIEHRPWM_AQCTL_PRD_FRCLOW FIELD_PREP(TIEHRPWM_AQCTL_PRD_MASK, 1) -#define TIEHRPWM_AQCTL_PRD_FRCHIGH FIELD_PREP(TIEHRPWM_AQCTL_PRD_MASK, 2) -#define TIEHRPWM_AQCTL_PRD_FRCTOGGLE FIELD_PREP(TIEHRPWM_AQCTL_PRD_MASK, = 3) +#define TIEHRPWM_AQCTL_PRD_FRCLOW FIELD_PREP(TIEHRPWM_AQCTL_PRD_MASK, \ + TIEHRPWM_AQCTL_FRCLOW) +#define TIEHRPWM_AQCTL_PRD_FRCHIGH FIELD_PREP(TIEHRPWM_AQCTL_PRD_MASK, \ + TIEHRPWM_AQCTL_FRCHIGH) +#define TIEHRPWM_AQCTL_PRD_FRCTOGGLE FIELD_PREP(TIEHRPWM_AQCTL_PRD_MASK, \ + TIEHRPWM_AQCTL_FRCTOGGLE) =20 #define TIEHRPWM_AQCTL_ZRO_MASK GENMASK(1, 0) -#define TIEHRPWM_AQCTL_ZRO_FRCLOW FIELD_PREP(TIEHRPWM_AQCTL_ZRO_MASK, 1) -#define TIEHRPWM_AQCTL_ZRO_FRCHIGH FIELD_PREP(TIEHRPWM_AQCTL_ZRO_MASK, 2) -#define TIEHRPWM_AQCTL_ZRO_FRCTOGGLE FIELD_PREP(TIEHRPWM_AQCTL_ZRO_MASK, = 3) +#define TIEHRPWM_AQCTL_ZRO_FRCLOW FIELD_PREP(TIEHRPWM_AQCTL_ZRO_MASK, \ + TIEHRPWM_AQCTL_FRCLOW) +#define TIEHRPWM_AQCTL_ZRO_FRCHIGH FIELD_PREP(TIEHRPWM_AQCTL_ZRO_MASK, \ + TIEHRPWM_AQCTL_FRCHIGH) +#define TIEHRPWM_AQCTL_ZRO_FRCTOGGLE FIELD_PREP(TIEHRPWM_AQCTL_ZRO_MASK, \ + TIEHRPWM_AQCTL_FRCTOGGLE) + +/* Action-Qualifier polarity presets for up-count mode */ +#define TIEHRPWM_AQCTL_CHA_UP_POLNORMAL (TIEHRPWM_AQCTL_CAU_FRCLOW | \ + TIEHRPWM_AQCTL_ZRO_FRCHIGH) +#define TIEHRPWM_AQCTL_CHA_UP_POLINVERSE (TIEHRPWM_AQCTL_CAU_FRCHIGH | \ + TIEHRPWM_AQCTL_ZRO_FRCLOW) +#define TIEHRPWM_AQCTL_CHB_UP_POLNORMAL (TIEHRPWM_AQCTL_CBU_FRCLOW | \ + TIEHRPWM_AQCTL_ZRO_FRCHIGH) +#define TIEHRPWM_AQCTL_CHB_UP_POLINVERSE (TIEHRPWM_AQCTL_CBU_FRCHIGH | \ + TIEHRPWM_AQCTL_ZRO_FRCLOW) =20 -#define TIEHRPWM_AQCTL_CHANA_POLNORMAL (TIEHRPWM_AQCTL_CAU_FRCLOW | \ +/* Action-Qualifier polarity presets for down-count mode */ +#define TIEHRPWM_AQCTL_CHA_DN_POLNORMAL (TIEHRPWM_AQCTL_CAU_FRCLOW | \ TIEHRPWM_AQCTL_ZRO_FRCHIGH) -#define TIEHRPWM_AQCTL_CHANA_POLINVERSED (TIEHRPWM_AQCTL_CAU_FRCHIGH | \ +#define TIEHRPWM_AQCTL_CHA_DN_POLINVERSE (TIEHRPWM_AQCTL_CAU_FRCHIGH | \ TIEHRPWM_AQCTL_ZRO_FRCLOW) -#define TIEHRPWM_AQCTL_CHANB_POLNORMAL (TIEHRPWM_AQCTL_CBU_FRCLOW | \ +#define TIEHRPWM_AQCTL_CHB_DN_POLNORMAL (TIEHRPWM_AQCTL_CBU_FRCLOW | \ TIEHRPWM_AQCTL_ZRO_FRCHIGH) -#define TIEHRPWM_AQCTL_CHANB_POLINVERSED (TIEHRPWM_AQCTL_CBU_FRCHIGH | \ +#define TIEHRPWM_AQCTL_CHB_DN_POLINVERSE (TIEHRPWM_AQCTL_CBU_FRCHIGH | \ TIEHRPWM_AQCTL_ZRO_FRCLOW) =20 #define TIEHRPWM_AQSFRC_RLDCSF_MASK GENMASK(7, 6) @@ -262,9 +307,9 @@ static int ehrpwm_pwm_config(struct pwm_chip *chip, str= uct pwm_device *pwm, aqctl_mask =3D TIEHRPWM_AQCTL_CBU_MASK; =20 if (polarity =3D=3D PWM_POLARITY_INVERSED) - aqctl_val =3D TIEHRPWM_AQCTL_CHANB_POLINVERSED; + aqctl_val =3D TIEHRPWM_AQCTL_CHB_UP_POLINVERSE; else - aqctl_val =3D TIEHRPWM_AQCTL_CHANB_POLNORMAL; + aqctl_val =3D TIEHRPWM_AQCTL_CHB_UP_POLNORMAL; =20 /* if duty_cycle is big, don't toggle on CBU */ if (duty_cycles > period_cycles) @@ -278,9 +323,9 @@ static int ehrpwm_pwm_config(struct pwm_chip *chip, str= uct pwm_device *pwm, aqctl_mask =3D TIEHRPWM_AQCTL_CAU_MASK; =20 if (polarity =3D=3D PWM_POLARITY_INVERSED) - aqctl_val =3D TIEHRPWM_AQCTL_CHANA_POLINVERSED; + aqctl_val =3D TIEHRPWM_AQCTL_CHA_UP_POLINVERSE; else - aqctl_val =3D TIEHRPWM_AQCTL_CHANA_POLNORMAL; + aqctl_val =3D TIEHRPWM_AQCTL_CHA_UP_POLNORMAL; =20 /* if duty_cycle is big, don't toggle on CAU */ if (duty_cycles > period_cycles) --=20 2.43.0