From nobody Mon Dec 1 22:36:50 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 27F7930B525; Fri, 28 Nov 2025 10:29:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764325763; cv=none; b=EZdjLPtvTBCzr24d6uks1u6xas9FiqaXRtClecDuZQfT8aKQnU9LDJSaswvWaMHcpRkbBujRZFntPyNohlI+P0vj+Zlmof30QOr4Cw61jr3wGlfQNPsH0ib1AuyADzOHFj1W0c+mfqIs2onOC15OGkIc+DWrCsNXePSM/0/0XQM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764325763; c=relaxed/simple; bh=fNS3C2NaCK+go2nQNBlkD9EyrNNHIb0CZcl2LNOQBmE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=iRh98acHGzMCOeqCHb4A30mpdpFjHp96ccf65E1oF0kaAGzHdhWM7H56NI22q+0GXrY7o91H7F+x1Dz1spr6OZc6bMG4DuV8oap/vEdtyjApt+7zNFUl0PcrMSLSe2YVFaWgVvk7/IenJxJhEqcPWhsFZR+HGM4iuhv2lP3w32c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qU845OFh; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qU845OFh" Received: by smtp.kernel.org (Postfix) with ESMTPS id BDCD9C113D0; Fri, 28 Nov 2025 10:29:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1764325762; bh=fNS3C2NaCK+go2nQNBlkD9EyrNNHIb0CZcl2LNOQBmE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=qU845OFhU3cciT1imeWuTMro85tXusIJt99AroBlTX9t+aY8oZwFPjd4KhPNki2mi gK5GyKlndlusCuuiAqnaaQahXFM6I16gAWHOaCMORh1VJ0Vdli6WOo66C/KlZBrRPN 4x/+oieXIooU174yYf8PhFevu9NVbs1arlck6sgsyyW7HB0WwedreqFH2qfmTO4NyF zDymUL0G9Og8hd89PsEyZkkDLVroKnvjU7POud+8el6a6PvDYUOmCTM/rsu2gJX64s k9Nm5ZJmRWfQvaku8McARECvY/QLX3P+pweAuDyazDxpGgTTxPqMbyywNEBjfVYu+o ksKwowwfTPqHg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0784D116EA; Fri, 28 Nov 2025 10:29:22 +0000 (UTC) From: George Moussalem via B4 Relay Date: Fri, 28 Nov 2025 14:29:13 +0400 Subject: [PATCH v19 1/6] dt-bindings: pwm: add IPQ6018 binding Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251128-ipq-pwm-v19-1-13bc704cc6a5@outlook.com> References: <20251128-ipq-pwm-v19-0-13bc704cc6a5@outlook.com> In-Reply-To: <20251128-ipq-pwm-v19-0-13bc704cc6a5@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Baruch Siach , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem , Devi Priya , Baruch Siach , Bjorn Andersson , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764325760; l=2042; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=8ayVJ9z0kZoRdShrug1dJ1pjUonk4k9SO1yJzG93fMg=; b=o0lsJw1oX/jEPu9xLh+Ovt+AbJGXh3X8na0H8Ko0Vcl7PFsYQQEOP9HhJAp8Y5XyBFBcroa6x AHFNonYE7aVArYgsi5KqkDnui4xwpKQpD5RwWJ3JFA96K5IALoApziu X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: Devi Priya DT binding for the PWM block in Qualcomm IPQ6018 SoC. Reviewed-by: Bjorn Andersson Reviewed-by: Krzysztof Kozlowski Co-developed-by: Baruch Siach Signed-off-by: Baruch Siach Signed-off-by: Devi Priya Signed-off-by: George Moussalem --- .../devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml | 51 ++++++++++++++++++= ++++ 1 file changed, 51 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml b/= Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml new file mode 100644 index 0000000000000000000000000000000000000000..f9f1f652e7527bc8fb3d5fad51b= 0057ea53b3766 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/qcom,ipq6018-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IPQ6018 PWM controller + +maintainers: + - George Moussalem + +properties: + compatible: + oneOf: + - items: + - enum: + - qcom,ipq5018-pwm + - qcom,ipq5332-pwm + - qcom,ipq9574-pwm + - const: qcom,ipq6018-pwm + - const: qcom,ipq6018-pwm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#pwm-cells": + const: 3 + +required: + - compatible + - reg + - clocks + - "#pwm-cells" + +additionalProperties: false + +examples: + - | + #include + + pwm: pwm@1941010 { + compatible =3D "qcom,ipq6018-pwm"; + reg =3D <0x01941010 0x20>; + clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates =3D <100000000>; + #pwm-cells =3D <3>; + }; --=20 2.52.0 From nobody Mon Dec 1 22:36:50 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32A6330BBB6; Fri, 28 Nov 2025 10:29:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764325763; cv=none; b=Tzl3GCZjE2m+aCNqXwS9YlwXBMRVfjpboNdMxhrMXPeoUopSQ3Ry4MRINf+lE8xzVojk5g0TORcLLp9hItA5+h0mJllDCBqApTVtREAgNflz7+IVWcDqoMyZ5AeAKzFZJZeHWfz77C9LrGkjapS93WkVz2tntemVjd160qx/TIA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764325763; c=relaxed/simple; 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Fri, 28 Nov 2025 10:29:22 +0000 (UTC) From: George Moussalem via B4 Relay Date: Fri, 28 Nov 2025 14:29:14 +0400 Subject: [PATCH v19 2/6] pwm: driver for qualcomm ipq6018 pwm block Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251128-ipq-pwm-v19-2-13bc704cc6a5@outlook.com> References: <20251128-ipq-pwm-v19-0-13bc704cc6a5@outlook.com> In-Reply-To: <20251128-ipq-pwm-v19-0-13bc704cc6a5@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Baruch Siach , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem , Devi Priya , Baruch Siach X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764325760; l=12302; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=ECLgbGQXvQqaCHleNN2KaOI3IfiJYGfU1o7zDHbZOZo=; b=vPkUe390XfPgnR9A+4cm/jNIETdu3JSzsxMjDjX/DTB7RqMnFGjoy8Nh/xGoBmr00hGJQY3dW bPY4a3duJVOAtYeG1EbsRAywjXTrIxNLun6ElJfCqutCXvpOyMkvWn0 X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: Devi Priya Driver for the PWM block in Qualcomm IPQ6018 line of SoCs. Based on driver from downstream Codeaurora kernel tree. Removed support for older (V1) variants because I have no access to that hardware. Tested on IPQ5018 and IPQ6010 based hardware. Co-developed-by: Baruch Siach Signed-off-by: Baruch Siach Signed-off-by: Devi Priya Reviewed-by: Bjorn Andersson Signed-off-by: George Moussalem --- v18: Added hardware notes and limitations based on own findings as requested. NOTE: there's no publically available datasheet though. Expanded comment on REG1_UPDATE to indicate that when this bit is set, values for div and pre-div take effect. The hardware automatically unsets it when the change is completed. Added newline between MACRO definition and next comment In config_div_and_duty, used mul_u64_u64_div_u64 to avoid overflow Removed unncessary restriction of pwm_div to MAX_DIV - 1 after testing Constrain pre_div to MAX_DIV is pre_div calculated is > MAX_DIV Use of mul_u64_u64_div_u64 in .apply Skip calculation of period and duty cycle when PWM_ENABLE REG is unset Set duty cycle to period value when calculated duty cycle > period to return a valid config Removed .npwm as it's taken care of in devm_pwmchip_alloc Added call to devm_clk_rate_exclusive_get to lock the clock rate Start all kernel messages with a capital letter and end with \n. v17: Removed unnecessary code comments v16: Simplified code to calculate divs and duty cycle as per Uwe's comments Removed unused pwm_chip struct from ipq_pwm_chip struct Removed unnecessary cast as per Uwe's comment Replaced devm_clk_get & clk_prepare_enable by devm_clk_get_enabled Replaced pwmchip_add by devm_pwmchip_add and removed .remove function Removed .owner from driver struct v15: No change v14: Picked up the R-b tag v13: Updated the file name to match the compatible Sorted the properties and updated the order in the required field Dropped the syscon node from examples v12: Picked up the R-b tag v11: No change v10: No change v9: Add 'ranges' property to example (Rob) Drop label in example (Rob) v8: Add size cell to 'reg' (Rob) v7: Use 'reg' instead of 'offset' (Rob) Drop 'clock-names' and 'assigned-clock*' (Bjorn) Use single cell address/size in example node (Bjorn) Move '#pwm-cells' lower in example node (Bjorn) List 'reg' as required v6: Device node is child of TCSR; remove phandle (Rob Herring) Add assigned-clocks/assigned-clock-rates (Uwe Kleine-K=C3=B6nig) v5: Use qcom,pwm-regs for phandle instead of direct regs (Bjorn Andersson, Kathiravan T) v4: Update the binding example node as well (Rob Herring's bot) v3: s/qcom,pwm-ipq6018/qcom,ipq6018-pwm/ (Rob Herring) v2: Make #pwm-cells const (Rob Herring) --- drivers/pwm/Kconfig | 12 +++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-ipq.c | 239 ++++++++++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 252 insertions(+) diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index bf2d101f67a1e0ae12a58b5630abd5cfd77ccc99..6393f4e91697ae471b1aba72e7e= f3f94c5e18383 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -347,6 +347,18 @@ config PWM_INTEL_LGM To compile this driver as a module, choose M here: the module will be called pwm-intel-lgm. =20 +config PWM_IPQ + tristate "IPQ PWM support" + depends on ARCH_QCOM || COMPILE_TEST + depends on HAVE_CLK && HAS_IOMEM + help + Generic PWM framework driver for IPQ PWM block which supports + 4 pwm channels. Each of the these channels can be configured + independent of each other. + + To compile this driver as a module, choose M here: the module + will be called pwm-ipq. + config PWM_IQS620A tristate "Azoteq IQS620A PWM support" depends on MFD_IQS62X || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 0dc0d2b69025dbd27013285cd335d3cb1ca2ab3f..5630a521a7cffeb83ff8c8960e1= 5eb23ddb1c9f8 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_PWM_IMX1) +=3D pwm-imx1.o obj-$(CONFIG_PWM_IMX27) +=3D pwm-imx27.o obj-$(CONFIG_PWM_IMX_TPM) +=3D pwm-imx-tpm.o obj-$(CONFIG_PWM_INTEL_LGM) +=3D pwm-intel-lgm.o +obj-$(CONFIG_PWM_IPQ) +=3D pwm-ipq.o obj-$(CONFIG_PWM_IQS620A) +=3D pwm-iqs620a.o obj-$(CONFIG_PWM_JZ4740) +=3D pwm-jz4740.o obj-$(CONFIG_PWM_KEEMBAY) +=3D pwm-keembay.o diff --git a/drivers/pwm/pwm-ipq.c b/drivers/pwm/pwm-ipq.c new file mode 100644 index 0000000000000000000000000000000000000000..9955b185bc60f27d770f3833d5a= cd7f587595324 --- /dev/null +++ b/drivers/pwm/pwm-ipq.c @@ -0,0 +1,239 @@ +// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 +/* + * Copyright (c) 2016-2017, 2020 The Linux Foundation. All rights reserved. + * + * Hardware notes / Limitations: + * - The PWM controller has no publicly available datasheet. + * - Each of the four channels is programmed via two 32-bit registers + * (REG0 and REG1 at 8-byte stride). + * - Period and duty-cycle reconfiguration is fully atomic: new divider, + * pre-divider, and high-duration values are latched by setting the + * UPDATE bit (bit 30 in REG1). The hardware applies the new settings + * at the beginning of the next period without disabling the output, + * so the currently running period is always completed. + * - On disable (clearing the ENABLE bit 31 in REG1), the hardware + * finishes the current period before stopping the output. The pin + * is then driven to the inactive (low) level. + * - Upon disabling, the hardware resets the pre-divider (PRE_DIV) and div= ider + * fields (PWM_DIV) in REG0 and REG1 to 0x0000 and 0x0001 respectively. + * - Only normal polarity is supported. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* The frequency range supported is 1 Hz to clock rate */ +#define IPQ_PWM_MAX_PERIOD_NS ((u64)NSEC_PER_SEC) + +/* + * The max value specified for each field is based on the number of bits + * in the pwm control register for that field + */ +#define IPQ_PWM_MAX_DIV 0xFFFF + +/* + * Two 32-bit registers for each PWM: REG0, and REG1. + * Base offset for PWM #i is at 8 * #i. + */ +#define IPQ_PWM_REG0 0 +#define IPQ_PWM_REG0_PWM_DIV GENMASK(15, 0) +#define IPQ_PWM_REG0_HI_DURATION GENMASK(31, 16) + +#define IPQ_PWM_REG1 4 +#define IPQ_PWM_REG1_PRE_DIV GENMASK(15, 0) + +/* + * Enable bit is set to enable output toggling in pwm device. + * Update bit is set to trigger the change and is unset automatically + * to reflect the changed divider and high duration values in register. + */ +#define IPQ_PWM_REG1_UPDATE BIT(30) +#define IPQ_PWM_REG1_ENABLE BIT(31) + +struct ipq_pwm_chip { + struct clk *clk; + void __iomem *mem; +}; + +static struct ipq_pwm_chip *ipq_pwm_from_chip(struct pwm_chip *chip) +{ + return pwmchip_get_drvdata(chip); +} + +static unsigned int ipq_pwm_reg_read(struct pwm_device *pwm, unsigned int = reg) +{ + struct ipq_pwm_chip *ipq_chip =3D ipq_pwm_from_chip(pwm->chip); + unsigned int off =3D 8 * pwm->hwpwm + reg; + + return readl(ipq_chip->mem + off); +} + +static void ipq_pwm_reg_write(struct pwm_device *pwm, unsigned int reg, + unsigned int val) +{ + struct ipq_pwm_chip *ipq_chip =3D ipq_pwm_from_chip(pwm->chip); + unsigned int off =3D 8 * pwm->hwpwm + reg; + + writel(val, ipq_chip->mem + off); +} + +static void config_div_and_duty(struct pwm_device *pwm, unsigned int pre_d= iv, + unsigned int pwm_div, unsigned long rate, u64 duty_ns, + bool enable) +{ + unsigned long hi_dur; + unsigned long val =3D 0; + + /* + * high duration =3D pwm duty * (pwm div + 1) + * pwm duty =3D duty_ns / period_ns + */ + hi_dur =3D mul_u64_u64_div_u64(duty_ns, rate, (pre_div + 1) * NSEC_PER_SE= C); + + val =3D FIELD_PREP(IPQ_PWM_REG0_HI_DURATION, hi_dur) | + FIELD_PREP(IPQ_PWM_REG0_PWM_DIV, pwm_div); + ipq_pwm_reg_write(pwm, IPQ_PWM_REG0, val); + + val =3D FIELD_PREP(IPQ_PWM_REG1_PRE_DIV, pre_div); + ipq_pwm_reg_write(pwm, IPQ_PWM_REG1, val); + + /* PWM enable toggle needs a separate write to REG1 */ + val |=3D IPQ_PWM_REG1_UPDATE; + if (enable) + val |=3D IPQ_PWM_REG1_ENABLE; + ipq_pwm_reg_write(pwm, IPQ_PWM_REG1, val); +} + +static int ipq_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct ipq_pwm_chip *ipq_chip =3D ipq_pwm_from_chip(chip); + unsigned long rate =3D clk_get_rate(ipq_chip->clk); + unsigned int pre_div, pwm_div; + u64 period_ns, duty_ns; + + if (state->polarity !=3D PWM_POLARITY_NORMAL) + return -EINVAL; + + if (state->period < DIV64_U64_ROUND_UP(NSEC_PER_SEC, rate)) + return -ERANGE; + + period_ns =3D min(state->period, IPQ_PWM_MAX_PERIOD_NS); + duty_ns =3D min(state->duty_cycle, period_ns); + + pwm_div =3D IPQ_PWM_MAX_DIV; + pre_div =3D mul_u64_u64_div_u64(period_ns, rate, (u64)NSEC_PER_SEC * (pwm= _div + 1)); + + if (pre_div > IPQ_PWM_MAX_DIV) + pre_div =3D IPQ_PWM_MAX_DIV; + + config_div_and_duty(pwm, pre_div, pwm_div, rate, duty_ns, state->enabled); + + return 0; +} + +static int ipq_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + struct ipq_pwm_chip *ipq_chip =3D ipq_pwm_from_chip(chip); + unsigned long rate =3D clk_get_rate(ipq_chip->clk); + unsigned int pre_div, pwm_div, hi_dur; + u64 effective_div, hi_div; + u32 reg0, reg1; + + reg1 =3D ipq_pwm_reg_read(pwm, IPQ_PWM_REG1); + state->enabled =3D reg1 & IPQ_PWM_REG1_ENABLE; + + if (!state->enabled) + return 0; + + reg0 =3D ipq_pwm_reg_read(pwm, IPQ_PWM_REG0); + + state->polarity =3D PWM_POLARITY_NORMAL; + + pwm_div =3D FIELD_GET(IPQ_PWM_REG0_PWM_DIV, reg0); + hi_dur =3D FIELD_GET(IPQ_PWM_REG0_HI_DURATION, reg0); + pre_div =3D FIELD_GET(IPQ_PWM_REG1_PRE_DIV, reg1); + + /* No overflow here, both pre_div and pwm_div <=3D 0xffff */ + effective_div =3D (pre_div + 1) * (pwm_div + 1); + state->period =3D DIV64_U64_ROUND_UP(effective_div * NSEC_PER_SEC, rate); + + hi_div =3D hi_dur * (pre_div + 1); + state->duty_cycle =3D DIV64_U64_ROUND_UP(hi_div * NSEC_PER_SEC, rate); + + /* + * ensure a valid config is passed back to PWM core in case duty_cycle + * is > period (>100%) + */ + state->duty_cycle =3D min(state->duty_cycle, state->period); + + return 0; +} + +static const struct pwm_ops ipq_pwm_ops =3D { + .apply =3D ipq_pwm_apply, + .get_state =3D ipq_pwm_get_state, +}; + +static int ipq_pwm_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct ipq_pwm_chip *pwm; + struct pwm_chip *chip; + int ret; + + chip =3D devm_pwmchip_alloc(dev, 4, sizeof(*pwm)); + if (IS_ERR(chip)) + return PTR_ERR(chip); + pwm =3D ipq_pwm_from_chip(chip); + + pwm->mem =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pwm->mem)) + return dev_err_probe(dev, PTR_ERR(pwm->mem), + "Failed to acquire resource\n"); + + pwm->clk =3D devm_clk_get_enabled(dev, NULL); + if (IS_ERR(pwm->clk)) + return dev_err_probe(dev, PTR_ERR(pwm->clk), + "Failed to get clock\n"); + + ret =3D devm_clk_rate_exclusive_get(dev, pwm->clk); + if (ret) + return dev_err_probe(dev, ret, + "Failed to lock clock rate\n"); + + chip->ops =3D &ipq_pwm_ops; + + ret =3D devm_pwmchip_add(dev, chip); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to add pwm chip\n"); + + return ret; +} + +static const struct of_device_id pwm_ipq_dt_match[] =3D { + { .compatible =3D "qcom,ipq6018-pwm", }, + {} +}; +MODULE_DEVICE_TABLE(of, pwm_ipq_dt_match); + +static struct platform_driver ipq_pwm_driver =3D { + .driver =3D { + .name =3D "ipq-pwm", + .of_match_table =3D pwm_ipq_dt_match, + }, + .probe =3D ipq_pwm_probe, +}; + +module_platform_driver(ipq_pwm_driver); + +MODULE_LICENSE("GPL"); --=20 2.52.0 From nobody Mon Dec 1 22:36:50 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 329E530BBA9; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251128-ipq-pwm-v19-3-13bc704cc6a5@outlook.com> References: <20251128-ipq-pwm-v19-0-13bc704cc6a5@outlook.com> In-Reply-To: <20251128-ipq-pwm-v19-0-13bc704cc6a5@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Baruch Siach , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem , Devi Priya , Baruch Siach , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764325760; l=1391; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=P5CK/w1B6zAAyU8rGtps6nkSbcs6bEiQ8DwAdl5cL3U=; b=/6XPsu39QbBZI3Mfycrd4KpyfOG5UfVQqg/ELTSp6pCKpOdt+L7d095xWp4jaKWkCWFEZAiS3 yx3LqvDbLPODoUhscnnWCvTkGGzfplAVS6dAFTt2OY51lGc7ZO/WvZ1 X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: Devi Priya Describe the PWM block on IPQ6018. Although PWM is in the TCSR area, make pwm its own node as simple-mfd has been removed from the bindings and as such hardware components should have its own node. Reviewed-by: Krzysztof Kozlowski Co-developed-by: Baruch Siach Signed-off-by: Baruch Siach Signed-off-by: Devi Priya Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qc= om/ipq6018.dtsi index 40f1c262126eff3761430a47472b52d27f961040..7866844cc09fd2c2c2f512ce2c8= fa7826fabc7aa 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -413,6 +413,16 @@ tcsr: syscon@1937000 { reg =3D <0x0 0x01937000 0x0 0x21000>; }; =20 + pwm: pwm@1941010 { + compatible =3D "qcom,ipq6018-pwm"; + reg =3D <0x0 0x01941010 0x0 0x20>; + clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates =3D <100000000>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + usb2: usb@70f8800 { compatible =3D "qcom,ipq6018-dwc3", "qcom,dwc3"; reg =3D <0x0 0x070f8800 0x0 0x400>; --=20 2.52.0 From nobody Mon Dec 1 22:36:50 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 46BC430BBB9; Fri, 28 Nov 2025 10:29:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764325763; cv=none; b=gh9T1aemB5mj+lBXozbRvl4WCV9KrjeYYArKOEBnQNkmkAdHr3GXVQMOfZAWWjoUy1o5QximIeDUb8YT0CsblV04yHYBGbYKBf2bvwUqu6dcxu4Lsa4Bn8x/au+Ba7CD3idQt0Agmb1buqfmcsUQGb9jyuRztxEdoXLqbDjECsg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764325763; c=relaxed/simple; bh=D+IYdEf1AAd+os28JYbeyk65ffDrEct65XrzEOazOeg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JkwwnoneRu7XzP/xz5dH+dTzQzdYNsxjGJfWtyeuGskAlPIKlzTrQYBdyl30iZdcQVugRfnZsgHFK9Fcde1Xmb1JysKfexJHt8Jkcbl+aZ2HERHZcRftX+CXPAA1B1SX/BQir6WJJvmQAr5yIBcVLwSdqv4zgsgGiy1MRsUN4EY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=kfCJ6MIX; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kfCJ6MIX" Received: by smtp.kernel.org (Postfix) with ESMTPS id E27C6C16AAE; Fri, 28 Nov 2025 10:29:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1764325762; bh=D+IYdEf1AAd+os28JYbeyk65ffDrEct65XrzEOazOeg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=kfCJ6MIXxh5g3VtiNQKOw8fvi08gnf5I/5fIjhL+oraPORosKHpHMNb9dxy8Tqagp SU/RGYLqNcuu/tDH3VvqzvcEt+Fbos2UE5rUJaO1YZH7ZdyrttrJYIE3edw/wnaQ6v GFUbDt1AttFToxLDdlWcSIPmRdW60Yqj2Os/fhLacGySiSXsjd1SuUZl+U+fmlsKlC rr25yPXOdZdIdQYQaXTa/ksREs5IztwR7lrCRnKMWSZG4ph4uJMQVQBMT3Cr+RsSAL UaCs4aaZ6hv0NSzap9ni3p4VI3lHMoVRrbQvnkM0iNajzYGh26INcK9gxq9wWDWgNh hUKTBn8K6QJ8Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2CCDD116F5; Fri, 28 Nov 2025 10:29:22 +0000 (UTC) From: George Moussalem via B4 Relay Date: Fri, 28 Nov 2025 14:29:16 +0400 Subject: [PATCH v19 4/6] arm64: dts: qcom: ipq5018: add pwm node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251128-ipq-pwm-v19-4-13bc704cc6a5@outlook.com> References: <20251128-ipq-pwm-v19-0-13bc704cc6a5@outlook.com> In-Reply-To: <20251128-ipq-pwm-v19-0-13bc704cc6a5@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Baruch Siach , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764325760; l=1233; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=6GVkWxkNyxlHL3r1TlaN/60BvZzwHu9RAFHkcBI1mf0=; b=wJJus1uGuxe93ESdWVLFnyIDmj7daYiRdQYKuZw7ulRV4lE9MB2ThNcHwkJJud/jreFF/Lfx8 hu6UZNc47OSCTv0mOqCyJBpC6aYNEfjL2SIe3rQf2w1SfOgNi07Vwgs X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem Describe the PWM block on IPQ5018. Although PWM is in the TCSR area, make pwm its own node as simple-mfd has been removed from the bindings and as such hardware components should have its own node. Reviewed-by: Dmitry Baryshkov Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qc= om/ipq5018.dtsi index f024b3cba33f6100ac3f4d45598ff2356e026dcf..562e81c2670ce95e306401f4f46= 46fd7f9950fe6 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -453,6 +453,16 @@ tcsr: syscon@1937000 { reg =3D <0x01937000 0x21000>; }; =20 + pwm: pwm@1941010 { + compatible =3D "qcom,ipq5018-pwm", "qcom,ipq6018-pwm"; + reg =3D <0x01941010 0x20>; + clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates =3D <100000000>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + sdhc_1: mmc@7804000 { compatible =3D "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0x7804000 0x1000>; --=20 2.52.0 From nobody Mon Dec 1 22:36:50 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7219730C631; Fri, 28 Nov 2025 10:29:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764325763; cv=none; b=TrZJk5blK0C9/K19E/p42NhguPggM0CwCZ95+ngNtXJEf18fT0uRI2B5kayDVxConnn3sgbju7f5jawEaB9WO/nOtZIItvzUOCAN9iiHUIVYwf86IZihBnjtzNLwJUTel3iHp6edPCcW/RSmSCFzB8mE5ssG+hK1qSnW9m+oL58= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764325763; c=relaxed/simple; bh=XQ4+jrCNUegmedw+kAaz44GruUsx1JtVMFlXfj8TCGg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=thTUXcFo/CBsmn4TnLBNcqmV6Q+nwi/JYD9BtaQe1NndvnOl+xHzG3gmjFhwvZB9W9CWJAhkJ7uRSJW0JNxNHTZ53kLsZhYy6Cmc//pQQq7PPHBvRk0fJTczdG1ADTsEOzXom2FBXhwV9UT+0vf22lEMSIs9G2VgvTUFmrkSKVk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Aj4TY4wk; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Aj4TY4wk" Received: by smtp.kernel.org (Postfix) with ESMTPS id F1FA9C19421; Fri, 28 Nov 2025 10:29:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1764325763; bh=XQ4+jrCNUegmedw+kAaz44GruUsx1JtVMFlXfj8TCGg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Aj4TY4wkGQYANB46OYfuBuNYlNA388L8b2ubHdtZDQY0lbqMVwga8v0AUlp26rX4A fhRrzIYwMg0p2vl4Qd2VupMxg6Z9sXNDknU3Ol2NM33ziPz4dPhSDfBfGpmsqz+CGi izNgZjjf2jnr8jznO/ierqEvpW3rlm7wKtE8GN/M5Bn498rhDz8IK/0rixbxl23Abf E4iJWT65uvGadfvG8yxvGJ3EkDRS5L+JKAJEZ49Q5NRlWCaoxqEa3r4UU08+WsuTc6 bbJ0O+FzvU4iqzPIOfZ9McGyGNvx/x0hvEDIWhAvhai57VfLG8M8U6pNe6to/isImY 9qtg/ycAGyQQw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4207CFD376; Fri, 28 Nov 2025 10:29:22 +0000 (UTC) From: George Moussalem via B4 Relay Date: Fri, 28 Nov 2025 14:29:17 +0400 Subject: [PATCH v19 5/6] arm64: dts: qcom: ipq5332: add pwm node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251128-ipq-pwm-v19-5-13bc704cc6a5@outlook.com> References: <20251128-ipq-pwm-v19-0-13bc704cc6a5@outlook.com> In-Reply-To: <20251128-ipq-pwm-v19-0-13bc704cc6a5@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Baruch Siach , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764325760; l=1253; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=ZzpZ9Oc2KX6I6uglSgS8/bCLV/sm5oDSygkEKKOZMT4=; b=3vGNro9Ja1P7N6wnvg4pg0K4XT4vfGr/1vBxM/TYRBpoF/OuWL4Ll4EwKyS4UMa+Vt8i6yf4P HcDzH7E0poyDIuA1aKoQX7xV54rNMoxuc4A9bakTy4KceSF9tR9R8sL X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem Describe the PWM block on IPQ5332. Although PWM is in the TCSR area, make pwm its own node as simple-mfd has been removed from the bindings and as such hardware components should have its own node. Reviewed-by: Dmitry Baryshkov Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qc= om/ipq5332.dtsi index 45fc512a3bab221c0d99f819294abf63369987da..e58051f6c1c4fd8ef85cbcc9b98= 433f599377c7a 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -334,6 +334,16 @@ tcsr: syscon@1937000 { reg =3D <0x01937000 0x21000>; }; =20 + pwm: pwm@1941010 { + compatible =3D "qcom,ipq5332-pwm", "qcom,ipq6018-pwm"; + reg =3D <0x01941010 0x20>; + clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates =3D <100000000>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + sdhc: mmc@7804000 { compatible =3D "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0x07804000 0x1000>, <0x07805000 0x1000>; --=20 2.52.0 From nobody Mon Dec 1 22:36:50 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7225830C633; Fri, 28 Nov 2025 10:29:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764325763; cv=none; b=axyQMJFuX6qJl+hBQoO4i/VAGEzqhjzAzlQLmumxWf73Kn02fw37S/lCLYWJBwNRiBB+pZBSUzGiw9pX3Xyr/ZA5tdQHEDuI8MBNfi823Lk7XBnEUj5qnQBdyaybIrIwUUHcz9YgpUYQsYVA8rdJSLkR0F4H/W2rfR1cN3yMO+A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764325763; c=relaxed/simple; bh=pe7YMi8OC3yKuQ3LkXUb2inQD2tWKaMwnCP66LSugwo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rcA4vmlBllyM8jcZsN/FEN5f+bGzips0BkTPZH+FMJlKVNQhQKo9T5XeN5txTs5mToiVqzclc4a+q+ocXzQi46FTKaoqYOkU90dYod6Xv9br9XPnzeEHCe7ykI97dxcmoS5h1dSo49dA2FxjJIVX614WchF3nFP1Wg2DewQssGo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WkpmcfUf; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WkpmcfUf" Received: by smtp.kernel.org (Postfix) with ESMTPS id 0E8E3C2BC9E; Fri, 28 Nov 2025 10:29:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1764325763; bh=pe7YMi8OC3yKuQ3LkXUb2inQD2tWKaMwnCP66LSugwo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=WkpmcfUf5qU3ZJFDn7CAQXK2ZY7DCjxSF0vLvSk0FgPDoL3Xp6RGU9dcik2mWzMqQ XZ8W9MBfNhtlfQwykUxsgkgsmh/tlqs2SlkrKWYW+j1Ec9Sn5By5ym5cmdzovR3Cfl 8EkqxPi6pm0aczkU3NZRK8Mfvjjn9STIyiNeZoJ3wRQE2kUN5Oog5Rymv/x8nU7P79 9LCAY8EoNVvEwteEFceFj02HBA1qxn7WKeCI0Kn+vY/4JgAftQPdAkUpW0crjwNC1h XBPy1ZP4WUyjEaykVyngtuhNwPrHJ4+ifUGfnG4SPDH5Dmq2QauBQeDPXEOQeTkFsJ B2LQkNjVEocRQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 03CFCD116EA; Fri, 28 Nov 2025 10:29:23 +0000 (UTC) From: George Moussalem via B4 Relay Date: Fri, 28 Nov 2025 14:29:18 +0400 Subject: [PATCH v19 6/6] arm64: dts: qcom: ipq9574: add pwm node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251128-ipq-pwm-v19-6-13bc704cc6a5@outlook.com> References: <20251128-ipq-pwm-v19-0-13bc704cc6a5@outlook.com> In-Reply-To: <20251128-ipq-pwm-v19-0-13bc704cc6a5@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Baruch Siach , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764325760; l=1234; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=9v7/UevGH2hUC1+SPEdsNKg4jplKvUQ7JbA9V5V+kSc=; b=NOosCxAFNtyHdh0CZXQHfKfcI/2XszvFfKQFo7nkdC6jnoLg4o1FtB4hVem3P5EZGMEwz5dQf 1Uza9u+gHQaDRU17TViI1KBbHu6+42RP25c0lx9nUJyj3NadDr59X8h X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem Describe the PWM block on IPQ9574. Although PWM is in the TCSR area, make pwm its own node as simple-mfd has been removed from the bindings and as such hardware components should have its own node. Reviewed-by: Dmitry Baryshkov Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qc= om/ipq9574.dtsi index 86c9cb9fffc98fdd1b0b08e81428ce5e7bb87e17..baf165dcb6b1be823332cdfac63= 1eef2633867b4 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -449,6 +449,16 @@ tcsr: syscon@1937000 { reg =3D <0x01937000 0x21000>; }; =20 + pwm: pwm@1941010 { + compatible =3D "qcom,ipq9574-pwm", "qcom,ipq6018-pwm"; + reg =3D <0x01941010 0x20>; + clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates =3D <100000000>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + sdhc_1: mmc@7804000 { compatible =3D "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0x07804000 0x1000>, --=20 2.52.0