From nobody Mon Dec 1 22:36:21 2025 Received: from sender3-pp-f112.zoho.com (sender3-pp-f112.zoho.com [136.143.184.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 59CA42DEA6E for ; Fri, 28 Nov 2025 21:08:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.184.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764364110; cv=pass; b=YwReoGmKnnI4fe24ipr0oywhml3S6JSsKMrLW8HrwBWRKcfMvnrEqHO/XjOs/HeXVFevb3glXPi0sy/HmT5tMCCbKRtipYKeF1StN1QAfd5J5PnG7KtQnGO3NA+gsZBFKoY6lecgLVfEowDrqaN+T8FsHZsYZCx35DnPCnTVSTw= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764364110; c=relaxed/simple; bh=z2gkLn5ZCVP2oqnHuFVDrOQjy2gBFXozrfujbVahNl8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=eRje5ZAyWU6S+tZGGqT7s4mA42OlNojuMXN++EcDUlAKAurSKvMl7065lAwa6cR0FJewYKDoe+jEk0/OvW0bRrqLBpDyfbDwzURvQeUe2LY0QNwA+b0dLm/aw2n6+RIobfbkVrsZLVPiUjKAuxh7q2xlrdl+7U7502jzalmMkiY= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=A19WYfmm; arc=pass smtp.client-ip=136.143.184.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="A19WYfmm" ARC-Seal: i=1; a=rsa-sha256; t=1764364062; cv=none; d=zohomail.com; s=zohoarc; b=grGoH9h1PdGRRJ3pOURX10ptElYtOElY974w2MJ/iJH02y/xfwCRz1gbwRGuc/wuA7lj/zQjV3oIc8ej0UMFDo3j3oL23IFiCWqnK1yWDrNLmfqCCPHIXV5Dy4CWuIfEQP0vAMDnwY50aXU4a1s+AMIC6Lznas6i+aNpsJ7TEK8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764364062; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=t9MOLGQnjIX0i6MWMRJ3Uvi+d7WdDeCX9ytBsMIm2YI=; b=CYfBc4MsjWzggFnQXVavpzzbVStLdISfZglLeeQQhtG2rMbSvHdssYCl+0EVeSsMfcmHJXIEgpS5uK+lTmKNmbDW9uO04auTgy0mlHHEXmIJMDqzEqDEk/axJ2YVUMSvtwiDZ7AL1Gc4spxtGK32AU/c+4HzArKpJ5Mnjhfp7Jo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1764364062; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=t9MOLGQnjIX0i6MWMRJ3Uvi+d7WdDeCX9ytBsMIm2YI=; b=A19WYfmmuZJQz5hKGgA2rAC1mCnirw/J0aOZzV92pMI9HVQPBcvOXqxaqSHnVma8 rU6eprfShFmVka2xK6CiKK70HatTZaZTNkTUbRjzGLXih8gJkp9t6vXmnjqAimE38dG XxsaBlXr4m0RafDUHinG68EEFAvvBcJAmYhS5ny8= Received: by mx.zohomail.com with SMTPS id 1764364060044867.1068385253593; Fri, 28 Nov 2025 13:07:40 -0800 (PST) From: Nicolas Frattaroli Date: Fri, 28 Nov 2025 22:05:50 +0100 Subject: [PATCH v5 14/17] drm/rockchip: dw_hdmi_qp: Implement "color format" DRM property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251128-color-format-v5-14-63e82f1db1e1@collabora.com> References: <20251128-color-format-v5-0-63e82f1db1e1@collabora.com> In-Reply-To: <20251128-color-format-v5-0-63e82f1db1e1@collabora.com> To: Harry Wentland , Leo Li , Rodrigo Siqueira , Alex Deucher , =?utf-8?q?Christian_K=C3=B6nig?= , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Jani Nikula , Rodrigo Vivi , Joonas Lahtinen , Tvrtko Ursulin , Dmitry Baryshkov , Sascha Hauer , Rob Herring Cc: kernel@collabora.com, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 Switch between requested color formats by setting the right bus formats, configuring the VO GRF registers, and setting the right output mode. Signed-off-by: Nicolas Frattaroli --- drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c | 61 ++++++++++++++++++++++= ++-- drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 1 + 2 files changed, 59 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c b/drivers/gpu/d= rm/rockchip/dw_hdmi_qp-rockchip.c index c9fe6aa3e3e3..c79ebd9e866c 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -135,24 +136,70 @@ dw_hdmi_qp_rockchip_encoder_atomic_check(struct drm_e= ncoder *encoder, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) { - struct rockchip_hdmi_qp *hdmi =3D to_rockchip_hdmi_qp(encoder); + struct drm_display_info *info =3D &conn_state->connector->display_info; struct rockchip_crtc_state *s =3D to_rockchip_crtc_state(crtc_state); + struct rockchip_hdmi_qp *hdmi =3D to_rockchip_hdmi_qp(encoder); union phy_configure_opts phy_cfg =3D {}; int ret; =20 if (hdmi->tmds_char_rate =3D=3D conn_state->hdmi.tmds_char_rate && - s->output_bpc =3D=3D conn_state->hdmi.output_bpc) + s->output_bpc =3D=3D conn_state->hdmi.output_bpc && + s->color_format =3D=3D conn_state->color_format) return 0; =20 + if (conn_state->color_format && + !(info->color_formats & conn_state->color_format)) + return -EINVAL; + + switch (conn_state->color_format) { + case DRM_COLOR_FORMAT_AUTO: + case DRM_COLOR_FORMAT_RGB444: + if (conn_state->hdmi.output_bpc =3D=3D 8) + s->bus_format =3D MEDIA_BUS_FMT_RGB888_1X24; + else if (conn_state->hdmi.output_bpc =3D=3D 10) + s->bus_format =3D MEDIA_BUS_FMT_RGB101010_1X30; + else + return -EINVAL; + s->output_mode =3D ROCKCHIP_OUT_MODE_AAAA; + break; + case DRM_COLOR_FORMAT_YCBCR444: + if (conn_state->hdmi.output_bpc =3D=3D 8) + s->bus_format =3D MEDIA_BUS_FMT_YUV8_1X24; + else if (conn_state->hdmi.output_bpc =3D=3D 10) + s->bus_format =3D MEDIA_BUS_FMT_YUV10_1X30; + else + return -EINVAL; + s->output_mode =3D ROCKCHIP_OUT_MODE_AAAA; + break; + case DRM_COLOR_FORMAT_YCBCR422: + if (conn_state->hdmi.output_bpc =3D=3D 8) + s->bus_format =3D MEDIA_BUS_FMT_YUYV8_1X16; + else /* 10 bpc possible, but currently busted */ + return -EINVAL; + s->output_mode =3D ROCKCHIP_OUT_MODE_YUV422; + break; + case DRM_COLOR_FORMAT_YCBCR420: + if (conn_state->hdmi.output_bpc =3D=3D 8) + s->bus_format =3D MEDIA_BUS_FMT_UYYVYY8_0_5X24; + else if (conn_state->hdmi.output_bpc =3D=3D 10) + s->bus_format =3D MEDIA_BUS_FMT_UYYVYY10_0_5X30; + else + return -EINVAL; + s->output_mode =3D ROCKCHIP_OUT_MODE_YUV420; + break; + default: + return -EINVAL; + } + phy_cfg.hdmi.tmds_char_rate =3D conn_state->hdmi.tmds_char_rate; phy_cfg.hdmi.bpc =3D conn_state->hdmi.output_bpc; =20 ret =3D phy_configure(hdmi->phy, &phy_cfg); if (!ret) { hdmi->tmds_char_rate =3D conn_state->hdmi.tmds_char_rate; - s->output_mode =3D ROCKCHIP_OUT_MODE_AAAA; s->output_type =3D DRM_MODE_CONNECTOR_HDMIA; s->output_bpc =3D conn_state->hdmi.output_bpc; + s->color_format =3D conn_state->color_format; } else { dev_err(hdmi->dev, "Failed to configure phy: %d\n", ret); } @@ -391,6 +438,8 @@ static void dw_hdmi_qp_rk3588_io_init(struct rockchip_h= dmi_qp *hdmi) static void dw_hdmi_qp_rk3576_enc_init(struct rockchip_hdmi_qp *hdmi, struct rockchip_crtc_state *state) { + enum hdmi_colorspace color =3D + drm_color_format_to_hdmi_colorspace(state->color_format); u32 val; =20 if (state->output_bpc =3D=3D 10) @@ -398,12 +447,16 @@ static void dw_hdmi_qp_rk3576_enc_init(struct rockchi= p_hdmi_qp *hdmi, else val =3D FIELD_PREP_WM16(RK3576_COLOR_DEPTH_MASK, RK3576_8BPC); =20 + val |=3D FIELD_PREP_WM16(RK3576_COLOR_FORMAT_MASK, color); + regmap_write(hdmi->vo_regmap, RK3576_VO0_GRF_SOC_CON8, val); } =20 static void dw_hdmi_qp_rk3588_enc_init(struct rockchip_hdmi_qp *hdmi, struct rockchip_crtc_state *state) { + enum hdmi_colorspace color =3D + drm_color_format_to_hdmi_colorspace(state->color_format); u32 val; =20 if (state->output_bpc =3D=3D 10) @@ -411,6 +464,8 @@ static void dw_hdmi_qp_rk3588_enc_init(struct rockchip_= hdmi_qp *hdmi, else val =3D FIELD_PREP_WM16(RK3588_COLOR_DEPTH_MASK, RK3588_8BPC); =20 + val |=3D FIELD_PREP_WM16(RK3588_COLOR_FORMAT_MASK, color); + regmap_write(hdmi->vo_regmap, hdmi->port_id ? RK3588_GRF_VO1_CON6 : RK3588_GRF_VO1_CON3, val); diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/= rockchip/rockchip_drm_drv.h index 4705dc6b8bd7..2549e58f3497 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h @@ -57,6 +57,7 @@ struct rockchip_crtc_state { u32 bus_format; u32 bus_flags; int color_space; + enum drm_color_format color_format; }; #define to_rockchip_crtc_state(s) \ container_of(s, struct rockchip_crtc_state, base) --=20 2.52.0