From nobody Mon Dec 1 22:36:23 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D85F12DC791 for ; Fri, 28 Nov 2025 21:07:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764364073; cv=pass; b=EHoNC0QtBBbVopTyCZxMnC+Yy+8l7QU7fwlwbJ7pAkYGyo4J5wpPTU1++wgTiaQecOoTBwEoDNdCzGIx6hxsd405DcOkLTAttF5rk8J98oknwZdXVYLRGPgfHs8v4iXkVUXISM2FASq+iQZrBKbqm0ufr0/eyTdtF4cRXpKP9lM= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764364073; c=relaxed/simple; bh=qELFdahJFjJanPq3aLi4A8Hh8zrv4Lhy4An+8vOTQhw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BnFQ7hxH1jiz9Dgcpho2h44eX78q3nvvuM8GZ2VL+JKlWSMm7RKVXh4vw1qHhFrR1HqeEyYfmcsa0ojaPBYaju+93ZK5kZPlRDa21xA7Vm9DaO9pVGPgtv8a+ozALVM1wG3QV55jI3hmS2gkDJp1Bc1/DCdN7neBnC34OcP3060= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=X77oHtYE; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="X77oHtYE" ARC-Seal: i=1; a=rsa-sha256; t=1764364034; cv=none; d=zohomail.com; s=zohoarc; b=Nu0xqIRmGhmozM0z0zhx5llyzEbLNOHWkrCU4t7O7jg+XLm0ir8eFhFLpE/Xrc0JCe6nWyjlkUo+g1q6YyZLrRoFJMpi6lB9R1/0EVdQ+hsVtTkCTNol8EMHqTRECb9C0Gkio3TAwiudMVJ8RacSQ7Q2obgBzZX9PrPsr08f770= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764364034; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=/MpT/AtBy9PLkAWryhr0CXHQiQHAmL0aMyFWeO6QNU4=; b=Mz7wRJx1Ya75IwbmXOAxiJVDZ6bDBRnMQbd4CdqxTh+19t/uM6GUIaTRdgHbZ34k3yl8cV+SrTl+RlFIqUxzuyJZcQY1+ZprolZnz315v3wH5VVusY+SL/+v6NGh9e1FKIzj+eBL6eVd3GnXihzjmKb2OIlyBYHG3YPqgEUnfn8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1764364034; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=/MpT/AtBy9PLkAWryhr0CXHQiQHAmL0aMyFWeO6QNU4=; b=X77oHtYEdxbo6XR7v5PUBCxoRX0oCXG27QaFIUrn875nX2jmz5q+lq54zeMXSle0 7ugpMG3+9L1c1ZulRuqTo+/S3tGbBH16m9T0KewhiXt3/fJc0y80Ryq4ejf3HRUSnpU n+qPdQMsUpVe0zWw0hDMcficet2PdBoCxfb4ONBU= Received: by mx.zohomail.com with SMTPS id 176436403133274.97397831652074; Fri, 28 Nov 2025 13:07:11 -0800 (PST) From: Nicolas Frattaroli Date: Fri, 28 Nov 2025 22:05:46 +0100 Subject: [PATCH v5 10/17] drm/rockchip: vop2: Fix YUV444 output Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251128-color-format-v5-10-63e82f1db1e1@collabora.com> References: <20251128-color-format-v5-0-63e82f1db1e1@collabora.com> In-Reply-To: <20251128-color-format-v5-0-63e82f1db1e1@collabora.com> To: Harry Wentland , Leo Li , Rodrigo Siqueira , Alex Deucher , =?utf-8?q?Christian_K=C3=B6nig?= , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Jani Nikula , Rodrigo Vivi , Joonas Lahtinen , Tvrtko Ursulin , Dmitry Baryshkov , Sascha Hauer , Rob Herring Cc: kernel@collabora.com, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 YUV444 (aka YCbCr444) output isn't working quite right on RK3588. The resulting image on the display, while identifying itself as YUV444, has some components swapped, even after adding the necessary DRM formats to the conversion functions. Judging by downstream, this is because YUV444 also needs an rb swap performed in the AFBC case. Add the DRM formats to the appropriate switch statements, and add a function for checking whether an rb swap needs to be performed in the AFBC case. Fixes: 604be85547ce ("drm/rockchip: Add VOP2 driver") Signed-off-by: Nicolas Frattaroli --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm= /rockchip/rockchip_drm_vop2.c index 498df0ce4680..f1252d1f06e9 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -176,6 +176,7 @@ static enum vop2_data_format vop2_convert_format(u32 fo= rmat) case DRM_FORMAT_ARGB2101010: case DRM_FORMAT_XBGR2101010: case DRM_FORMAT_ABGR2101010: + case DRM_FORMAT_VUY101010: return VOP2_FMT_XRGB101010; case DRM_FORMAT_XRGB8888: case DRM_FORMAT_ARGB8888: @@ -184,6 +185,7 @@ static enum vop2_data_format vop2_convert_format(u32 fo= rmat) return VOP2_FMT_ARGB8888; case DRM_FORMAT_RGB888: case DRM_FORMAT_BGR888: + case DRM_FORMAT_VUY888: return VOP2_FMT_RGB888; case DRM_FORMAT_RGB565: case DRM_FORMAT_BGR565: @@ -225,6 +227,7 @@ static enum vop2_afbc_format vop2_convert_afbc_format(u= 32 format) case DRM_FORMAT_ARGB2101010: case DRM_FORMAT_XBGR2101010: case DRM_FORMAT_ABGR2101010: + case DRM_FORMAT_VUY101010: return VOP2_AFBC_FMT_ARGB2101010; case DRM_FORMAT_XRGB8888: case DRM_FORMAT_ARGB8888: @@ -233,6 +236,7 @@ static enum vop2_afbc_format vop2_convert_afbc_format(u= 32 format) return VOP2_AFBC_FMT_ARGB8888; case DRM_FORMAT_RGB888: case DRM_FORMAT_BGR888: + case DRM_FORMAT_VUY888: return VOP2_AFBC_FMT_RGB888; case DRM_FORMAT_RGB565: case DRM_FORMAT_BGR565: @@ -270,6 +274,19 @@ static bool vop2_win_rb_swap(u32 format) } } =20 +static bool vop2_afbc_rb_swap(u32 format) +{ + switch (format) { + case DRM_FORMAT_NV24: + case DRM_FORMAT_NV30: + case DRM_FORMAT_VUY888: + case DRM_FORMAT_VUY101010: + return true; + default: + return false; + } +} + static bool vop2_afbc_uv_swap(u32 format) { switch (format) { @@ -1304,6 +1321,7 @@ static void vop2_plane_atomic_update(struct drm_plane= *plane, /* It's for head stride, each head size is 16 byte */ stride =3D ALIGN(stride, block_w) / block_w * 16; =20 + rb_swap =3D vop2_afbc_rb_swap(fb->format->format); uv_swap =3D vop2_afbc_uv_swap(fb->format->format); /* * This is a workaround for crazy IC design, Cluster @@ -1321,6 +1339,7 @@ static void vop2_plane_atomic_update(struct drm_plane= *plane, vop2_win_write(win, VOP2_WIN_AFBC_ENABLE, 1); vop2_win_write(win, VOP2_WIN_AFBC_FORMAT, afbc_format); vop2_win_write(win, VOP2_WIN_AFBC_UV_SWAP, uv_swap); + vop2_win_write(win, VOP2_WIN_AFBC_RB_SWAP, rb_swap); /* * On rk3566/8, this bit is auto gating enable, * but this function is not work well so we need --=20 2.52.0