From nobody Mon Dec 1 21:29:55 2025 Received: from mail-vs1-f48.google.com (mail-vs1-f48.google.com [209.85.217.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 664FE1C4A20 for ; Sat, 29 Nov 2025 03:47:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.217.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764388061; cv=none; b=pWTGpZNb3BWL/Ws1897jDlzojGInMYXxKH8bO0q7Skoqg2QdQXzd0SWhfZf86/otXkZTGS3nckJNI7qUSUxLbpi4togtld+ZASl9xeLhSkJY+jY/DalglMKtEiwL39ZokmO+toHs9IkSqs6YElDhkjWT+OtYduK4KA3kiPgLF3E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764388061; c=relaxed/simple; bh=rQHq0sGiu2mdFEBt0fl6MdifmUNZYpOHittrIbd/nKY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=AkWPygh6Vi2j77y3KRw7z4aVx1Kx3VdrtLYH97jdrUqXzbAoNpyQHJL5D2XGZSZN4qXJ6gWKz3GcSs05u48Y00pxmm2kKTdp/iI/WGzpMCfellKa7nw1Pkb0xZfo5QAMc8bzxQ6TtaGAnjfM1SM6XOXg0iyUHe8T6SaiGPQTFYI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=dkBCTEHc; arc=none smtp.client-ip=209.85.217.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="dkBCTEHc" Received: by mail-vs1-f48.google.com with SMTP id ada2fe7eead31-5d758dba570so1061621137.2 for ; Fri, 28 Nov 2025 19:47:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1764388058; x=1764992858; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=+9UjSoBnDQ20j4ZGp694sj4o1gSVNbN0KxtroIiBUBY=; b=dkBCTEHcCr8OpjRsXPxWCqEPTb1N+J93mamzr72yWbfRLALJO6sH1NXg94PaBH6PQH TrK10Lt81Agoe86qrwFqvSpN/c7n5H08zuwLQe2oZgV7nyLzsiIOk+BHu9YsMOUJ9yWt n4uQUQ8pXMNuUSoisTlhs0PZNMWeC5DveoN7kfpc6PGmfbEqDrkbKqXwHG4TchRPGoIO 4f8NTpr06RlD0fAokzupzKyKwOuNMyAQrDActZ+OWDbd6aFNAzeXqogUMzZt9BeqhaKz Q8BBB+bSwQAs28dHeC8mF2dfRfBdxgYq7EYOjseqi4ndycBVfFzKVX2ShGdTBlI0mKSg qEtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764388058; x=1764992858; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=+9UjSoBnDQ20j4ZGp694sj4o1gSVNbN0KxtroIiBUBY=; b=DWoK4MWAhOJeQHHeS3igNoR7HxJDMo7cqd40dPvTCFFxmOi2XCzDA/iIOFqX3e3xk5 wqyIErJudByeTRFLFNbchpRZKFQMDS282e0cebrc/Br/qyXQOu3/unbhPKnywXpgpuV5 VoWXHmbJaWNWquuSVgAvcfzWTaImWPWvn1BmPKI+XdhtBNBZnmR6hk3cJAZecTHQlmRe gfM1HVZX78b1YyKlZRvhKqkOS0Bx6x9CWWGD9Z0mXUVKKohx6L2WnEv8zPEtKsqlyEBj GkfACDuxSLlltH3rqmXecigq6x8X2exVdn47rsnpk3Zd2LeATg3uKecaEHMoDp8ebcjJ O4/g== X-Forwarded-Encrypted: i=1; AJvYcCVwhWM82HTaT0jB/2z/J4B3nOP0Dd9Pg0Sn2k1wvN6KGiQl9Fyy367sxB/ZW9jrBm1lRc7woU2yLmiFDpM=@vger.kernel.org X-Gm-Message-State: AOJu0YzUJu0bGvKneyIVEH0SL2hisq+u+ZYjvsIxRMUCsycqr7Sx4OH6 LMmy58exxthKd68KOyRJyYi9jf9e5o4jGjhdD8AOIjjKaMqFBEvVMTZ6 X-Gm-Gg: ASbGncsit590+Lez1vnbEg6gMoyONfgWSDlSr87VvxfVVRbFmjSyoW+RjhUIzXhiWKS o1ARWS4KLwf+M+ZNdk141KGFAVZFJicVoeB1olGRMAy1AK/VJwtJ3f8+SoNGok9PTPfP0q2takT jHwstOsvLm2qJcNY0Yzx29sYT8o3JsJNFMfFmq7hwZtfMBq8/uk64u13iEeEtl9C5+RLTW8xBds oHVayKH8AGZ4cQkXJcngui0Jmvkg0OuDDuXJTzHHTcXKOPgBtMR56QU6DkAEUdYoJ9UOQKJx9Fv I7Pim+TLtCYfgM/+VmdO1e1Zmx8HtxUBb9hVR3b1JAcyVE1/OaNt3P2eV0vQ69EDhiaYKtCcjlw BIvJCriSsqGZnfC1my+WD6o5X8LzI48vSJng/A5+Uub6ri9dL8iKrGXWSmYeUEeOlvovHB+UCaE AHsCrByfvbrg93 X-Google-Smtp-Source: AGHT+IFzpvnK4d2KpXG/45kSjdrugjb/jXZfBqQTOWS4SXk7wOPD2ST2pbr0ENcRDjfl9RHrINVE9g== X-Received: by 2002:a05:6102:3e96:b0:5df:b3ed:2c8b with SMTP id ada2fe7eead31-5e22442a01cmr6608852137.38.1764388058183; Fri, 28 Nov 2025 19:47:38 -0800 (PST) Received: from [192.168.100.70] ([2800:bf0:82:3d2:875c:6c76:e06b:3095]) by smtp.gmail.com with ESMTPSA id ada2fe7eead31-5e24d917860sm2562662137.2.2025.11.28.19.47.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Nov 2025 19:47:37 -0800 (PST) From: Kurt Borja Date: Fri, 28 Nov 2025 22:47:12 -0500 Subject: [PATCH v3 1/2] dt-bindings: iio: adc: Add TI ADS1018/ADS1118 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251128-ads1x18-v3-1-a6ebab815b2d@gmail.com> References: <20251128-ads1x18-v3-0-a6ebab815b2d@gmail.com> In-Reply-To: <20251128-ads1x18-v3-0-a6ebab815b2d@gmail.com> To: Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tobias Sperling Cc: David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jonathan Cameron , Kurt Borja X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=3207; i=kuurtb@gmail.com; h=from:subject:message-id; bh=rQHq0sGiu2mdFEBt0fl6MdifmUNZYpOHittrIbd/nKY=; b=owGbwMvMwCUmluBs8WX+lTTG02pJDJlaOddMu3Zdu6e7plxHZMVam/ULnFl77CXrfzTJK7Ub7 21/vPtpRykLgxgXg6yYIkt7wqJvj6Ly3vodCL0PM4eVCWQIAxenAEykeRvDP/MzgsKVsa/OScbP YxH1EJmjU9CTxTnBQUDi7aXwy0fXzWVkmC4eeNqY6eXzV0d4vRyvJNYxbN2S9+5nzaKofYJi3oV cjAA= X-Developer-Key: i=kuurtb@gmail.com; a=openpgp; fpr=54D3BE170AEF777983C3C63B57E3B6585920A69A Add documentation for Texas Instruments ADS1018 and ADS1118 analog-to-digital converters. Signed-off-by: Kurt Borja Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/iio/adc/ti,ads1018.yaml | 82 ++++++++++++++++++= ++++ MAINTAINERS | 6 ++ 2 files changed, 88 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/ti,ads1018.yaml b/Do= cumentation/devicetree/bindings/iio/adc/ti,ads1018.yaml new file mode 100644 index 000000000000..93c9b2921a54 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/ti,ads1018.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/ti,ads1018.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI ADS1018/ADS1118 SPI analog to digital converter + +maintainers: + - Kurt Borja + +description: | + The ADS1018/ADS1118 is a precision, low-power, 12-bit or 16-bit, noise-f= ree, + analog-to-digital converter (ADC). It integrates a programmable gain amp= lifier + (PGA), voltage reference, oscillator and high-accuracy temperature senso= r. + + Datasheets: + - ADS1018: https://www.ti.com/lit/ds/symlink/ads1018.pdf + - ADS1118: https://www.ti.com/lit/ds/symlink/ads1118.pdf + +properties: + compatible: + enum: + - ti,ads1018 + - ti,ads1118 + + reg: + maxItems: 1 + + vdd-supply: true + + spi-max-frequency: + maximum: 4000000 + + spi-cpha: true + + interrupts: + description: DOUT/DRDY (Data Out/Data Ready) line. + maxItems: 1 + + drdy-gpios: + description: + Extra GPIO line connected to DOUT/DRDY (Data Out/Data Ready). This a= llows + distinguishing between interrupts triggered by the data-ready signal= and + interrupts triggered by an SPI transfer. + maxItems: 1 + + '#io-channel-cells': + const: 1 + +required: + - compatible + - reg + - vdd-supply + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@0 { + compatible =3D "ti,ads1118"; + reg =3D <0>; + + spi-max-frequency =3D <4000000>; + spi-cpha; + + vdd-supply =3D <&vdd_3v3_reg>; + + interrupts-extended =3D <&gpio 14 IRQ_TYPE_EDGE_FALLING>; + drdy-gpios =3D <&gpio 14 GPIO_ACTIVE_LOW>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 31d98efb1ad1..3d5295b5d6eb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -25646,6 +25646,12 @@ S: Maintained F: Documentation/devicetree/bindings/iio/adc/ti,ads1119.yaml F: drivers/iio/adc/ti-ads1119.c =20 +TI ADS1018 ADC DRIVER +M: Kurt Borja +L: linux-iio@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/iio/adc/ti,ads1018.yaml + TI ADS7924 ADC DRIVER M: Hugo Villeneuve L: linux-iio@vger.kernel.org --=20 2.52.0 From nobody Mon Dec 1 21:29:55 2025 Received: from mail-vs1-f53.google.com (mail-vs1-f53.google.com [209.85.217.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36B01221F12 for ; Sat, 29 Nov 2025 03:47:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.217.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764388064; cv=none; b=ADlELesWh2DJi4FZ1PaEWxCdnO6Q13cbM155yMNkhiDmGjNpdh3kyG1/8hKVlclh60/vBN+GZvkPzVL8JhzCg3KeQeSsawMfnX4nbAIJ3hIzQdV3BzcFCbxfQS/cfP2Cwxi/NJD23brT8aGdzsAzhsndAZCsy1L22aq5oP0s55o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764388064; c=relaxed/simple; bh=vVyK2OA9BueB0Wqbshf0aIbe/dr0Ml0Vv7Dw2/Y6QzM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YlL3yCAEoPw1QVzyKns2oCXpMXLlXr0zWE7hYDMT0luQD8Pm7+V9xvKi52pjTGqZyk/FKURoZhCVxRl/jAFgXOqyGfp1MpNWbFMkSulGexC0Y1v15sdXxJRgb2nM31q58ouHuM3+lD5ScJ0neDSF+yW5fKrcFGaGZw/2TS+iLKY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Rjt8GW2l; arc=none smtp.client-ip=209.85.217.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Rjt8GW2l" Received: by mail-vs1-f53.google.com with SMTP id ada2fe7eead31-5dfae681ff8so1565499137.1 for ; Fri, 28 Nov 2025 19:47:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1764388060; x=1764992860; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=rmni4V+uKnAPjyol8loTSbjc9cQwYf5Y7BodpeonkIM=; b=Rjt8GW2lo2+c3PzBtbVHbdoMtwW/VD5KX0Izp0y3CA1y6mTNFWKcTLKf/6I2B/GZ51 gX017zOkXMWxB1GrOcGu2wKc0n+rm9rgUs0oqM8bsvt1HxykDd/txMGMs/NnLEV7aj0+ S5FJtBqijkmDDhsHAiFxcLtpIHgvLvVkJQAbezhc60lyG+ZFx8sU8bk5NjF2Ood7o8it XiKH2zpfqhSXy+WfrfPkkqm6hXj8g0P7QFpwUphYmUQN+Hg4KqyVNzN+1vtlIQ+XOPLu iA4+EFkhIVSh8o71t+c3AyOsD3luatsDzIFaP39ojL1scNf2T1akRmC2ErQYSOEjTkFX 7Vwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764388060; x=1764992860; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=rmni4V+uKnAPjyol8loTSbjc9cQwYf5Y7BodpeonkIM=; b=QyO4h3nTdJ4RzZdqxSZTGeBJvrxK2Z2lF3dXksIrvUjGSvwk/bIxeMC1vEN/TjtEgo IcvQIgAuQPwmURqaLExvj/8l2suurSaxQGVErQralY5sNIMEy9CqfpOjJoqux2uUEihD Afzpd33PhQoOpYGoa3IZxyMsF1c1M1UIZFvcvfgEfBcEEdppdz5Gazz9NpxGI5rd6C72 HFIdJe239BOApdsJzZbAToGvLEVW0W+9APyr32uYZN/M+DOArAnU/qBhk7zxfvYqHVi1 fgELjF7woM2b6ft2ZfM1R0iuK/DsZ5URkLZ3n6UHCsG0jgYg4NXv4A4ger+MFOagI8iI MGqw== X-Forwarded-Encrypted: i=1; AJvYcCXP1C7DLWgz4SSVOK8crdpKvaOqZHGtSE6FBQphKCjuEAICwdCnZurc7mzusVQgHQezYLOUrreDcoZqq6A=@vger.kernel.org X-Gm-Message-State: AOJu0YwC8LQeLr8CacScSbByiXOAUWlUVp2XdTXRSOzgVpsoYc2MKxCJ M1Pi27L2iqteJxzypWsW2kIIrzo9ZwroG26LEkUub0HZVGbks9/9Oc/f X-Gm-Gg: ASbGncsBzud9skd723MXaDJYWnyRxkUqkLXR7OaEXSD46Yyfj9g10SkGNCM04ubxbs4 Xzx/1Kvk5i3werfhc0wXFOLZNfylK2Ct3msaVOchK8/90ap/RU+fOfu1ewrxfDVhVH1NG6lZSnp 6jxXkhbIOyPzDDd+majHD3ec2YPa2i6Anm0GbHPjAvSd2CIUPaUoNguLeb1bPsU9WC3xBcpqLwz +lxTkdkZGnvc2Hi5Nx6CITcLM4mPRXBvysGh0jspscnh+8OKPPUF8s3Q/bnQkgJCD/3r/1emmPC 1ykcSR96gKlOmthLg6FFAgm/+9CWQc9W1MMWrm9MYD9T+a8PRCMpMvrcrFWuAhz3kfGXf10jJ3v K/MxtDlA08fCn0+2FDL+5pP/v3XpjspeQDbeKl8XnnnFltQPJLEeaVJlPxc+BeEgQH9WRJG2HOI vr1pZvEOn+MolQ X-Google-Smtp-Source: AGHT+IGxSFH3Bqps9OmzoPwMDyZjQ1B5vzVHzo7POG4taW5PgtexP6XyXLtzCFuQFZbnYFFtj5wGPg== X-Received: by 2002:a67:e70b:0:b0:5db:27e9:933f with SMTP id ada2fe7eead31-5e1de350db3mr12092118137.40.1764388060047; Fri, 28 Nov 2025 19:47:40 -0800 (PST) Received: from [192.168.100.70] ([2800:bf0:82:3d2:875c:6c76:e06b:3095]) by smtp.gmail.com with ESMTPSA id ada2fe7eead31-5e24d917860sm2562662137.2.2025.11.28.19.47.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Nov 2025 19:47:39 -0800 (PST) From: Kurt Borja Date: Fri, 28 Nov 2025 22:47:13 -0500 Subject: [PATCH v3 2/2] iio: adc: Add ti-ads1018 driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251128-ads1x18-v3-2-a6ebab815b2d@gmail.com> References: <20251128-ads1x18-v3-0-a6ebab815b2d@gmail.com> In-Reply-To: <20251128-ads1x18-v3-0-a6ebab815b2d@gmail.com> To: Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tobias Sperling Cc: David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jonathan Cameron , Kurt Borja X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=26437; i=kuurtb@gmail.com; h=from:subject:message-id; bh=vVyK2OA9BueB0Wqbshf0aIbe/dr0Ml0Vv7Dw2/Y6QzM=; b=owGbwMvMwCUmluBs8WX+lTTG02pJDJlaOddOX3ysbJAb8G0Vr1/Lo21fbj/5MLXuzOUmnly1n zkVG1f+6ShlYRDjYpAVU2RpT1j07VFU3lu/A6H3YeawMoEMYeDiFICJFFszMkyfl6K2P3xmit4p PZajYqYtSsunXBPMCd402771UPyXScyMDP82mczketxYmC7z49vyAJXK6StftIYzKW88VhyenDl djB8A X-Developer-Key: i=kuurtb@gmail.com; a=openpgp; fpr=54D3BE170AEF777983C3C63B57E3B6585920A69A Add ti-ads1018 driver for Texas Instruments ADS1018 and ADS1118 SPI analog-to-digital converters. These chips' MOSI pin is shared with a data-ready interrupt. Defining this interrupt in devicetree is optional, therefore we only create an IIO trigger if one is found. Handling this interrupt requires some considerations. When enabling the trigger the CS line is tied low (active), thus we need to hold spi_bus_lock() too, to avoid state corruption. This is done inside the set_trigger_state() callback, to let users use other triggers without wasting a bus lock. Signed-off-by: Kurt Borja --- MAINTAINERS | 1 + drivers/iio/adc/Kconfig | 12 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/ti-ads1018.c | 811 +++++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 825 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 3d5295b5d6eb..b3822cbff2c6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -25651,6 +25651,7 @@ M: Kurt Borja L: linux-iio@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/iio/adc/ti,ads1018.yaml +F: drivers/iio/adc/ti-ads1018.c =20 TI ADS7924 ADC DRIVER M: Hugo Villeneuve diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 58da8255525e..aa3f7023c64b 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -1664,6 +1664,18 @@ config TI_ADS1015 This driver can also be built as a module. If so, the module will be called ti-ads1015. =20 +config TI_ADS1018 + tristate "Texas Instruments ADS1018 ADC" + depends on SPI + select IIO_BUFFER + select IIO_TRIGGERED_BUFFER + help + If you say yes here you get support for Texas Instruments ADS1018= and + ADS1118 ADC chips. + + This driver can also be built as a module. If so, the module will= be + called ti-ads1018. + config TI_ADS1100 tristate "Texas Instruments ADS1100 and ADS1000 ADC" depends on I2C diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index 7cc8f9a12f76..72ef79becdec 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -145,6 +145,7 @@ obj-$(CONFIG_TI_ADC12138) +=3D ti-adc12138.o obj-$(CONFIG_TI_ADC128S052) +=3D ti-adc128s052.o obj-$(CONFIG_TI_ADC161S626) +=3D ti-adc161s626.o obj-$(CONFIG_TI_ADS1015) +=3D ti-ads1015.o +obj-$(CONFIG_TI_ADS1018) +=3D ti-ads1018.o obj-$(CONFIG_TI_ADS1100) +=3D ti-ads1100.o obj-$(CONFIG_TI_ADS1119) +=3D ti-ads1119.o obj-$(CONFIG_TI_ADS124S08) +=3D ti-ads124s08.o diff --git a/drivers/iio/adc/ti-ads1018.c b/drivers/iio/adc/ti-ads1018.c new file mode 100644 index 000000000000..2e851a1addfd --- /dev/null +++ b/drivers/iio/adc/ti-ads1018.c @@ -0,0 +1,811 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Texas Instruments ADS1018 ADC driver + * + * Copyright (C) 2025 Kurt Borja + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#define ADS1018_CFG_DEFAULT 0x058b + +#define ADS1018_CFG_OS_TRIG BIT(15) +#define ADS1018_CFG_TS_MODE_EN BIT(4) +#define ADS1018_CFG_PULL_UP BIT(3) +#define ADS1018_CFG_NOP BIT(1) +#define ADS1018_CFG_VALID (ADS1018_CFG_PULL_UP | ADS1018_CFG_NOP) + +#define ADS1018_CFG_MUX_MASK GENMASK(14, 12) + +#define ADS1018_CFG_PGA_MASK GENMASK(11, 9) +#define ADS1018_PGA_DEFAULT 2 + +#define ADS1018_CFG_MODE_MASK GENMASK(8, 8) +#define ADS1018_MODE_CONTINUOUS 0 +#define ADS1018_MODE_ONESHOT 1 + +#define ADS1018_CFG_DRATE_MASK GENMASK(7, 5) +#define ADS1018_DRATE_DEFAULT 4 + +#define ADS1018_CHANNELS_MAX 10 + +struct ads1018_chan_data { + u8 pga_mode; + u8 data_rate_mode; +}; + +struct ads1018_chip_info { + const char *name; + + const struct iio_chan_spec *channels; + unsigned long num_channels; + + /* IIO_VAL_INT */ + const unsigned int *data_rate_mode_to_hz; + unsigned long num_data_rate_mode_to_hz; + + /* IIO_VAL_INT_PLUS_NANO */ + const unsigned int (*pga_mode_to_gain)[2]; + unsigned long num_pga_mode_to_gain; + + /* IIO_VAL_INT_PLUS_MICRO */ + const int temp_scale[2]; +}; + +struct ads1018 { + struct spi_device *spi; + struct iio_trigger *indio_trig; + + struct gpio_desc *drdy_gpiod; + int drdy_irq; + + bool restore_mode; + + struct ads1018_chan_data chan_data[ADS1018_CHANNELS_MAX]; + const struct ads1018_chip_info *chip_info; + + struct spi_message msg_read; + struct spi_transfer xfer; + __be16 tx_buf[2] __aligned(IIO_DMA_MINALIGN); + __be16 rx_buf[2]; +}; + +#define ADS1018_VOLT_DIFF_CHAN(_addr, _chan, _chan2, _realbits) { \ + .type =3D IIO_VOLTAGE, \ + .channel =3D _chan, \ + .channel2 =3D _chan2, \ + .scan_index =3D _addr, \ + .scan_type =3D { \ + .sign =3D 's', \ + .realbits =3D _realbits, \ + .storagebits =3D 16, \ + .shift =3D 16 - _realbits, \ + .endianness =3D IIO_BE, \ + }, \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_SCALE) | \ + BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + .info_mask_shared_by_type_available =3D BIT(IIO_CHAN_INFO_SCALE), \ + .info_mask_shared_by_all_available =3D BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + .indexed =3D true, \ + .differential =3D true, \ +} + +#define ADS1018_VOLT_CHAN(_addr, _chan, _realbits) { \ + .type =3D IIO_VOLTAGE, \ + .channel =3D _chan, \ + .scan_index =3D _addr, \ + .scan_type =3D { \ + .sign =3D 's', \ + .realbits =3D _realbits, \ + .storagebits =3D 16, \ + .shift =3D 16 - _realbits, \ + .endianness =3D IIO_BE, \ + }, \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_SCALE) | \ + BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + .info_mask_shared_by_type_available =3D BIT(IIO_CHAN_INFO_SCALE), \ + .info_mask_shared_by_all_available =3D BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + .indexed =3D true, \ +} + +#define ADS1018_TEMP_CHAN(_addr, _realbits) { \ + .type =3D IIO_TEMP, \ + .channel =3D 0, \ + .scan_index =3D _addr, \ + .scan_type =3D { \ + .sign =3D 's', \ + .realbits =3D _realbits, \ + .storagebits =3D 16, \ + .shift =3D 16 - _realbits, \ + .endianness =3D IIO_BE, \ + }, \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_SCALE) | \ + BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + .info_mask_shared_by_all_available =3D BIT(IIO_CHAN_INFO_SAMP_FREQ), \ +} + +static const struct iio_chan_spec ads1118_iio_channels[] =3D { + ADS1018_VOLT_DIFF_CHAN(0, 0, 1, 16), + ADS1018_VOLT_DIFF_CHAN(1, 0, 3, 16), + ADS1018_VOLT_DIFF_CHAN(2, 1, 3, 16), + ADS1018_VOLT_DIFF_CHAN(3, 2, 3, 16), + ADS1018_VOLT_CHAN(4, 0, 16), + ADS1018_VOLT_CHAN(5, 1, 16), + ADS1018_VOLT_CHAN(6, 2, 16), + ADS1018_VOLT_CHAN(7, 3, 16), + ADS1018_TEMP_CHAN(8, 14), + IIO_CHAN_SOFT_TIMESTAMP(9), +}; + +static const struct iio_chan_spec ads1018_iio_channels[] =3D { + ADS1018_VOLT_DIFF_CHAN(0, 0, 1, 12), + ADS1018_VOLT_DIFF_CHAN(1, 0, 3, 12), + ADS1018_VOLT_DIFF_CHAN(2, 1, 3, 12), + ADS1018_VOLT_DIFF_CHAN(3, 2, 3, 12), + ADS1018_VOLT_CHAN(4, 0, 12), + ADS1018_VOLT_CHAN(5, 1, 12), + ADS1018_VOLT_CHAN(6, 2, 12), + ADS1018_VOLT_CHAN(7, 3, 12), + ADS1018_TEMP_CHAN(8, 12), + IIO_CHAN_SOFT_TIMESTAMP(9), +}; + +/** + * ads1018_get_data_rate_mode - Get current data-rate mode for a channel. + * @ad1018: Device data + * @address: Channel address + * + * Context: Expects iio_device_claim_direct() is held. + * + * Return: Current data-rate mode for the channel at @address. + */ +static u8 ads1018_get_data_rate_mode(struct ads1018 *ads1018, unsigned int= address) +{ + return ads1018->chan_data[address].data_rate_mode; +} + +/** + * ads1018_get_pga_mode - Get current PGA mode for a channel. + * @ad1018: Device data + * @address: Channel address + * + * Context: Expects iio_device_claim_direct() is held. + * + * Return: Current PGA mode for the channel at @address. + */ +static u8 ads1018_get_pga_mode(struct ads1018 *ads1018, unsigned int addre= ss) +{ + return ads1018->chan_data[address].pga_mode; +} + +/** + * ads1018_set_data_rate_mode - Set a data-rate mode for a channel. + * @ad1018: Device data + * @address: Channel address + * @val: New data-rate mode for channel at @address. + * + * Context: Expects iio_device_claim_direct() is held. + * + * Lazily set a new data-rate mode for a channel. + */ +static void ads1018_set_data_rate_mode(struct ads1018 *ads1018, unsigned i= nt address, + u8 val) +{ + ads1018->chan_data[address].data_rate_mode =3D val; +} + +/** + * ads1018_set_pga_mode - Set a PGA mode for a channel. + * @ad1018: Device data + * @address: Channel address + * @val: New PGA mode for channel at @address. + * + * Context: Expects iio_device_claim_direct() is held. + * + * Lazily set a new PGA mode for a channel. + */ +static void ads1018_set_pga_mode(struct ads1018 *ads1018, unsigned int add= ress, + u8 val) +{ + ads1018->chan_data[address].pga_mode =3D val; +} + +/** + * ads1018_calc_delay - Calculates an appropriate delay for a single-shot + * reading + * @ad1018: Device data + * + * Calculates an appropriate delay for a single shot reading, assuming the + * device's maximum data-rate is used. + * + * Context: Expects iio_device_claim_direct() is held. + * + * Return: Delay in microseconds. + */ +static unsigned long ads1018_calc_delay(struct ads1018 *ads1018) +{ + const struct ads1018_chip_info *chip_info =3D ads1018->chip_info; + unsigned long max_drate_mode =3D chip_info->num_data_rate_mode_to_hz - 1; + unsigned int hz =3D chip_info->data_rate_mode_to_hz[max_drate_mode]; + + /* We subtract 10% data-rate error */ + hz -=3D DIV_ROUND_UP(hz, 10); + + /* Calculate time per sample in microseconds */ + return DIV_ROUND_UP(MICROHZ_PER_HZ, hz); +} + +/** + * ads1018_read_unlocked - Reads a conversion value from the device + * @ad1018: Device data + * @cnv: ADC Conversion value + * @hold_cs: Keep CS line asserted after the SPI transfer + * + * Reads the most recent ADC conversion value, without updating the + * device's configuration. + * + * Context: Expects spi_bus_lock() is held. + * + * Return: 0 on success, negative errno on error. + */ +static int ads1018_read_unlocked(struct ads1018 *ads1018, __be16 *cnv, boo= l hold_cs) +{ + int ret; + + ads1018->xfer.cs_change =3D hold_cs; + + ret =3D spi_sync_locked(ads1018->spi, &ads1018->msg_read); + if (ret) + return ret; + + if (cnv) + *cnv =3D ads1018->rx_buf[0]; + + return 0; +} + +/** + * ads1018_oneshot - Performs a one-shot reading sequence + * @ad1018: Device data + * @cfg: New configuration for the device + * @cnv: Conversion value + * + * Writes a new configuration, waits an appropriate delay (assuming the new + * configuration uses the maximum data-rate) and then reads the most recent + * conversion. + * + * Context: Expects iio_device_claim_direct() is held. + * + * Return: 0 on success, negative errno on error. + */ +static int ads1018_oneshot(struct ads1018 *ads1018, u16 cfg, u16 *cnv) +{ + struct spi_transfer xfer[2] =3D { + { + .tx_buf =3D ads1018->tx_buf, + .len =3D sizeof(ads1018->tx_buf), + .delay =3D { + .value =3D ads1018_calc_delay(ads1018), + .unit =3D SPI_DELAY_UNIT_USECS, + }, + }, + { + .rx_buf =3D ads1018->rx_buf, + .len =3D sizeof(ads1018->rx_buf), + }, + }; + int ret; + + ads1018->tx_buf[0] =3D cpu_to_be16(cfg); + ads1018->tx_buf[1] =3D 0; + + ret =3D spi_sync_transfer(ads1018->spi, xfer, ARRAY_SIZE(xfer)); + if (ret) + return ret; + + *cnv =3D be16_to_cpu(ads1018->rx_buf[0]); + + return 0; +} + +static int +ads1018_read_raw_unlocked(struct iio_dev *indio_dev, struct iio_chan_spec = const *chan, + int *val, int *val2, long mask) +{ + struct ads1018 *ads1018 =3D iio_priv(indio_dev); + const struct ads1018_chip_info *chip_info =3D ads1018->chip_info; + u8 drate_mode =3D ads1018_get_data_rate_mode(ads1018, chan->scan_index); + u8 pga_mode =3D ads1018_get_pga_mode(ads1018, chan->scan_index); + u8 max_drate_mode =3D chip_info->num_data_rate_mode_to_hz - 1; + u16 cnv, cfg; + int ret; + + switch (mask) { + case IIO_CHAN_INFO_RAW: + cfg =3D ADS1018_CFG_VALID | ADS1018_CFG_OS_TRIG; + cfg |=3D FIELD_PREP(ADS1018_CFG_MUX_MASK, chan->scan_index); + cfg |=3D FIELD_PREP(ADS1018_CFG_PGA_MASK, pga_mode); + cfg |=3D FIELD_PREP(ADS1018_CFG_MODE_MASK, ADS1018_MODE_ONESHOT); + cfg |=3D FIELD_PREP(ADS1018_CFG_DRATE_MASK, max_drate_mode); + + if (chan->type =3D=3D IIO_TEMP) + cfg |=3D ADS1018_CFG_TS_MODE_EN; + + ret =3D ads1018_oneshot(ads1018, cfg, &cnv); + if (ret) + return ret; + + cnv >>=3D chan->scan_type.shift; + *val =3D sign_extend32(cnv, chan->scan_type.realbits - 1); + + return IIO_VAL_INT; + + case IIO_CHAN_INFO_SCALE: + switch (chan->type) { + case IIO_VOLTAGE: + *val =3D chip_info->pga_mode_to_gain[pga_mode][0]; + *val2 =3D chip_info->pga_mode_to_gain[pga_mode][1]; + return IIO_VAL_INT_PLUS_NANO; + + case IIO_TEMP: + *val =3D chip_info->temp_scale[0]; + *val2 =3D chip_info->temp_scale[1]; + return IIO_VAL_INT_PLUS_MICRO; + + default: + return -EOPNOTSUPP; + } + + case IIO_CHAN_INFO_SAMP_FREQ: + *val =3D chip_info->data_rate_mode_to_hz[drate_mode]; + return IIO_VAL_INT; + + default: + return -EOPNOTSUPP; + } +} + +static int +ads1018_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *ch= an, + int *val, int *val2, long mask) +{ + int ret; + + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + ret =3D ads1018_read_raw_unlocked(indio_dev, chan, val, val2, mask); + iio_device_release_direct(indio_dev); + + return ret; +} + +static int +ads1018_read_avail(struct iio_dev *indio_dev, struct iio_chan_spec const *= chan, + const int **vals, int *type, int *length, long mask) +{ + struct ads1018 *ads1018 =3D iio_priv(indio_dev); + + switch (mask) { + case IIO_CHAN_INFO_SCALE: + *type =3D IIO_VAL_INT_PLUS_NANO; + *vals =3D (const int *)ads1018->chip_info->pga_mode_to_gain; + *length =3D ads1018->chip_info->num_pga_mode_to_gain * 2; + return IIO_AVAIL_LIST; + + case IIO_CHAN_INFO_SAMP_FREQ: + *type =3D IIO_VAL_INT; + *vals =3D ads1018->chip_info->data_rate_mode_to_hz; + *length =3D ads1018->chip_info->num_data_rate_mode_to_hz; + return IIO_AVAIL_LIST; + + default: + return -EOPNOTSUPP; + } +} + +static int +ads1018_write_raw_unlocked(struct iio_dev *indio_dev, struct iio_chan_spec= const *chan, + int val, int val2, long mask) +{ + struct ads1018 *ads1018 =3D iio_priv(indio_dev); + const struct ads1018_chip_info *info =3D ads1018->chip_info; + unsigned int i; + + switch (mask) { + case IIO_CHAN_INFO_SCALE: + for (i =3D 0; i < info->num_pga_mode_to_gain; i++) { + if (val =3D=3D info->pga_mode_to_gain[i][0] && + val2 =3D=3D info->pga_mode_to_gain[i][1]) + break; + } + + if (i =3D=3D info->num_pga_mode_to_gain) + return -EINVAL; + + ads1018_set_pga_mode(ads1018, chan->scan_index, i); + return 0; + + case IIO_CHAN_INFO_SAMP_FREQ: + for (i =3D 0; i < info->num_data_rate_mode_to_hz; i++) { + if (val =3D=3D info->data_rate_mode_to_hz[i]) + break; + } + + if (i =3D=3D info->num_data_rate_mode_to_hz) + return -EINVAL; + + ads1018_set_data_rate_mode(ads1018, chan->scan_index, i); + return 0; + + default: + return -EOPNOTSUPP; + } +} + +static int +ads1018_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *c= han, + int val, int val2, long mask) +{ + int ret; + + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + ret =3D ads1018_write_raw_unlocked(indio_dev, chan, val, val2, mask); + iio_device_release_direct(indio_dev); + + return ret; +} + +static int +ads1018_write_raw_get_fmt(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, long mask) +{ + switch (mask) { + case IIO_CHAN_INFO_SCALE: + return IIO_VAL_INT_PLUS_NANO; + default: + return IIO_VAL_INT_PLUS_MICRO; + } +} + +static const struct iio_info ads1018_iio_info =3D { + .read_raw =3D ads1018_read_raw, + .read_avail =3D ads1018_read_avail, + .write_raw =3D ads1018_write_raw, + .write_raw_get_fmt =3D ads1018_write_raw_get_fmt, +}; + +static void ads1018_set_trigger_enable(struct ads1018 *ads1018) +{ + spi_bus_lock(ads1018->spi->controller); + ads1018_read_unlocked(ads1018, NULL, true); + enable_irq(ads1018->drdy_irq); +} + +static void ads1018_set_trigger_disable(struct ads1018 *ads1018) +{ + disable_irq(ads1018->drdy_irq); + ads1018_read_unlocked(ads1018, NULL, false); + spi_bus_unlock(ads1018->spi->controller); +} + +static int ads1018_set_trigger_state(struct iio_trigger *trig, bool state) +{ + struct ads1018 *ads1018 =3D iio_trigger_get_drvdata(trig); + + /* + * We need to lock the SPI bus and tie CS low (hold_cs) to catch + * data-ready interrupts, otherwise the MISO line enters a Hi-Z state. + */ + + if (state) + ads1018_set_trigger_enable(ads1018); + else + ads1018_set_trigger_disable(ads1018); + + return 0; +} + +static const struct iio_trigger_ops ads1018_trigger_ops =3D { + .set_trigger_state =3D ads1018_set_trigger_state, + .validate_device =3D iio_trigger_validate_own_device, +}; + +static int ads1018_buffer_preenable(struct iio_dev *indio_dev) +{ + struct ads1018 *ads1018 =3D iio_priv(indio_dev); + const struct ads1018_chip_info *chip_info =3D ads1018->chip_info; + unsigned int pga, drate, addr; + u16 cfg; + + addr =3D find_first_bit(indio_dev->active_scan_mask, iio_get_masklength(i= ndio_dev)); + pga =3D ads1018_get_pga_mode(ads1018, addr); + drate =3D ads1018_get_data_rate_mode(ads1018, addr); + + cfg =3D ADS1018_CFG_VALID; + cfg |=3D FIELD_PREP(ADS1018_CFG_MUX_MASK, addr); + cfg |=3D FIELD_PREP(ADS1018_CFG_PGA_MASK, pga); + cfg |=3D FIELD_PREP(ADS1018_CFG_MODE_MASK, ADS1018_MODE_CONTINUOUS); + cfg |=3D FIELD_PREP(ADS1018_CFG_DRATE_MASK, drate); + + if (chip_info->channels[addr].type =3D=3D IIO_TEMP) + cfg |=3D ADS1018_CFG_TS_MODE_EN; + + ads1018->tx_buf[0] =3D cpu_to_be16(cfg); + ads1018->tx_buf[1] =3D 0; + + return spi_write(ads1018->spi, ads1018->tx_buf, sizeof(ads1018->tx_buf)); +} + +static int ads1018_buffer_postdisable(struct iio_dev *indio_dev) +{ + struct ads1018 *ads1018 =3D iio_priv(indio_dev); + + ads1018->tx_buf[0] =3D cpu_to_be16(ADS1018_CFG_DEFAULT); + ads1018->tx_buf[1] =3D 0; + + return spi_write(ads1018->spi, ads1018->tx_buf, sizeof(ads1018->tx_buf)); +} + +static const struct iio_buffer_setup_ops ads1018_buffer_ops =3D { + .preenable =3D ads1018_buffer_preenable, + .postdisable =3D ads1018_buffer_postdisable, + .validate_scan_mask =3D iio_validate_scan_mask_onehot, +}; + +static irqreturn_t ads1018_irq_handler(int irq, void *dev_id) +{ + struct ads1018 *ads1018 =3D dev_id; + + /* + * We need to check if the "drdy" pin is actually active or if it's a + * pending interrupt triggered by the SPI transfer. + */ + if (ads1018->drdy_gpiod && !gpiod_get_value(ads1018->drdy_gpiod)) + return IRQ_HANDLED; + + iio_trigger_poll(ads1018->indio_trig); + + return IRQ_HANDLED; +} + +static irqreturn_t ads1018_trigger_handler(int irq, void *p) +{ + struct iio_poll_func *pf =3D p; + struct iio_dev *indio_dev =3D pf->indio_dev; + struct ads1018 *ads1018 =3D iio_priv(indio_dev); + struct { + __be16 conv; + aligned_s64 ts; + } scan =3D {}; + int ret; + + if (iio_device_claim_buffer_mode(indio_dev)) + goto out_notify_done; + + if (iio_trigger_using_own(indio_dev)) { + disable_irq(ads1018->drdy_irq); + ret =3D ads1018_read_unlocked(ads1018, &scan.conv, true); + enable_irq(ads1018->drdy_irq); + } else { + ret =3D spi_read(ads1018->spi, ads1018->rx_buf, sizeof(ads1018->rx_buf)); + scan.conv =3D ads1018->rx_buf[0]; + } + + iio_device_release_buffer_mode(indio_dev); + + if (ret) + goto out_notify_done; + + iio_push_to_buffers_with_ts(indio_dev, &scan, sizeof(scan), pf->timestamp= ); + +out_notify_done: + iio_trigger_notify_done(ads1018->indio_trig); + + return IRQ_HANDLED; +} + +static int ads1018_trigger_setup(struct iio_dev *indio_dev) +{ + struct ads1018 *ads1018 =3D iio_priv(indio_dev); + struct spi_device *spi =3D ads1018->spi; + struct device *dev =3D &spi->dev; + const char *con_id =3D "drdy"; + int ret; + + ads1018->drdy_gpiod =3D devm_gpiod_get_optional(dev, con_id, GPIOD_IN); + if (IS_ERR(ads1018->drdy_gpiod)) + return dev_err_probe(dev, PTR_ERR(ads1018->drdy_gpiod), + "Failed to get %s GPIO.\n", con_id); + + /* First try to get IRQ from SPI core, then from GPIO */ + if (spi->irq > 0) + ads1018->drdy_irq =3D spi->irq; + else if (ads1018->drdy_gpiod) + ads1018->drdy_irq =3D gpiod_to_irq(ads1018->drdy_gpiod); + if (ads1018->drdy_irq < 0) + return dev_err_probe(dev, ads1018->drdy_irq, + "Failed to get IRQ from %s GPIO.\n", con_id); + + /* An IRQ line is only an optional requirement for the IIO trigger */ + if (ads1018->drdy_irq =3D=3D 0) + return 0; + + ads1018->indio_trig =3D devm_iio_trigger_alloc(dev, "%s-dev%d-drdy", indi= o_dev->name, + iio_device_id(indio_dev)); + if (!ads1018->indio_trig) + return -ENOMEM; + + iio_trigger_set_drvdata(ads1018->indio_trig, ads1018); + ads1018->indio_trig->ops =3D &ads1018_trigger_ops; + + ret =3D devm_iio_trigger_register(dev, ads1018->indio_trig); + if (ret) + return ret; + + /* + * The "data-ready" IRQ line is shared with the MOSI pin, thus we need + * to keep it disabled until we actually request data. + */ + return devm_request_irq(dev, ads1018->drdy_irq, ads1018_irq_handler, + IRQF_NO_AUTOEN, ads1018->chip_info->name, ads1018); +} + +static int ads1018_spi_probe(struct spi_device *spi) +{ + const struct ads1018_chip_info *info =3D spi_get_device_match_data(spi); + struct iio_dev *indio_dev; + struct ads1018 *ads1018; + int ret; + + indio_dev =3D devm_iio_device_alloc(&spi->dev, sizeof(*ads1018)); + if (!indio_dev) + return -ENOMEM; + + ads1018 =3D iio_priv(indio_dev); + ads1018->spi =3D spi; + ads1018->chip_info =3D info; + spi_set_drvdata(spi, ads1018); + + indio_dev->modes =3D INDIO_DIRECT_MODE; + indio_dev->name =3D info->name; + indio_dev->info =3D &ads1018_iio_info; + indio_dev->channels =3D info->channels; + indio_dev->num_channels =3D info->num_channels; + + for (unsigned int i =3D 0; i < ADS1018_CHANNELS_MAX; i++) { + ads1018->chan_data[i].data_rate_mode =3D ADS1018_DRATE_DEFAULT; + ads1018->chan_data[i].pga_mode =3D ADS1018_PGA_DEFAULT; + } + + ads1018->xfer.rx_buf =3D ads1018->rx_buf; + ads1018->xfer.len =3D sizeof(ads1018->rx_buf); + spi_message_init_with_transfers(&ads1018->msg_read, &ads1018->xfer, 1); + + ret =3D ads1018_trigger_setup(indio_dev); + if (ret) + return ret; + + ret =3D devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, iio_pollfun= c_store_time, + ads1018_trigger_handler, &ads1018_buffer_ops); + if (ret) + return ret; + + return devm_iio_device_register(&spi->dev, indio_dev); +} + +/** + * ADS1018_FSR_TO_SCALE - Converts FSR into scale + * @_fsr: Full-scale range in millivolts + * @_res: ADC resolution + * + * Return: Scale in IIO_VAL_INT_PLUS_NANO format + */ +#define ADS1018_FSR_TO_SCALE(_fsr, _res) \ + { 0, ((_fsr) * (MICRO >> 6)) / BIT((_res) - 6) } + +static const unsigned int ads1018_gain_table[][2] =3D { + ADS1018_FSR_TO_SCALE(6144, 11), + ADS1018_FSR_TO_SCALE(4096, 11), + ADS1018_FSR_TO_SCALE(2048, 11), + ADS1018_FSR_TO_SCALE(1024, 11), + ADS1018_FSR_TO_SCALE(512, 11), + ADS1018_FSR_TO_SCALE(256, 11), +}; + +static const unsigned int ads1118_gain_table[][2] =3D { + ADS1018_FSR_TO_SCALE(6144, 15), + ADS1018_FSR_TO_SCALE(4096, 15), + ADS1018_FSR_TO_SCALE(2048, 15), + ADS1018_FSR_TO_SCALE(1024, 15), + ADS1018_FSR_TO_SCALE(512, 15), + ADS1018_FSR_TO_SCALE(256, 15), +}; + +static const unsigned int ads1018_data_rate_table[] =3D { + 128, 250, 490, 920, 1600, 2400, 3300, +}; + +static const unsigned int ads1118_data_rate_table[] =3D { + 8, 16, 32, 64, 128, 250, 475, 860, +}; + +static const struct ads1018_chip_info ads1018_chip_info =3D { + .name =3D "ads1018", + + .channels =3D ads1018_iio_channels, + .num_channels =3D ARRAY_SIZE(ads1018_iio_channels), + + .pga_mode_to_gain =3D ads1018_gain_table, + .num_pga_mode_to_gain =3D ARRAY_SIZE(ads1018_gain_table), + + .data_rate_mode_to_hz =3D ads1018_data_rate_table, + .num_data_rate_mode_to_hz =3D ARRAY_SIZE(ads1018_data_rate_table), + + .temp_scale =3D { 0, 125000 }, +}; + +static const struct ads1018_chip_info ads1118_chip_info =3D { + .name =3D "ads1118", + + .channels =3D ads1118_iio_channels, + .num_channels =3D ARRAY_SIZE(ads1118_iio_channels), + + .pga_mode_to_gain =3D ads1118_gain_table, + .num_pga_mode_to_gain =3D ARRAY_SIZE(ads1118_gain_table), + + .data_rate_mode_to_hz =3D ads1118_data_rate_table, + .num_data_rate_mode_to_hz =3D ARRAY_SIZE(ads1118_data_rate_table), + + .temp_scale =3D { 0, 31250 }, +}; + +static const struct of_device_id ads1018_of_match[] =3D { + { .compatible =3D "ti,ads1018", .data =3D &ads1018_chip_info }, + { .compatible =3D "ti,ads1118", .data =3D &ads1118_chip_info }, + { } +}; +MODULE_DEVICE_TABLE(of, ads1018_of_match); + +static const struct spi_device_id ads1018_spi_match[] =3D { + { "ads1018", (kernel_ulong_t)&ads1018_chip_info }, + { "ads1118", (kernel_ulong_t)&ads1118_chip_info }, + { } +}; +MODULE_DEVICE_TABLE(spi, ads1018_spi_match); + +static struct spi_driver ads1018_spi_driver =3D { + .driver =3D { + .name =3D "ads1018", + .of_match_table =3D ads1018_of_match, + }, + .probe =3D ads1018_spi_probe, + .id_table =3D ads1018_spi_match, +}; + +module_spi_driver(ads1018_spi_driver); + +MODULE_DESCRIPTION("Texas Instruments ADS1018 ADC Driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Kurt Borja "); --=20 2.52.0