From nobody Mon Dec 1 21:29:59 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 078B02FFDE2; Thu, 27 Nov 2025 19:00:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764270038; cv=none; b=FMJWKtCHPbUN+Sx63RiM4Euq5/nvDcTjkPhLpRGylmS6M6BYP/J3t8ru0lm1rsboMQYuGZt9npQWT6QNmJtenwNgzMMBP3bMQXCTWPpguh7ENFLYTnmREH3zOnm7mM2slDcf8XiwNNAyTqA2sii5cRgD0GnOzpBoLsueXimAkBE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764270038; c=relaxed/simple; bh=yuDl+vV9uGiSg1HH//XrjlArBAJ2MDXUa6CNLBLNkqc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=IHzn5E5v+GM3U96cxBAcEs4TM6a3NbLnYh5cCpIRW7ToApAK6wm3BYOo9je+C/lOo1/Mwv3fKFJQz7DeyhJiCCzPXZo3Pc4w9WkYcuQpCTAOgnp+mIRyTQRg0p8ZFBDOuItfVVvPWD62GE926FuTVpmLtFSTSjBx0VbUqYqEMbM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Yi9tuhDu; arc=none smtp.client-ip=192.198.163.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Yi9tuhDu" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1764270037; x=1795806037; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yuDl+vV9uGiSg1HH//XrjlArBAJ2MDXUa6CNLBLNkqc=; b=Yi9tuhDu8ZkFKKb0rP3vKKO6Ogh7bQKEWLQu5mRiyFSZvj7bBEiYEPqR JQ9Z49Cw/oXEBnQo0djeYBLaO1evdO12S+rRcRZMEBS9USRAxSQ9uMOim O4xjDo4Cq6Jk/EAjBsIDr/4h5IlAf6OZUn2ytSac9uwKePJKa6tRFjMHl a6d+cBmVAxvU93oCYohOGKqSqaES8ORzDA1ry641h637xIcKYpT+WshvR ZhspFywfY5ZWhCrHtKl9tumL6OXki8Z7wInm5rggyfmBZgFW/y7l11Uck u4UPjXkGA+5X/2Maq0j7hh0rg9xbJYT2//Dw4dLO5DLQFhF7uudRLkOgW Q==; X-CSE-ConnectionGUID: /gXmrsw3Rs+QQXhJnSTafw== X-CSE-MsgGUID: PhOUnBNTTjilPHP7m64vNg== X-IronPort-AV: E=McAfee;i="6800,10657,11626"; a="91796255" X-IronPort-AV: E=Sophos;i="6.20,231,1758610800"; d="scan'208";a="91796255" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Nov 2025 11:00:35 -0800 X-CSE-ConnectionGUID: vdevt3uLSx6K1c9n9Gi2Vg== X-CSE-MsgGUID: QzmVBog8TnmHOap/Zht6Lw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.20,231,1758610800"; d="scan'208";a="216645897" Received: from black.igk.intel.com ([10.91.253.5]) by fmviesa002.fm.intel.com with ESMTP; 27 Nov 2025 11:00:33 -0800 Received: by black.igk.intel.com (Postfix, from userid 1003) id 394FEA0; Thu, 27 Nov 2025 20:00:32 +0100 (CET) From: Andy Shevchenko To: Prajna Rajendra Kumar , Andy Shevchenko , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Brown , David Laight Subject: [PATCH v3 1/6] spi: microchip-core: use min() instead of min_t() Date: Thu, 27 Nov 2025 19:58:58 +0100 Message-ID: <20251127190031.2998705-2-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251127190031.2998705-1-andriy.shevchenko@linux.intel.com> References: <20251127190031.2998705-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" min_t(int, a, b) casts an 'unsigned int' to 'int'. This might lead to the cases when big number is wrongly chosen. On the other hand, the SPI transfer length is unsigned and driver uses signed type for an unknown reason. Change the type of the transfer length to be unsigned and convert use min() instead of min_t(). Reviewed-by: David Laight Reviewed-by: Prajna Rajendra Kumar Signed-off-by: Andy Shevchenko --- drivers/spi/spi-microchip-core-spi.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/spi/spi-microchip-core-spi.c b/drivers/spi/spi-microch= ip-core-spi.c index 16e0885474a0..08ccdc5f0cc9 100644 --- a/drivers/spi/spi-microchip-core-spi.c +++ b/drivers/spi/spi-microchip-core-spi.c @@ -74,8 +74,8 @@ struct mchp_corespi { u8 *rx_buf; u32 clk_gen; int irq; - int tx_len; - int rx_len; + unsigned int tx_len; + unsigned int rx_len; u32 fifo_depth; }; =20 @@ -214,7 +214,7 @@ static irqreturn_t mchp_corespi_interrupt(int irq, void= *dev_id) spi->regs + MCHP_CORESPI_REG_INTCLEAR); finalise =3D true; dev_err(&host->dev, - "RX OVERFLOW: rxlen: %d, txlen: %d\n", + "RX OVERFLOW: rxlen: %u, txlen: %u\n", spi->rx_len, spi->tx_len); } =20 @@ -223,7 +223,7 @@ static irqreturn_t mchp_corespi_interrupt(int irq, void= *dev_id) spi->regs + MCHP_CORESPI_REG_INTCLEAR); finalise =3D true; dev_err(&host->dev, - "TX UNDERFLOW: rxlen: %d, txlen: %d\n", + "TX UNDERFLOW: rxlen: %u, txlen: %u\n", spi->rx_len, spi->tx_len); } =20 @@ -283,7 +283,7 @@ static int mchp_corespi_transfer_one(struct spi_control= ler *host, spi->rx_len =3D xfer->len; =20 while (spi->tx_len) { - int fifo_max =3D min_t(int, spi->tx_len, spi->fifo_depth); + unsigned int fifo_max =3D min(spi->tx_len, spi->fifo_depth); =20 mchp_corespi_write_fifo(spi, fifo_max); mchp_corespi_read_fifo(spi, fifo_max); --=20 2.50.1 From nobody Mon Dec 1 21:29:59 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 448133019D9; Thu, 27 Nov 2025 19:00:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764270039; cv=none; b=OGgj1x4y0+/GjJ91cvwZxELtbyQXuNiYMwNiOOpnqK2fiu49ozjMAb16ejnos2MAfZv43FREXuBLROPZg3v22wX8AHqwrxHsYSd14Pk8O8upKI7/CzC91J7TqdhkMSVJGhgsK5BpplF1ZMR9yUx/Kw6vWLJK4Kk3q0L9W8EXY4A= ARC-Message-Signature: i=1; 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d="scan'208";a="216645899" Received: from black.igk.intel.com ([10.91.253.5]) by fmviesa002.fm.intel.com with ESMTP; 27 Nov 2025 11:00:33 -0800 Received: by black.igk.intel.com (Postfix, from userid 1003) id 3D67DA1; Thu, 27 Nov 2025 20:00:32 +0100 (CET) From: Andy Shevchenko To: Prajna Rajendra Kumar , Andy Shevchenko , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Brown Subject: [PATCH v3 2/6] spi: microchip-core: Refactor FIFO read and write handlers Date: Thu, 27 Nov 2025 19:58:59 +0100 Message-ID: <20251127190031.2998705-3-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251127190031.2998705-1-andriy.shevchenko@linux.intel.com> References: <20251127190031.2998705-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Make both handlers to be shorter and easier to understand. While at it, unify their style. Signed-off-by: Andy Shevchenko --- drivers/spi/spi-microchip-core-spi.c | 31 +++++++++++----------------- 1 file changed, 12 insertions(+), 19 deletions(-) diff --git a/drivers/spi/spi-microchip-core-spi.c b/drivers/spi/spi-microch= ip-core-spi.c index 08ccdc5f0cc9..439745a36f9c 100644 --- a/drivers/spi/spi-microchip-core-spi.c +++ b/drivers/spi/spi-microchip-core-spi.c @@ -97,15 +97,12 @@ static inline void mchp_corespi_read_fifo(struct mchp_c= orespi *spi, u32 fifo_max MCHP_CORESPI_STATUS_RXFIFO_EMPTY) ; =20 + /* On TX-only transfers always perform a dummy read */ data =3D readb(spi->regs + MCHP_CORESPI_REG_RXDATA); + if (spi->rx_buf) + *spi->rx_buf++ =3D data; =20 spi->rx_len--; - if (!spi->rx_buf) - continue; - - *spi->rx_buf =3D data; - - spi->rx_buf++; } } =20 @@ -127,23 +124,19 @@ static void mchp_corespi_disable_ints(struct mchp_cor= espi *spi) =20 static inline void mchp_corespi_write_fifo(struct mchp_corespi *spi, u32 f= ifo_max) { - int i =3D 0; - - while ((i < fifo_max) && - !(readb(spi->regs + MCHP_CORESPI_REG_STAT) & - MCHP_CORESPI_STATUS_TXFIFO_FULL)) { - u32 word; - - word =3D spi->tx_buf ? *spi->tx_buf : 0xaa; - writeb(word, spi->regs + MCHP_CORESPI_REG_TXDATA); + for (int i =3D 0; i < fifo_max; i++) { + if (readb(spi->regs + MCHP_CORESPI_REG_STAT) & + MCHP_CORESPI_STATUS_TXFIFO_FULL) + break; =20 + /* On RX-only transfers always perform a dummy write */ if (spi->tx_buf) - spi->tx_buf++; + writeb(*spi->tx_buf++, spi->regs + MCHP_CORESPI_REG_TXDATA); + else + writeb(0xaa, spi->regs + MCHP_CORESPI_REG_TXDATA); =20 - i++; + spi->tx_len--; } - - spi->tx_len -=3D i; } =20 static void mchp_corespi_set_cs(struct spi_device *spi, bool disable) --=20 2.50.1 From nobody Mon Dec 1 21:29:59 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 71EB52E11D7; Thu, 27 Nov 2025 19:00:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764270037; cv=none; b=Enk91FBONJoaJ2eA/QGuCawzH+Nd0uleEPr+WC6b86EbRlmYIM6LpkdJd8n35H4YS564RuYoV9I0LDKKkeM0Vv+6T/T4Bm9gqSct68WyOcSgnpfttwh6ZXPIUmGdI0zTl/mZOi4ue8sZAWc0XizmR+Dq+iY5dyKEjcLmegzj1bg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764270037; c=relaxed/simple; bh=oYdB1GXPJJOqdeYXnfWfCep2w45kxF/iHqiuAw9Dd8Y=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=flrTo3My9L/YoJd2SjaI20zY8zsP3EwmZmhpKFA9mKX8d+Z9UrwD27YJvmR0TVfJKEx2m9ZyeQp+NXbUXTo0d2I0mwCYMRh4wf8smd4k21f7jgTSa+c+hakiyWnRtpLMWtjfGsySqtspC8Pk+laL7iBp7GfRZjTqoYh1VyH1NG0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=CFA7dQIC; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="CFA7dQIC" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1764270035; x=1795806035; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=oYdB1GXPJJOqdeYXnfWfCep2w45kxF/iHqiuAw9Dd8Y=; b=CFA7dQICEpW4TvkrnBAy1KElZj1e461RkmlZH/ILSxxAql8G8FQYNQ8T uQZnmzyqdtTBBpXGjPGSeawH+WLmzctYLpJsK9mcMFQYSG1V905kNLW58 LhITWS2TwF1Q3duNoRaetyyElW2OodYOFknlvwXROjkuk95oqTfEZyKkN GPNVimUvsqvjGbxlQwDUNioE4AlIGUmbzQ4vi2kP1Qes0lnT7zaYZ2vfT hixw6Wqn2WgWUHNS6xYCbxGX1HnGOwVvrXNEDvfAo8QHU+dEaIqbsKI9l D+Uftr7ERZvz7N95ZPiaZQR9PHAqDq4udGMV397BYIwf/fooqalk27mhQ Q==; X-CSE-ConnectionGUID: 6vSX+E05STWNxQU0OunJuQ== X-CSE-MsgGUID: UNVNi81DSzG0BjU/+mpt9w== X-IronPort-AV: E=McAfee;i="6800,10657,11626"; a="66480310" X-IronPort-AV: E=Sophos;i="6.20,231,1758610800"; d="scan'208";a="66480310" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Nov 2025 11:00:35 -0800 X-CSE-ConnectionGUID: NnNSyZSvS0SZFo2EAYehbQ== X-CSE-MsgGUID: Zxggb9enT3SHj9/RnhR7tw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.20,231,1758610800"; d="scan'208";a="193312322" Received: from black.igk.intel.com ([10.91.253.5]) by orviesa007.jf.intel.com with ESMTP; 27 Nov 2025 11:00:33 -0800 Received: by black.igk.intel.com (Postfix, from userid 1003) id 41A94A2; Thu, 27 Nov 2025 20:00:32 +0100 (CET) From: Andy Shevchenko To: Prajna Rajendra Kumar , Andy Shevchenko , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Brown Subject: [PATCH v3 3/6] spi: microchip-core: Replace dead code (-ENOMEM error message) Date: Thu, 27 Nov 2025 19:59:00 +0100 Message-ID: <20251127190031.2998705-4-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251127190031.2998705-1-andriy.shevchenko@linux.intel.com> References: <20251127190031.2998705-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" First of all, the convention in the kernel that we do not issue error messages for -ENOMEM. Second, it's ignored by dev_err_probe(). Replace dead code by a simple return statement. Reviewed-by: Prajna Rajendra Kumar Signed-off-by: Andy Shevchenko --- drivers/spi/spi-microchip-core-spi.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/spi/spi-microchip-core-spi.c b/drivers/spi/spi-microch= ip-core-spi.c index 439745a36f9c..fa6fb2d3f7d0 100644 --- a/drivers/spi/spi-microchip-core-spi.c +++ b/drivers/spi/spi-microchip-core-spi.c @@ -298,8 +298,7 @@ static int mchp_corespi_probe(struct platform_device *p= dev) =20 host =3D devm_spi_alloc_host(&pdev->dev, sizeof(*spi)); if (!host) - return dev_err_probe(&pdev->dev, -ENOMEM, - "unable to allocate host for SPI controller\n"); + return -ENOMEM; =20 platform_set_drvdata(pdev, host); =20 --=20 2.50.1 From nobody Mon Dec 1 21:29:59 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F0C1A2EC08C; Thu, 27 Nov 2025 19:00:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764270039; cv=none; b=nAewaKr5Vzf0TZL5izQbQmgsYZz+RLyPA6NDBlk7+bpcgFX8l8tchfxHWSEEZxrjn7QEmR2PQsn1BHz3Yvz2H/OQ094vmuLsEbL9Xa5uM2SGvN/xw+hULRS73jshnIaCdcEn39N+HVNPNqHSJkT1WqYdxA8eaw3ahsD1bwTwVKc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764270039; c=relaxed/simple; bh=F6dY4g5b095vmulQz6TtHxeicjOX2tjh0n6p49QTNSo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kteZmdAeqvya/rM2FAPFLaWZayPWn/tUx+gv2k7tI6MSURhWXOymTXhnZV2UnaiiVdQmV9du88Wlp38jSMP3xV/AFr7LzBXofhDi+2vvgXO36SH3Ivqgy9QtERW3gnLGeKm223+yw4znDhpCPvpKWStmWujEDxTqlKufXoDRBD0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Q3EuHD39; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Q3EuHD39" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1764270037; x=1795806037; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=F6dY4g5b095vmulQz6TtHxeicjOX2tjh0n6p49QTNSo=; b=Q3EuHD39D3aCavt5x5Pgi3N6R1Yo1M4BTSNQn++fUBPS/S+svRcv/KjR 2k2wF9qw34K8Ep8Bihv6WE23W7fodhoTJW+BR4z9A449dQCufwn9hzgjO WokRObhK2NW3YjxrKiQC73MXTN56JCQ7eid+4g0/7boG4iLDDiIDFQHF/ vRWjPjsoSeqQlMwmfGZOeVs0TbR7i1gE6jdrO7+FOeRfpGd6Hk4o9BrtG h8//uxY1p0HHPBRSjIO37hWnAjuMBblebLQjdcu6yycyRlLcnUY0SfsoW fyt/cZfKxK2HPOIvf2vClgWYPGH9o6f4R+bNwwYKyD6GstNnwUg/z+Gzo w==; X-CSE-ConnectionGUID: fCMtGKNNRoKZvZj03XyKqA== X-CSE-MsgGUID: cMOZZ+QsSMysi2hlRWNr/g== X-IronPort-AV: E=McAfee;i="6800,10657,11626"; a="66480307" X-IronPort-AV: E=Sophos;i="6.20,231,1758610800"; d="scan'208";a="66480307" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Nov 2025 11:00:35 -0800 X-CSE-ConnectionGUID: gKzQ6W2hQAObozTdva2saA== X-CSE-MsgGUID: blVabnGbSs+WCNQYfb//lg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.20,231,1758610800"; d="scan'208";a="193312319" Received: from black.igk.intel.com ([10.91.253.5]) by orviesa007.jf.intel.com with ESMTP; 27 Nov 2025 11:00:33 -0800 Received: by black.igk.intel.com (Postfix, from userid 1003) id 45B83A3; Thu, 27 Nov 2025 20:00:32 +0100 (CET) From: Andy Shevchenko To: Prajna Rajendra Kumar , Andy Shevchenko , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Brown Subject: [PATCH v3 4/6] spi: microchip-core: Utilise temporary variable for struct device Date: Thu, 27 Nov 2025 19:59:01 +0100 Message-ID: <20251127190031.2998705-5-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251127190031.2998705-1-andriy.shevchenko@linux.intel.com> References: <20251127190031.2998705-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a temporary variable to keep a pointer to struct device. Utilise it where it makes sense. Reviewed-by: Prajna Rajendra Kumar Signed-off-by: Andy Shevchenko --- drivers/spi/spi-microchip-core-spi.c | 44 +++++++++++++--------------- 1 file changed, 21 insertions(+), 23 deletions(-) diff --git a/drivers/spi/spi-microchip-core-spi.c b/drivers/spi/spi-microch= ip-core-spi.c index fa6fb2d3f7d0..0ece51460ee0 100644 --- a/drivers/spi/spi-microchip-core-spi.c +++ b/drivers/spi/spi-microchip-core-spi.c @@ -289,6 +289,7 @@ static int mchp_corespi_transfer_one(struct spi_control= ler *host, static int mchp_corespi_probe(struct platform_device *pdev) { const char *protocol =3D "motorola"; + struct device *dev =3D &pdev->dev; struct spi_controller *host; struct mchp_corespi *spi; struct resource *res; @@ -296,13 +297,13 @@ static int mchp_corespi_probe(struct platform_device = *pdev) bool assert_ssel; int ret =3D 0; =20 - host =3D devm_spi_alloc_host(&pdev->dev, sizeof(*spi)); + host =3D devm_spi_alloc_host(dev, sizeof(*spi)); if (!host) return -ENOMEM; =20 platform_set_drvdata(pdev, host); =20 - if (of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs)) + if (of_property_read_u32(dev->of_node, "num-cs", &num_cs)) num_cs =3D MCHP_CORESPI_MAX_CS; =20 /* @@ -310,12 +311,12 @@ static int mchp_corespi_probe(struct platform_device = *pdev) * CoreSPI can be configured for Motorola, TI or NSC. * The current driver supports only Motorola mode. */ - ret =3D of_property_read_string(pdev->dev.of_node, "microchip,protocol-co= nfiguration", + ret =3D of_property_read_string(dev->of_node, "microchip,protocol-configu= ration", &protocol); if (ret && ret !=3D -EINVAL) - return dev_err_probe(&pdev->dev, ret, "Error reading protocol-configurat= ion\n"); + return dev_err_probe(dev, ret, "Error reading protocol-configuration\n"); if (strcmp(protocol, "motorola") !=3D 0) - return dev_err_probe(&pdev->dev, -EINVAL, + return dev_err_probe(dev, -EINVAL, "CoreSPI: protocol '%s' not supported by this driver\n", protocol); =20 @@ -323,11 +324,11 @@ static int mchp_corespi_probe(struct platform_device = *pdev) * Motorola mode (0-3): CFG_MOT_MODE * Mode is fixed in the IP configurator. */ - ret =3D of_property_read_u32(pdev->dev.of_node, "microchip,motorola-mode"= , &mode); + ret =3D of_property_read_u32(dev->of_node, "microchip,motorola-mode", &mo= de); if (ret) mode =3D MCHP_CORESPI_DEFAULT_MOTOROLA_MODE; else if (mode > 3) - return dev_err_probe(&pdev->dev, -EINVAL, + return dev_err_probe(dev, -EINVAL, "invalid 'microchip,motorola-mode' value %u\n", mode); =20 /* @@ -335,9 +336,9 @@ static int mchp_corespi_probe(struct platform_device *p= dev) * The hardware allows frame sizes <=3D APB data width. * However, this driver currently only supports 8-bit frames. */ - ret =3D of_property_read_u32(pdev->dev.of_node, "microchip,frame-size", &= frame_size); + ret =3D of_property_read_u32(dev->of_node, "microchip,frame-size", &frame= _size); if (!ret && frame_size !=3D 8) - return dev_err_probe(&pdev->dev, -EINVAL, + return dev_err_probe(dev, -EINVAL, "CoreSPI: frame size %u not supported by this driver\n", frame_size); =20 @@ -347,9 +348,9 @@ static int mchp_corespi_probe(struct platform_device *p= dev) * To prevent CS deassertion when TX FIFO drains, the ssel-active property * keeps CS asserted for the full SPI transfer. */ - assert_ssel =3D of_property_read_bool(pdev->dev.of_node, "microchip,ssel-= active"); + assert_ssel =3D of_property_read_bool(dev->of_node, "microchip,ssel-activ= e"); if (!assert_ssel) - return dev_err_probe(&pdev->dev, -EINVAL, + return dev_err_probe(dev, -EINVAL, "hardware must enable 'microchip,ssel-active' to keep CS asserted= for the SPI transfer\n"); =20 spi =3D spi_controller_get_devdata(host); @@ -361,9 +362,9 @@ static int mchp_corespi_probe(struct platform_device *p= dev) host->bits_per_word_mask =3D SPI_BPW_RANGE_MASK(4, 32); host->transfer_one =3D mchp_corespi_transfer_one; host->set_cs =3D mchp_corespi_set_cs; - host->dev.of_node =3D pdev->dev.of_node; + host->dev.of_node =3D dev->of_node; =20 - ret =3D of_property_read_u32(pdev->dev.of_node, "fifo-depth", &spi->fifo_= depth); + ret =3D of_property_read_u32(dev->of_node, "fifo-depth", &spi->fifo_depth= ); if (ret) spi->fifo_depth =3D MCHP_CORESPI_DEFAULT_FIFO_DEPTH; =20 @@ -375,24 +376,21 @@ static int mchp_corespi_probe(struct platform_device = *pdev) if (spi->irq < 0) return spi->irq; =20 - ret =3D devm_request_irq(&pdev->dev, spi->irq, mchp_corespi_interrupt, - IRQF_SHARED, dev_name(&pdev->dev), host); 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charset="utf-8" Use SPI_MODE_X_MASK instead of open coded variant. Reviewed-by: Prajna Rajendra Kumar Signed-off-by: Andy Shevchenko --- drivers/spi/spi-microchip-core-spi.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/spi/spi-microchip-core-spi.c b/drivers/spi/spi-microch= ip-core-spi.c index 0ece51460ee0..d37e193e282f 100644 --- a/drivers/spi/spi-microchip-core-spi.c +++ b/drivers/spi/spi-microchip-core-spi.c @@ -153,8 +153,6 @@ static void mchp_corespi_set_cs(struct spi_device *spi,= bool disable) =20 static int mchp_corespi_setup(struct spi_device *spi) { - u32 dev_mode =3D spi->mode & (SPI_CPOL | SPI_CPHA); - if (spi_get_csgpiod(spi, 0)) return 0; =20 @@ -163,7 +161,7 @@ static int mchp_corespi_setup(struct spi_device *spi) return -EOPNOTSUPP; } =20 - if (dev_mode & ~spi->controller->mode_bits) { + if ((spi->mode ^ spi->controller->mode_bits) & SPI_MODE_X_MASK) { dev_err(&spi->dev, "incompatible CPOL/CPHA, must match controller's Moto= rola mode\n"); return -EINVAL; } --=20 2.50.1 From nobody Mon Dec 1 21:29:59 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D69A302175; Thu, 27 Nov 2025 19:00:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764270039; cv=none; b=gJwJtNXgkEnBtO6TKzX0I33Kb61gc9ZQ2sRy4z9HTkuJGbyeHu+a2uVIv789sl40GCFRN5Sq4s/d0QPGe3gEYcD37DuzNeKTT8d5fQBobUCH4/7ioByY7ixIPNdgoS0MMSAsWmvsKVIlbYMDb/Qe7jG/1ez0Cm4ejw+Zr6qLt0s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764270039; c=relaxed/simple; bh=4lakAawu+tT5I/1TAhrOXAulcIoD9+FM7nbBSisAF7s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=n/wU5l8Y/BgjQ2tY0BDky8FqoDGLJjbceNOwShfxAsDUziAe0RKGxa8JWPi/e5rOP4df+KsqwyMeNLvWfK3urwBg1reqVe9X0RPxToqwngoFDQvzWABUfY8bosa6ZaUS14WagP47Q4ylDnC2W08uwWqLsFnhwCxekR4+wInFjXo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=G9NhiC2w; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="G9NhiC2w" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1764270037; x=1795806037; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4lakAawu+tT5I/1TAhrOXAulcIoD9+FM7nbBSisAF7s=; b=G9NhiC2w69jwsD9lsRL7EfidM9FEm++hAJPZDMjUFFcN8qehlDS2iKZP jblCOaz3GsvQh5Zfd1Cw08y9iKfI6hsK2LI99nsb2VtpjOjuj5NXfOQrs 85fuow/FKSneFuPBs31xJ3bCvCZYZ7FSvS2OVZOG1cfOB956vkMyf2dCO iV/PA/tBLg56tEsAENXkGRmsShqPtNFiGpQRRv7cp1iaHOF+nGL+hAbjz s46GmYRCv7a8jHpaVeqCldOs5CGsm9mY60UnRE/+QDD9QukSrUgrjKWuL f8WStO+vJD77kaxuTwAmCS8Qz+Ri7urYfstDuyqahDbHzrXzAxoip1/W4 w==; X-CSE-ConnectionGUID: JazK1PUASrqaT3/nsbzLZw== X-CSE-MsgGUID: fMJwBSR2TzCiISY9S/dUpA== X-IronPort-AV: E=McAfee;i="6800,10657,11626"; a="66480314" X-IronPort-AV: E=Sophos;i="6.20,231,1758610800"; d="scan'208";a="66480314" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Nov 2025 11:00:36 -0800 X-CSE-ConnectionGUID: Sd+N2V3LQESNTOJcpFdMQg== X-CSE-MsgGUID: 7LHwIba6SpSoQMrMTqeV0A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.20,231,1758610800"; d="scan'208";a="193312329" Received: from black.igk.intel.com ([10.91.253.5]) by orviesa007.jf.intel.com with ESMTP; 27 Nov 2025 11:00:35 -0800 Received: by black.igk.intel.com (Postfix, from userid 1003) id 4E104A5; Thu, 27 Nov 2025 20:00:32 +0100 (CET) From: Andy Shevchenko To: Prajna Rajendra Kumar , Andy Shevchenko , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Brown Subject: [PATCH v3 6/6] spi: microchip-core: Remove unneeded PM related macro Date: Thu, 27 Nov 2025 19:59:03 +0100 Message-ID: <20251127190031.2998705-7-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251127190031.2998705-1-andriy.shevchenko@linux.intel.com> References: <20251127190031.2998705-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Static declaration by default are 0 or NULL, no need to initialise them explicitly. Remove unneeded PM related macro. Reviewed-by: Prajna Rajendra Kumar Signed-off-by: Andy Shevchenko --- drivers/spi/spi-microchip-core-spi.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/spi/spi-microchip-core-spi.c b/drivers/spi/spi-microch= ip-core-spi.c index d37e193e282f..2f4b21ad56a7 100644 --- a/drivers/spi/spi-microchip-core-spi.c +++ b/drivers/spi/spi-microchip-core-spi.c @@ -403,8 +403,6 @@ static void mchp_corespi_remove(struct platform_device = *pdev) mchp_corespi_disable(spi); } =20 -#define MICROCHIP_SPI_PM_OPS (NULL) - /* * Platform driver data structure */ @@ -421,7 +419,6 @@ static struct platform_driver mchp_corespi_driver =3D { .probe =3D mchp_corespi_probe, .driver =3D { .name =3D "microchip-corespi", - .pm =3D MICROCHIP_SPI_PM_OPS, .of_match_table =3D of_match_ptr(mchp_corespi_dt_ids), }, .remove =3D mchp_corespi_remove, --=20 2.50.1