From nobody Mon Dec 1 21:33:23 2025 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E1FD2DF132; Thu, 27 Nov 2025 17:10:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764263454; cv=none; b=PJ3DDC9sfHIL9meZNwe6jULyufZoTjH06Nas3zD+3rcRuLAxAuZayP8Op9xk9SAfBxegzsuYvBQLhj5w8Lag4Fse42VChrigMda2/4Lq+solM6vk2sqzGe4DQJglzMQJlJ/wMWi0jIrweGtDaA3mcoX4N09wCpOhR+KbkcltxCg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764263454; c=relaxed/simple; bh=ShWsDxbS9rMHO4Rz2R/xGxd1y8sow72GpKgcMYmFCGU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Vvvt+QH4b5Gd94nVZlMDDL3b+kg6A2v8HyqIsed3ANU4NQ9ayA0I4u2vASYhgOswPQHu1auE0Ey6lJcCAmWxdiPVl1fr7/0EHTZg1Ai5y53cnf3AuPVLwGv191v3mfZya3wZeYRB/nWtK7z7kqlwoLo7nwAxsrHFee/OrSsZtZM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=HPevv09x; arc=none smtp.client-ip=117.135.210.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="HPevv09x" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=p4 BEwT/W3XQBlce+4mMjg1k8Az7t6B/IA1oEwR7bxT4=; b=HPevv09xcNHbDY2eOg 1Rf/8YCvaecuIRMb7ZFfrihMYAcMaBYOXZftMvF+9CZRbAH9rQ5e69LQa2iM0ESw EMCAV0+/TjKJ343vJmy2vI5MCqzrahW3Of4mWqy3amrcEl/DBj/TpCzVfLA8WzPH m3t96BHgcbyp1bpBnUsaA/xj4= Received: from zhb.. (unknown []) by gzga-smtp-mtada-g1-1 (Coremail) with SMTP id _____wDX71K2hShpkFjfDA--.43603S3; Fri, 28 Nov 2025 01:09:13 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, helgaas@kernel.org, heiko@sntech.de, mani@kernel.org, yue.wang@Amlogic.com Cc: pali@kernel.org, neil.armstrong@linaro.org, robh@kernel.org, jingoohan1@gmail.com, khilman@baylibre.com, jbrunet@baylibre.com, martin.blumenstingl@googlemail.com, cassel@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-rockchip@lists.infradead.org, Hans Zhang <18255117159@163.com>, Mahesh Vaidya , Shawn Lin Subject: [PATCH v7 1/2] PCI: Configure Root Port MPS during host probing Date: Fri, 28 Nov 2025 01:09:07 +0800 Message-Id: <20251127170908.14850-2-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251127170908.14850-1-18255117159@163.com> References: <20251127170908.14850-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDX71K2hShpkFjfDA--.43603S3 X-Coremail-Antispam: 1Uf129KBjvJXoW7WF1DCr43Xr1rAr4DKFy7Awb_yoW8KFyDpa yUWanYyFn7GF43ZanrA3W0vFyYqF93ArW3GrZYv34qvan8AryDJrW7ta95Jwn7GrWI9Fya vFn8try7CasFvF7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0piPCztUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiOh4To2kohTEP5AAAsK Content-Type: text/plain; charset="utf-8" Current PCIe initialization logic may leave Root Ports operating with non-optimal Maximum Payload Size (MPS) settings. The existing code in pci_configure_mps() returns early for devices without an upstream bridge which includes Root Ports, so their MPS values remain at firmware defaults. This fails to utilize the controller's full capabilities, leading to suboptimal data transfer efficiency across the PCIe hierarchy. With this patch, during the host controller probing phase: - When PCIe bus tuning is enabled (not PCIE_BUS_TUNE_OFF) and not PCIE_BUS_PEER2PEER (which requires the default 128 bytes for optimal peer-to-peer operation), and - The device is a Root Port, the Root Port's MPS is set to its maximum supported value. Note that this initial maximum MPS setting may be reduced later, during downstream device enumeration, if any downstream device does not support the Root Port's maximum MPS. This change ensures Root Ports are initialized to their maximum MPS before downstream devices negotiate MPS, while maintaining backward compatibility via the PCIE_BUS_TUNE_OFF check and not interfering with the PCIE_BUS_PEER2PEER strategy. Suggested-by: Niklas Cassel Suggested-by: Manivannan Sadhasivam Signed-off-by: Hans Zhang <18255117159@163.com> Tested-by: Mahesh Vaidya Tested-by: Shawn Lin --- drivers/pci/probe.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 9cd032dff31e..3970d964d868 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2203,6 +2203,18 @@ static void pci_configure_mps(struct pci_dev *dev) return; } =20 + /* + * Unless MPS strategy is PCIE_BUS_TUNE_OFF (don't touch MPS at all) or + * PCIE_BUS_PEER2PEER (use minimum MPS for peer-to-peer), set Root Ports' + * MPS to their maximum supported value. Depending on the MPS strategy + * and MPSS of downstream devices, a Root Port's MPS may be reduced + * later during device enumeration. + */ + if (pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_ROOT_PORT && + pcie_bus_config !=3D PCIE_BUS_TUNE_OFF && + pcie_bus_config !=3D PCIE_BUS_PEER2PEER) + pcie_set_mps(dev, 128 << dev->pcie_mpss); + if (!bridge || !pci_is_pcie(bridge)) return; =20 --=20 2.34.1 From nobody Mon Dec 1 21:33:23 2025 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E3652DECDF; Thu, 27 Nov 2025 17:10:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764263444; cv=none; b=DhCqJn5A8P1XLTttSHz93i2rHhprXq8x/+Hv7tAlDn16G7aiffigELi9v0U9wLWaLAYjwSUMNsCrK3jtxrNCso6u4rF5cmGE50ssxacapPNOIan621Vv7Avy4+YwJ57vkZLXf3jCoXU6Y4+1WKGrLvu8jOOm2IuybQTnfb1/32U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764263444; c=relaxed/simple; bh=xY9EeZNG6327M7qafePF+MG8xDd3VZN9/Xn/tPbQxWA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=g5G9DXuPjAR1szJ436H5uy7WBRm5hf3P+qOj06Pgm163G464EIH4CChKtadvwIFLpJBdj4oWv9N7sqkYB8OW8ALouYBk+nqmKT0cJP9FYW/OFBAKDUxR5azQMtIsLNxHC6vyUWOtAONd/AZthUkAi6hDZGmlGqIJgEDG04uvIOM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=naXGPXJT; arc=none smtp.client-ip=220.197.31.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="naXGPXJT" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=HV 6aCZe858sfDxOrV63v3V1QYYmt0i4YMWexhlJ+tbA=; b=naXGPXJTlIK1unETm8 75auW4gIbvDvDlitwThqx4P2ocxvvockkkT5bjipCrPuGjTEYpbwFqvrOWdvsqMR 0QfNAC5HHfX0HfqXbMBuY8PGxYkGszrk7tQEVF+6KwshWG8XjWUpU7iLHiW70Mw8 lffFtoGlbzjxW66amaFgr3Wgs= Received: from zhb.. (unknown []) by gzga-smtp-mtada-g1-1 (Coremail) with SMTP id _____wDX71K2hShpkFjfDA--.43603S4; Fri, 28 Nov 2025 01:09:14 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, helgaas@kernel.org, heiko@sntech.de, mani@kernel.org, yue.wang@Amlogic.com Cc: pali@kernel.org, neil.armstrong@linaro.org, robh@kernel.org, jingoohan1@gmail.com, khilman@baylibre.com, jbrunet@baylibre.com, martin.blumenstingl@googlemail.com, cassel@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-rockchip@lists.infradead.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v7 2/2] PCI: dwc: Remove redundant MPS configuration Date: Fri, 28 Nov 2025 01:09:08 +0800 Message-Id: <20251127170908.14850-3-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251127170908.14850-1-18255117159@163.com> References: <20251127170908.14850-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDX71K2hShpkFjfDA--.43603S4 X-Coremail-Antispam: 1Uf129KBjvJXoW7KF4xuw4xXFWDJw43WF4xtFb_yoW8Cr1fpF y3WrsakF18Ar45WF4qkan5Cay3tasxCry7JF9Ig34fZFyayFsrJa4ayFWFka4xWrW293WS kr98K3y8A3W5trUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pE1vVXUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCxBrzl2kohboRnwAA3K Content-Type: text/plain; charset="utf-8" The Meson PCIe controller driver manually configures maximum payload size (MPS) through meson_set_max_payload, duplicating functionality now centralized in the PCI core. Deprecating redundant code simplifies the driver and aligns it with the consolidated MPS management strategy, improving long-term maintainability. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pci-meson.c | 17 ----------------- 1 file changed, 17 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controlle= r/dwc/pci-meson.c index 787469d1b396..3d12e1a9bb0c 100644 --- a/drivers/pci/controller/dwc/pci-meson.c +++ b/drivers/pci/controller/dwc/pci-meson.c @@ -261,22 +261,6 @@ static int meson_size_to_payload(struct meson_pcie *mp= , int size) return fls(size) - 8; } =20 -static void meson_set_max_payload(struct meson_pcie *mp, int size) -{ - struct dw_pcie *pci =3D &mp->pci; - u32 val; - u16 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - int max_payload_size =3D meson_size_to_payload(mp, size); - - val =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL); - val &=3D ~PCI_EXP_DEVCTL_PAYLOAD; - dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val); - - val =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL); - val |=3D PCIE_CAP_MAX_PAYLOAD_SIZE(max_payload_size); - dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val); -} - static void meson_set_max_rd_req_size(struct meson_pcie *mp, int size) { struct dw_pcie *pci =3D &mp->pci; @@ -381,7 +365,6 @@ static int meson_pcie_host_init(struct dw_pcie_rp *pp) =20 pp->bridge->ops =3D &meson_pci_ops; =20 - meson_set_max_payload(mp, MAX_PAYLOAD_SIZE); meson_set_max_rd_req_size(mp, MAX_READ_REQ_SIZE); =20 return 0; --=20 2.34.1