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Thu, 27 Nov 2025 06:12:42 -0800 (PST) Received: from J9GPGXL7NT.bytedance.net ([61.213.176.58]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3477b7341d2sm2030249a91.11.2025.11.27.06.12.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 27 Nov 2025 06:12:42 -0800 (PST) From: Xu Lu To: pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, kees@kernel.org, mingo@redhat.com, peterz@infradead.org, juri.lelli@redhat.com, vincent.guittot@linaro.org, akpm@linux-foundation.org, david@redhat.com, apatel@ventanamicro.com, guoren@kernel.org Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, Xu Lu Subject: [RFC PATCH v2 7/9] riscv: mm: Defer the TLB Flush to switch_mm Date: Thu, 27 Nov 2025 22:11:15 +0800 Message-ID: <20251127141117.87420-8-luxu.kernel@bytedance.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251127141117.87420-1-luxu.kernel@bytedance.com> References: <20251127141117.87420-1-luxu.kernel@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since the TLB Flush IPI is avoided when the modified mm is not running on the target CPU, next time when target CPU switches to the modified mm, it has to check percpu TLB Flush queue and perform TLB FLush for the midified mm. Signed-off-by: Xu Lu --- arch/riscv/mm/tlbflush.c | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index b5a2d9874d62b..0083fac87c2bc 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -365,8 +365,10 @@ void local_load_tlb_mm(struct mm_struct *mm) { struct tlb_info *info =3D this_cpu_ptr(&tlbinfo); struct tlb_context *contexts =3D info->contexts; + struct tlb_flush_queue *queue =3D NULL; struct mm_struct *victim =3D NULL; - unsigned int i, pos =3D 0, min =3D UINT_MAX; + unsigned int i, len, pos =3D 0, min =3D UINT_MAX; + unsigned long asid, start, size, stride; =20 for (i =3D 0; i < MAX_LOADED_MM; i++) { if (contexts[i].mm =3D=3D mm) { @@ -387,11 +389,36 @@ void local_load_tlb_mm(struct mm_struct *mm) mmgrab_lazy_mm(mm); victim =3D contexts[pos].mm; contexts[pos].mm =3D mm; + contexts[pos].need_flush =3D false; + + queue =3D &info->flush_queues[pos]; + atomic_set(&queue->len, 0); + queue->flag =3D 0; } contexts[pos].gen =3D new_tlb_gen(info); =20 write_unlock(&info->rwlock); =20 + if (contexts[pos].need_flush) { + queue =3D &info->flush_queues[pos]; + asid =3D get_mm_asid(mm); + if (queue->flag & FLUSH_TLB_ALL_ASID) { + local_flush_tlb_all_asid(asid); + } else { + len =3D atomic_read(&queue->len); + for (i =3D 0; i < len; i++) { + start =3D queue->tasks[i].start; + size =3D queue->tasks[i].size; + stride =3D queue->tasks[i].stride; + local_flush_tlb_range_asid(start, size, + stride, asid); + } + } + contexts[pos].need_flush =3D false; + atomic_set(&queue->len, 0); + queue->flag =3D 0; + } + if (victim) { cpumask_clear_cpu(raw_smp_processor_id(), mm_cpumask(victim)); local_flush_tlb_all_asid(get_mm_asid(victim)); --=20 2.20.1