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Thu, 27 Nov 2025 06:11:44 -0800 (PST) Received: from J9GPGXL7NT.bytedance.net ([61.213.176.58]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3477b7341d2sm2030249a91.11.2025.11.27.06.11.39 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 27 Nov 2025 06:11:44 -0800 (PST) From: Xu Lu To: pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, kees@kernel.org, mingo@redhat.com, peterz@infradead.org, juri.lelli@redhat.com, vincent.guittot@linaro.org, akpm@linux-foundation.org, david@redhat.com, apatel@ventanamicro.com, guoren@kernel.org Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, Xu Lu Subject: [RFC PATCH v2 1/9] riscv: Introduce RISCV_LAZY_TLB_FLUSH config Date: Thu, 27 Nov 2025 22:11:09 +0800 Message-ID: <20251127141117.87420-2-luxu.kernel@bytedance.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251127141117.87420-1-luxu.kernel@bytedance.com> References: <20251127141117.87420-1-luxu.kernel@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This feature avoids unnecessary TLB Flush IPIs. After memory mapping modifications on certain mm_struct, instead of sending IPIs, this feature records the TLB Flush information on percpu buffer, defer the TLB Flush to the moment when target CPUs really load this mm_struct. Signed-off-by: Xu Lu --- arch/riscv/Kconfig | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 22cda9c452d2a..d219c7f4b129e 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -925,6 +925,18 @@ config RISCV_VECTOR_MISALIGNED help Enable detecting support for vector misaligned loads and stores. =20 +config RISCV_LAZY_TLB_FLUSH + bool "Defer TLB Flush to context switch to avoid IPIs" + depends on MMU && SMP + def_bool n + help + This feature avoids unnecessary TLB Flush IPIs. After memory mapping + modifications on certain mm_struct, instead of sending IPIs, this featu= re + records the TLB Flush information on percpu buffer, defer the TLB Flush + to the moment when target CPUs really load this mm_struct. + + If unsure what to do here, say N. + choice prompt "Unaligned Accesses Support" default RISCV_PROBE_UNALIGNED_ACCESS --=20 2.20.1