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Thu, 27 Nov 2025 04:53:59 -0800 (PST) From: Yunhui Cui To: conor@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, cuiyunhui@bytedance.com, luxu.kernel@bytedance.com, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, jassisinghbrar@gmail.com, conor.dooley@microchip.com, valentina.fernandezalanis@microchip.com, catalin.marinas@arm.com, will@kernel.org, maz@kernel.org, timothy.hayes@arm.com, lpieralisi@kernel.org, arnd@arndb.de, kees@kernel.org, tglx@linutronix.de, viresh.kumar@linaro.org, boqun.feng@gmail.com, linux-arm-kernel@lists.infradead.org, cleger@rivosinc.com, atishp@rivosinc.com, ajones@ventanamicro.com Subject: [PATCH v3 5/8] riscv: smp: use NMI for CPU stop Date: Thu, 27 Nov 2025 20:53:02 +0800 Message-Id: <20251127125305.89961-6-cuiyunhui@bytedance.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20251127125305.89961-1-cuiyunhui@bytedance.com> References: <20251127125305.89961-1-cuiyunhui@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use NMI instead of IPI for CPU stop if RISC-V SSE NMI is supported. Signed-off-by: Yunhui Cui --- arch/riscv/include/asm/smp.h | 2 ++ arch/riscv/kernel/smp.c | 10 +++++++--- drivers/firmware/riscv/riscv_sse_nmi.c | 1 + 3 files changed, 10 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h index f53f1f0e7aa9e..e01ea962adfc4 100644 --- a/arch/riscv/include/asm/smp.h +++ b/arch/riscv/include/asm/smp.h @@ -63,6 +63,8 @@ static inline void cpu_crash_stop(unsigned int cpu, struc= t pt_regs *regs) } #endif =20 +void cpu_stop(void); + /* Secondary hart entry */ asmlinkage void smp_callin(void); =20 diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index 1b8cf986abbd0..bca95ec0b0f74 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -69,7 +69,7 @@ int riscv_hartid_to_cpuid(unsigned long hartid) return -ENOENT; } =20 -static void ipi_stop(void) +void cpu_stop(void) { set_cpu_online(smp_processor_id(), false); while (1) @@ -127,7 +127,7 @@ static irqreturn_t handle_IPI(int irq, void *data) generic_smp_call_function_interrupt(); break; case IPI_CPU_STOP: - ipi_stop(); + cpu_stop(); break; case IPI_CPU_CRASH_STOP: cpu_crash_stop(cpu, get_irq_regs()); @@ -259,7 +259,11 @@ void smp_send_stop(void) =20 if (system_state <=3D SYSTEM_RUNNING) pr_crit("SMP: stopping secondary CPUs\n"); - send_ipi_mask(&mask, IPI_CPU_STOP); + + if (!nmi_support()) + send_ipi_mask(&mask, IPI_CPU_STOP); + else + send_nmi_mask(&mask, LOCAL_NMI_CRASH); } =20 /* Wait up to one second for other CPUs to stop */ diff --git a/drivers/firmware/riscv/riscv_sse_nmi.c b/drivers/firmware/risc= v/riscv_sse_nmi.c index add028efd25a0..02e2de2bb70f7 100644 --- a/drivers/firmware/riscv/riscv_sse_nmi.c +++ b/drivers/firmware/riscv/riscv_sse_nmi.c @@ -58,6 +58,7 @@ static int local_nmi_handler(u32 evt, void *arg, struct p= t_regs *regs) type =3D atomic_read(this_cpu_ptr(&local_nmi)); =20 NMI_HANDLE(LOCAL_NMI_CRASH, cpu_crash_stop, cpu, regs); + NMI_HANDLE(LOCAL_NMI_STOP, cpu_stop); =20 atomic_andnot(type, this_cpu_ptr(&local_nmi)); =20 --=20 2.39.5