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Thu, 27 Nov 2025 04:53:51 -0800 (PST) From: Yunhui Cui To: conor@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, cuiyunhui@bytedance.com, luxu.kernel@bytedance.com, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, jassisinghbrar@gmail.com, conor.dooley@microchip.com, valentina.fernandezalanis@microchip.com, catalin.marinas@arm.com, will@kernel.org, maz@kernel.org, timothy.hayes@arm.com, lpieralisi@kernel.org, arnd@arndb.de, kees@kernel.org, tglx@linutronix.de, viresh.kumar@linaro.org, boqun.feng@gmail.com, linux-arm-kernel@lists.infradead.org, cleger@rivosinc.com, atishp@rivosinc.com, ajones@ventanamicro.com Subject: [PATCH v3 4/8] riscv: smp: use NMI for crash stop Date: Thu, 27 Nov 2025 20:53:01 +0800 Message-Id: <20251127125305.89961-5-cuiyunhui@bytedance.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20251127125305.89961-1-cuiyunhui@bytedance.com> References: <20251127125305.89961-1-cuiyunhui@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use NMI instead of IPI for crash stop if RISC-V SSE NMI is supported. Signed-off-by: Yunhui Cui --- arch/riscv/kernel/smp.c | 11 ++++++++++- drivers/firmware/riscv/riscv_sse_nmi.c | 12 ++++++++++++ 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index 669325e68a21a..1b8cf986abbd0 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -300,7 +301,15 @@ void crash_smp_send_stop(void) atomic_set(&waiting_for_crash_ipi, num_other_online_cpus()); =20 pr_crit("SMP: stopping secondary CPUs\n"); - send_ipi_mask(&mask, IPI_CPU_CRASH_STOP); + + /* + * Not a high frequency operation and is in final state, directly use + * NMI instead of IPI to ensure reliability. + */ + if (!nmi_support()) + send_ipi_mask(&mask, IPI_CPU_CRASH_STOP); + else + send_nmi_mask(&mask, LOCAL_NMI_CRASH); =20 /* Wait up to one second for other CPUs to stop */ timeout =3D USEC_PER_SEC; diff --git a/drivers/firmware/riscv/riscv_sse_nmi.c b/drivers/firmware/risc= v/riscv_sse_nmi.c index 752ee88b230da..add028efd25a0 100644 --- a/drivers/firmware/riscv/riscv_sse_nmi.c +++ b/drivers/firmware/riscv/riscv_sse_nmi.c @@ -10,6 +10,9 @@ #include #include =20 +#define NMI_HANDLE(mask, func, ...) \ + do { if (type & (mask)) func(__VA_ARGS__); } while (0) + static bool nmi_available; static struct sse_event *local_nmi_evt; static DEFINE_PER_CPU(atomic_t, local_nmi) =3D ATOMIC_INIT(LOCAL_NMI_NONE); @@ -49,6 +52,15 @@ void send_nmi_mask(cpumask_t *mask, enum local_nmi_type = type) =20 static int local_nmi_handler(u32 evt, void *arg, struct pt_regs *regs) { + enum local_nmi_type type; + unsigned int cpu =3D smp_processor_id(); + + type =3D atomic_read(this_cpu_ptr(&local_nmi)); + + NMI_HANDLE(LOCAL_NMI_CRASH, cpu_crash_stop, cpu, regs); + + atomic_andnot(type, this_cpu_ptr(&local_nmi)); + return 0; } =20 --=20 2.39.5