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Thu, 27 Nov 2025 04:46:46 -0800 (PST) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7d150b66c67sm1951332b3a.13.2025.11.27.04.46.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Nov 2025 04:46:45 -0800 (PST) From: Krishna Chaitanya Chundru Date: Thu, 27 Nov 2025 18:15:43 +0530 Subject: [PATCH v6 2/2] PCI: Add support for PCIe WAKE# interrupt Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251127-wakeirq_support-v6-2-60f581f94205@oss.qualcomm.com> References: <20251127-wakeirq_support-v6-0-60f581f94205@oss.qualcomm.com> In-Reply-To: <20251127-wakeirq_support-v6-0-60f581f94205@oss.qualcomm.com> To: "Rafael J. Wysocki" , Len Brown , Pavel Machek , Greg Kroah-Hartman , Danilo Krummrich , Bjorn Helgaas , Linus Walleij , Bartosz Golaszewski Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-gpio@vger.kernel.org, quic_vbadigan@quicinc.com, quic_mrana@quicinc.com, sherry.sun@nxp.com, Krishna Chaitanya Chundru X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764247587; l=6954; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=QTar8G3HPjr2G/dTy3IURU1yuHkDZrUw3M3E2StJypg=; b=w5MlLSN1DG4j/i2NshPA5/Q6fEhjH2QktTkwS8fSDvBAeUV0M/i/iFtg7/ypUGeawDM9PsVub F544A/LclZFCYeh5P5ZdLBdVQ2DBnOyrev1SCIKa7YuxI5P11oFRPXc X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-ORIG-GUID: CAnO3RGjxuFgNcGXB5G6aQIFvHPhnt2Q X-Authority-Analysis: v=2.4 cv=QOplhwLL c=1 sm=1 tr=0 ts=6928483a cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=NEAV23lmAAAA:8 a=KKAkSRfTAAAA:8 a=MM5MBmnPbV1rJZqCYTkA:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTI3MDA5NCBTYWx0ZWRfX+PsUflJr2UCY 5PJ491j3ri3m7pvplJUUwcASZSZglPUAVIOQMHYS5tEkSShcYflK5MJj36p2uJukaBIS71jmazA DkCRJh67gQoRAeWxqeMpzE6SQNc14iYQmX1EXI2Xk03o5ocmbpudy7C1K9nVrNNcYJbOjxm8bHN 0/qsDCAuoEeN7BsYbPmzrheP9I+vDZV9oDbQgVoiRLHci+IqZdaMcryYHwvsDEh4VPpKzUWgCkm RtgRGHtVlu1gyThd1adljtkIWQeJ+DouvsABpWnl5eG+6lG1INQ1enDwOgtRWh1zss0jYcHMhRE YObppK8Dc4+oyAU9iqjqRNcA/qmdQpUZ0bmlfDwa2dugUagbyWfnY23QSpdra0alr+gN0FVDzL4 QJZsh3TQtx6ugL9bQ3Bh2nSkVvQShA== X-Proofpoint-GUID: CAnO3RGjxuFgNcGXB5G6aQIFvHPhnt2Q X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-25_02,2025-11-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 phishscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511270094 According to the PCIe specification 6, sec 5.3.3.2, there are two defined wakeup mechanisms: Beacon and WAKE# for the Link wakeup mechanisms to provide a means of signaling the platform to re-establish power and reference clocks to the components within its domain. Beacon is a hardware mechanism invisible to software (PCIe r7.0, sec 4.2.7.8.1). Adding WAKE# support in PCI framework. According to the PCIe specification, multiple WAKE# signals can exist in a system. In configurations involving a PCIe switch, each downstream port (DSP) of the switch may be connected to a separate WAKE# line, allowing each endpoint to signal WAKE# independently. From figure 5.4, WAKE# can also be terminated at the switch itself. To support this, the WAKE# should be described in the device tree node of the endpint/bridge. If all endpoints share a single WAKE# line, then WAKE# should be defined in the each node. To support legacy devicetree in direct attach case, driver will search in root port node for WAKE# if the driver doesn't find in the endpoint node. In pci_device_add(), PCI framework will search for the WAKE# in its node, If not found, it searches in its upstream port only if upstream port is root port to support legacy bindings. Once found, register for the wake IRQ in shared mode, as the WAKE# may be shared among multiple endpoints. When the IRQ is asserted, the handle_threaded_wake_irq() handler triggers a pm_runtime_resume(). The PM framework ensures that the parent device is resumed before the child i.e controller driver which can bring back device state to D0. WAKE# is added in dts schema and merged based on below links. Link: https://lore.kernel.org/all/20250515090517.3506772-1-krishna.chundru@= oss.qualcomm.com/ Link: https://github.com/devicetree-org/dt-schema/pull/170 Reviewed-by: Linus Walleij Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/of.c | 58 ++++++++++++++++++++++++++++++++++++++++++++++++= ++++ drivers/pci/pci.h | 6 ++++++ drivers/pci/probe.c | 2 ++ drivers/pci/remove.c | 1 + include/linux/pci.h | 2 ++ 5 files changed, 69 insertions(+) diff --git a/drivers/pci/of.c b/drivers/pci/of.c index 3579265f119845637e163d9051437c89662762f8..fc33405a7b1f001e17127743466= 3cc9dfe57c69b 100644 --- a/drivers/pci/of.c +++ b/drivers/pci/of.c @@ -7,6 +7,7 @@ #define pr_fmt(fmt) "PCI: OF: " fmt =20 #include +#include #include #include #include @@ -15,6 +16,7 @@ #include #include #include +#include #include "pci.h" =20 #ifdef CONFIG_PCI @@ -586,6 +588,62 @@ int of_irq_parse_and_map_pci(const struct pci_dev *dev= , u8 slot, u8 pin) return irq_create_of_mapping(&oirq); } EXPORT_SYMBOL_GPL(of_irq_parse_and_map_pci); + +static void pci_configure_wake_irq(struct pci_dev *pdev, struct gpio_desc = *wake) +{ + int ret, wake_irq; + + if (!wake) + return; + + wake_irq =3D gpiod_to_irq(wake); + if (wake_irq < 0) { + dev_err(&pdev->dev, "Failed to get wake irq: %d\n", wake_irq); + return; + } + + device_init_wakeup(&pdev->dev, true); + + ret =3D dev_pm_set_dedicated_shared_wake_irq(&pdev->dev, wake_irq, + IRQ_TYPE_EDGE_FALLING); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to set wake IRQ: %d\n", ret); + device_init_wakeup(&pdev->dev, false); + } +} + +void pci_configure_of_wake_gpio(struct pci_dev *dev) +{ + struct device_node *dn =3D pci_device_to_OF_node(dev); + struct gpio_desc *gpio; + struct pci_dev *root; + + if (!dn) + return; + + gpio =3D fwnode_gpiod_get_index(of_fwnode_handle(dn), + "wake", 0, GPIOD_IN | GPIOD_FLAGS_BIT_NONEXCLUSIVE, NULL); + if (IS_ERR(gpio)) { + /* + * To support legacy devicetree, search in root port for WAKE# + * in direct attach case. + */ + root =3D pci_upstream_bridge(dev); + if (pci_is_root_bus(root->bus)) + pci_configure_wake_irq(dev, root->wake); + } else { + dev->wake =3D gpio; + pci_configure_wake_irq(dev, gpio); + } +} + +void pci_remove_of_wake_gpio(struct pci_dev *dev) +{ + dev_pm_clear_wake_irq(&dev->dev); + device_init_wakeup(&dev->dev, false); + gpiod_put(dev->wake); + dev->wake =3D NULL; +} #endif /* CONFIG_OF_IRQ */ =20 static int pci_parse_request_of_pci_ranges(struct device *dev, diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 4492b809094b5794bd94dfbc20102cb208c3fa2f..05cb240ecdb59f9833ca6dae235= 7fdbd012195d6 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -1056,6 +1056,9 @@ void pci_release_of_node(struct pci_dev *dev); void pci_set_bus_of_node(struct pci_bus *bus); void pci_release_bus_of_node(struct pci_bus *bus); =20 +void pci_configure_of_wake_gpio(struct pci_dev *dev); +void pci_remove_of_wake_gpio(struct pci_dev *dev); + int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *br= idge); bool of_pci_supply_present(struct device_node *np); int of_pci_get_equalization_presets(struct device *dev, @@ -1101,6 +1104,9 @@ static inline int devm_of_pci_bridge_init(struct devi= ce *dev, struct pci_host_br return 0; } =20 +static inline void pci_configure_of_wake_gpio(struct pci_dev *dev) { } +static inline void pci_remove_of_wake_gpio(struct pci_dev *dev) { } + static inline bool of_pci_supply_present(struct device_node *np) { return false; diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 0ce98e18b5a876afe72af35a9f4a44d598e8d500..f9b879c8e3f72a9845f60577335= 019aa2002dc23 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2762,6 +2762,8 @@ void pci_device_add(struct pci_dev *dev, struct pci_b= us *bus) ret =3D device_add(&dev->dev); WARN_ON(ret < 0); =20 + pci_configure_of_wake_gpio(dev); + pci_npem_create(dev); =20 pci_doe_sysfs_init(dev); diff --git a/drivers/pci/remove.c b/drivers/pci/remove.c index ce5c25adef5518e5aec30c41de37ea66d682f3b0..26e9c1df51c76344a1d7f5cc7ed= d433780e73474 100644 --- a/drivers/pci/remove.c +++ b/drivers/pci/remove.c @@ -54,6 +54,7 @@ static void pci_destroy_dev(struct pci_dev *dev) if (pci_dev_test_and_set_removed(dev)) return; =20 + pci_remove_of_wake_gpio(dev); pci_doe_sysfs_teardown(dev); pci_npem_remove(dev); =20 diff --git a/include/linux/pci.h b/include/linux/pci.h index d1fdf81fbe1e427aecbc951fa3fdf65c20450b05..cd7b5eb82a430ead2f64d903a24= a5b06a1b7b17e 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -555,6 +555,8 @@ struct pci_dev { /* These methods index pci_reset_fn_methods[] */ u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */ =20 + struct gpio_desc *wake; /* Holds WAKE# gpio */ + #ifdef CONFIG_PCIE_TPH u16 tph_cap; /* TPH capability offset */ u8 tph_mode; /* TPH mode */ --=20 2.34.1