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PM OPP is used to abstract these resources in firmware and SCMI perf protocol is used to request resource operations by using runtime PM framework APIs such as pm_runtime_get/put_sync to signal firmware for managing resources accordingly for respective perf levels. "qcom,snps-dwc3-fw-managed" compatible helps determine if the device's resources are managed by firmware. Additionally, it makes the power-domains property mandatory and excludes the clocks property for the controller. Signed-off-by: Sriram Dash --- .../devicetree/bindings/usb/qcom,snps-dwc3.yaml | 173 +++++++++++++----= ---- 1 file changed, 111 insertions(+), 62 deletions(-) diff --git a/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml b/Do= cumentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml index 8cee7c5582f2..d2d1b42fbb07 100644 --- a/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml @@ -12,68 +12,65 @@ maintainers: description: Describes the Qualcomm USB block, based on Synopsys DWC3. =20 -select: - properties: - compatible: - contains: - const: qcom,snps-dwc3 - required: - - compatible - properties: compatible: - items: - - enum: - - qcom,glymur-dwc3 - - qcom,glymur-dwc3-mp - - qcom,ipq4019-dwc3 - - qcom,ipq5018-dwc3 - - qcom,ipq5332-dwc3 - - qcom,ipq5424-dwc3 - - qcom,ipq6018-dwc3 - - qcom,ipq8064-dwc3 - - qcom,ipq8074-dwc3 - - qcom,ipq9574-dwc3 - - qcom,kaanapali-dwc3 - - qcom,milos-dwc3 - - qcom,msm8953-dwc3 - - qcom,msm8994-dwc3 - - qcom,msm8996-dwc3 - - qcom,msm8998-dwc3 - - qcom,qcm2290-dwc3 - - qcom,qcs404-dwc3 - - qcom,qcs615-dwc3 - - qcom,qcs8300-dwc3 - - qcom,qdu1000-dwc3 - - qcom,sa8775p-dwc3 - - qcom,sar2130p-dwc3 - - qcom,sc7180-dwc3 - - qcom,sc7280-dwc3 - - qcom,sc8180x-dwc3 - - qcom,sc8180x-dwc3-mp - - qcom,sc8280xp-dwc3 - - qcom,sc8280xp-dwc3-mp - - qcom,sdm660-dwc3 - - qcom,sdm670-dwc3 - - qcom,sdm845-dwc3 - - qcom,sdx55-dwc3 - - qcom,sdx65-dwc3 - - qcom,sdx75-dwc3 - - qcom,sm4250-dwc3 - - qcom,sm6115-dwc3 - - qcom,sm6125-dwc3 - - qcom,sm6350-dwc3 - - qcom,sm6375-dwc3 - - qcom,sm8150-dwc3 - - qcom,sm8250-dwc3 - - qcom,sm8350-dwc3 - - qcom,sm8450-dwc3 - - qcom,sm8550-dwc3 - - qcom,sm8650-dwc3 - - qcom,sm8750-dwc3 - - qcom,x1e80100-dwc3 - - qcom,x1e80100-dwc3-mp - - const: qcom,snps-dwc3 + oneOf: + - items: + - enum: + - qcom,glymur-dwc3 + - qcom,glymur-dwc3-mp + - qcom,ipq4019-dwc3 + - qcom,ipq5018-dwc3 + - qcom,ipq5332-dwc3 + - qcom,ipq5424-dwc3 + - qcom,ipq6018-dwc3 + - qcom,ipq8064-dwc3 + - qcom,ipq8074-dwc3 + - qcom,ipq9574-dwc3 + - qcom,kaanapali-dwc3 + - qcom,milos-dwc3 + - qcom,msm8953-dwc3 + - qcom,msm8994-dwc3 + - qcom,msm8996-dwc3 + - qcom,msm8998-dwc3 + - qcom,qcm2290-dwc3 + - qcom,qcs404-dwc3 + - qcom,qcs615-dwc3 + - qcom,qcs8300-dwc3 + - qcom,qdu1000-dwc3 + - qcom,sa8775p-dwc3 + - qcom,sar2130p-dwc3 + - qcom,sc7180-dwc3 + - qcom,sc7280-dwc3 + - qcom,sc8180x-dwc3 + - qcom,sc8180x-dwc3-mp + - qcom,sc8280xp-dwc3 + - qcom,sc8280xp-dwc3-mp + - qcom,sdm660-dwc3 + - qcom,sdm670-dwc3 + - qcom,sdm845-dwc3 + - qcom,sdx55-dwc3 + - qcom,sdx65-dwc3 + - qcom,sdx75-dwc3 + - qcom,sm4250-dwc3 + - qcom,sm6115-dwc3 + - qcom,sm6125-dwc3 + - qcom,sm6350-dwc3 + - qcom,sm6375-dwc3 + - qcom,sm8150-dwc3 + - qcom,sm8250-dwc3 + - qcom,sm8350-dwc3 + - qcom,sm8450-dwc3 + - qcom,sm8550-dwc3 + - qcom,sm8650-dwc3 + - qcom,sm8750-dwc3 + - qcom,x1e80100-dwc3 + - qcom,x1e80100-dwc3-mp + - const: qcom,snps-dwc3 + - items: + - enum: + - qcom,sa8255p-dwc3 + - const: qcom,snps-dwc3-fw-managed =20 reg: maxItems: 1 @@ -158,13 +155,31 @@ properties: required: - compatible - reg - - clocks - - clock-names - interrupts - interrupt-names =20 allOf: - $ref: snps,dwc3-common.yaml# + + - if: + properties: + compatible: + contains: + const: qcom,snps-dwc3 + then: + required: + - clocks + - clock-names + + - if: + properties: + compatible: + contains: + const: qcom,snps-dwc3-fw-managed + then: + required: + - power-domains + - if: properties: compatible: @@ -513,6 +528,7 @@ allOf: - qcom,qcs615-dwc3 - qcom,qcs8300-dwc3 - qcom,qdu1000-dwc3 + - qcom,sa8255p-dwc3 - qcom,sa8775p-dwc3 - qcom,sc7180-dwc3 - qcom,sc7280-dwc3 @@ -657,4 +673,37 @@ examples: phy-names =3D "usb2-phy", "usb3-phy"; }; }; + - | + #include + #include + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + usb@a600000 { + compatible =3D "qcom,sa8255p-dwc3", "qcom,snps-dwc3-fw-managed= "; + reg =3D <0x0 0x0a800000 0x0 0x10000>; + + interrupts-extended =3D <&intc GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH= >, + <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 8 IRQ_TYPE_EDGE_BOTH>, + <&pdc 7 IRQ_TYPE_EDGE_BOTH>, + <&pdc 13 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "dwc_usb3", + "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + power-domains =3D <&scmi1_dvfs 0>; + + iommus =3D <&apps_smmu 0x0a0 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys =3D <&usb_1_hsphy>, <&usb_1_qmpphy>; + phy-names =3D "usb2-phy", "usb3-phy"; + }; + }; ... --=20 2.34.1 From nobody Mon Dec 1 22:07:40 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C7CE532C937 for ; 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On platforms like sa8255p, where controller resources are abstracted and managed collectively by firmware, the driver communicates power management transitions using dedicated resource state levels via dev_pm_opp_set_level(). Macros are introduced to represent key lifecycle events: initialization, system and runtime suspend/resume, and exit. The driver sets the appropriate resource state during probe, remove, suspend, and resume operations, enabling bulk ON/OFF transitions of grouped resources according to the controller's operational state. Signed-off-by: Sriram Dash Co-developed-by: Shazad Hussain Signed-off-by: Shazad Hussain --- drivers/usb/dwc3/dwc3-qcom.c | 97 ++++++++++++++++++++++++++++++++++++++++= ---- 1 file changed, 88 insertions(+), 9 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c index 9ac75547820d..9615ca6cfcae 100644 --- a/drivers/usb/dwc3/dwc3-qcom.c +++ b/drivers/usb/dwc3/dwc3-qcom.c @@ -13,6 +13,8 @@ #include #include #include +#include +#include #include #include #include @@ -85,10 +87,48 @@ struct dwc3_qcom { struct icc_path *icc_path_apps; =20 enum usb_role current_role; + bool fw_managed; }; =20 #define to_dwc3_qcom(d) container_of((d), struct dwc3_qcom, dwc) =20 +/* + * QCOM DWC3 USB Controller: Firmware-Managed Resource State Levels + * + * On select Qualcomm platforms, the USB controller=E2=80=99s power-related + * resources including GDSC, reset lines, clocks, and interconnects + * are managed collectively by system firmware via SCMI. The driver + * signals the controller=E2=80=99s operational state to firmware using th= ese + * levels, each mapped to a specific power management transition or + * lifecycle event: + * + * DWC3_QCOM_FW_MANAGED_INIT + * Enable GDSC, Assert and Deassert Resets, and turn ON all clocks + * and interconnects. + * + * DWC3_QCOM_FW_MANAGED_SYSTEM_RESUME + * Enable GDSC and turn ON all clocks and interconnects. + * + * DWC3_QCOM_FW_MANAGED_RUNTIME_RESUME + * Turn ON all clocks and interconnects. + * + * DWC3_QCOM_FW_MANAGED_EXIT + * Turn OFF all clocks and interconnects, Assert reset and disable GDSC. + * + * DWC3_QCOM_FW_MANAGED_SYSTEM_SUSPEND + * Turn OFF all clocks and interconnects and disable GDSC. + * + * DWC3_QCOM_FW_MANAGED_RUNTIME_SUSPEND + * Turn OFF clocks and interconnects. + */ + +#define DWC3_QCOM_FW_MANAGED_INIT 1 +#define DWC3_QCOM_FW_MANAGED_SYSTEM_RESUME 2 +#define DWC3_QCOM_FW_MANAGED_RUNTIME_RESUME 3 +#define DWC3_QCOM_FW_MANAGED_EXIT 8 +#define DWC3_QCOM_FW_MANAGED_SYSTEM_SUSPEND 9 +#define DWC3_QCOM_FW_MANAGED_RUNTIME_SUSPEND 10 + static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 v= al) { u32 reg; @@ -335,7 +375,7 @@ static void dwc3_qcom_enable_interrupts(struct dwc3_qco= m *qcom) dwc3_qcom_enable_port_interrupts(&qcom->ports[i]); } =20 -static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup) +static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup, pm_messa= ge_t msg) { u32 val; int i, ret; @@ -348,6 +388,13 @@ static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, b= ool wakeup) if (!(val & PWR_EVNT_LPM_IN_L2_MASK)) dev_err(qcom->dev, "port-%d HS-PHY not in L2\n", i + 1); } + if (qcom->fw_managed) { + if (PMSG_IS_AUTO(msg)) + dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_RUNTIME_SUSPEND); + else + dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_SYSTEM_SUSPEND); + } + clk_bulk_disable_unprepare(qcom->num_clocks, qcom->clks); =20 ret =3D dwc3_qcom_interconnect_disable(qcom); @@ -369,7 +416,7 @@ static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bo= ol wakeup) return 0; } =20 -static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup) +static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup, pm_messag= e_t msg) { int ret; int i; @@ -380,6 +427,18 @@ static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bo= ol wakeup) if (dwc3_qcom_is_host(qcom) && wakeup) dwc3_qcom_disable_interrupts(qcom); =20 + if (qcom->fw_managed) { + if (PMSG_IS_AUTO(msg)) + ret =3D dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_RUNTIME_RE= SUME); + else + ret =3D dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_SYSTEM_RES= UME); + + if (ret < 0) { + dev_err(qcom->dev, "Failed to Resume fw managed device\n"); + return ret; + } + } + ret =3D clk_bulk_prepare_enable(qcom->num_clocks, qcom->clks); if (ret < 0) return ret; @@ -624,10 +683,18 @@ static int dwc3_qcom_probe(struct platform_device *pd= ev) =20 qcom->dev =3D &pdev->dev; =20 + qcom->fw_managed =3D device_get_match_data(dev); + if (qcom->fw_managed) { + ret =3D dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_INIT); + if (ret < 0) + return ret; + } + qcom->resets =3D devm_reset_control_array_get_optional_exclusive(dev); if (IS_ERR(qcom->resets)) { - return dev_err_probe(&pdev->dev, PTR_ERR(qcom->resets), - "failed to get resets\n"); + dev_err_probe(&pdev->dev, PTR_ERR(qcom->resets), + "failed to get resets\n"); + goto resources_off; } =20 ret =3D devm_clk_bulk_get_all(&pdev->dev, &qcom->clks); @@ -638,7 +705,7 @@ static int dwc3_qcom_probe(struct platform_device *pdev) ret =3D reset_control_assert(qcom->resets); if (ret) { dev_err(&pdev->dev, "failed to assert resets, err=3D%d\n", ret); - return ret; + goto resources_off; } =20 usleep_range(10, 1000); @@ -727,6 +794,10 @@ static int dwc3_qcom_probe(struct platform_device *pde= v) clk_disable: clk_bulk_disable_unprepare(qcom->num_clocks, qcom->clks); =20 +resources_off: + if (qcom->fw_managed) + dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_EXIT); + return ret; } =20 @@ -739,6 +810,10 @@ static void dwc3_qcom_remove(struct platform_device *p= dev) return; =20 dwc3_core_remove(&qcom->dwc); + + if (qcom->fw_managed) + dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_EXIT); + clk_bulk_disable_unprepare(qcom->num_clocks, qcom->clks); dwc3_qcom_interconnect_exit(qcom); =20 @@ -756,7 +831,7 @@ static int dwc3_qcom_pm_suspend(struct device *dev) if (ret) return ret; =20 - ret =3D dwc3_qcom_suspend(qcom, wakeup); + ret =3D dwc3_qcom_suspend(qcom, wakeup, PMSG_SUSPEND); if (ret) return ret; =20 @@ -772,7 +847,7 @@ static int dwc3_qcom_pm_resume(struct device *dev) bool wakeup =3D device_may_wakeup(dev); int ret; =20 - ret =3D dwc3_qcom_resume(qcom, wakeup); + ret =3D dwc3_qcom_resume(qcom, wakeup, PMSG_RESUME); if (ret) return ret; =20 @@ -809,7 +884,7 @@ static int dwc3_qcom_runtime_suspend(struct device *dev) if (ret) return ret; =20 - return dwc3_qcom_suspend(qcom, true); + return dwc3_qcom_suspend(qcom, true, PMSG_AUTO_SUSPEND); } =20 static int dwc3_qcom_runtime_resume(struct device *dev) @@ -818,7 +893,7 @@ static int dwc3_qcom_runtime_resume(struct device *dev) struct dwc3_qcom *qcom =3D to_dwc3_qcom(dwc); int ret; =20 - ret =3D dwc3_qcom_resume(qcom, true); + ret =3D dwc3_qcom_resume(qcom, true, PMSG_AUTO_RESUME); if (ret) return ret; =20 @@ -839,6 +914,10 @@ static const struct dev_pm_ops dwc3_qcom_dev_pm_ops = =3D { }; =20 static const struct of_device_id dwc3_qcom_of_match[] =3D { + { + .compatible =3D "qcom,snps-dwc3-fw-managed", + .data =3D (void *)true, + }, { .compatible =3D "qcom,snps-dwc3" }, { } }; --=20 2.34.1