From nobody Mon Dec 1 23:06:55 2025 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 0A3EC22756A; Wed, 26 Nov 2025 13:05:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764162316; cv=none; b=sV/rA7R2Am5UXUAWMKuq0gBER5Rs5XBgzT1D+9HHYUaucb0VXl5Icem3AeO0EG3Efg+2LoTSLp538HG2QhxZITKUJ1CTaOGFE/dLVKhGkE0LaR9ekJzOxPUN6Y/E1yQ0DWoDDJUVt+BQWR+pFn0Y3HUWSwWYRq/SqhKKG5JU1+Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764162316; c=relaxed/simple; bh=PzzgNjocYWBzraToDPR4zbqXDV0pQkODpfP6ELH+LE8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=AJw80IGmmuzW1J7JKUWBSwmN33Mr60Va7nnwWvPWq+Yu8sVmFSqlOE1l6fAG5jCV0i1XST0jSbRfEk5bWiGkKml0RI/ObBk60eResPR7OLkGiFJg0sM0i2bugXu1wyPkh4ACIyVEpNeFalUmQO7eT9uArir+cZswmfOx0bdKKy4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: W+NTOzuJSo6GRuNP26fJ5A== X-CSE-MsgGUID: ZW4Npv/TS0K8wWfVgDVUGw== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 26 Nov 2025 22:05:13 +0900 Received: from demon-pc.localdomain (unknown [10.226.92.98]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id A00E4400EF6C; Wed, 26 Nov 2025 22:05:08 +0900 (JST) From: Cosmin Tanislav To: John Madieu , "Rafael J . Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Philipp Zabel Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Cosmin Tanislav Subject: [PATCH v3 5/9] thermal: renesas: rzg3e: add support for RZ/T2H and RZ/N2H Date: Wed, 26 Nov 2025 15:03:52 +0200 Message-ID: <20251126130356.2768625-6-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251126130356.2768625-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20251126130356.2768625-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs expose the temperature calibration via SMC SIP and do not have a reset for the TSU peripheral, and use different minimum and maximum temperature values compared to the already supported RZ/G3E. Although the calibration data is stored in an OTP memory, the OTP itself is not memory-mapped, access to it is done through an OTP controller. The OTP controller is only accessible from the secure world, but the temperature calibration data stored in the OTP is exposed via SMC. Add support for retrieving the calibration data using arm_smcc_smc(). Add a compatible for RZ/T2H, RZ/N2H can use it as a fallback. Signed-off-by: Cosmin Tanislav --- V3: * no changes V2: * no changes drivers/thermal/renesas/rzg3e_thermal.c | 26 +++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/thermal/renesas/rzg3e_thermal.c b/drivers/thermal/rene= sas/rzg3e_thermal.c index d2525ad3ffcc..efd09c35b216 100644 --- a/drivers/thermal/renesas/rzg3e_thermal.c +++ b/drivers/thermal/renesas/rzg3e_thermal.c @@ -72,6 +72,10 @@ =20 #define TSU_TEMP_MASK GENMASK(11, 0) =20 +#define RZ_SIP_SVC_GET_SYSTSU 0x82000022 +#define OTP_TSU_REG_ADR_TEMPHI 0x01DC +#define OTP_TSU_REG_ADR_TEMPLO 0x01DD + struct rzg3e_thermal_priv; =20 struct rzg3e_thermal_info { @@ -381,6 +385,21 @@ static int rzg3e_thermal_get_syscon_trim(struct rzg3e_= thermal_priv *priv) return 0; } =20 +static int rzg3e_thermal_get_smc_trim(struct rzg3e_thermal_priv *priv) +{ + struct arm_smccc_res local_res; + + arm_smccc_smc(RZ_SIP_SVC_GET_SYSTSU, OTP_TSU_REG_ADR_TEMPLO, + 0, 0, 0, 0, 0, 0, &local_res); + priv->trmval0 =3D local_res.a0 & TSU_TEMP_MASK; + + arm_smccc_smc(RZ_SIP_SVC_GET_SYSTSU, OTP_TSU_REG_ADR_TEMPHI, + 0, 0, 0, 0, 0, 0, &local_res); + priv->trmval1 =3D local_res.a0 & TSU_TEMP_MASK; + + return 0; +} + static int rzg3e_thermal_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -539,8 +558,15 @@ static const struct rzg3e_thermal_info rzg3e_thermal_i= nfo =3D { .temp_e_mc =3D 126000, }; =20 +static const struct rzg3e_thermal_info rzt2h_thermal_info =3D { + .get_trim =3D rzg3e_thermal_get_smc_trim, + .temp_d_mc =3D -40000, + .temp_e_mc =3D 125000, +}; + static const struct of_device_id rzg3e_thermal_dt_ids[] =3D { { .compatible =3D "renesas,r9a09g047-tsu", .data =3D &rzg3e_thermal_info = }, + { .compatible =3D "renesas,r9a09g077-tsu", .data =3D &rzt2h_thermal_info = }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, rzg3e_thermal_dt_ids); --=20 2.52.0