From nobody Mon Dec 1 23:06:56 2025 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 54A7421B905; Wed, 26 Nov 2025 13:04:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764162298; cv=none; b=NUYZ629QCcUtjJEJG//Ki+4zlT+A1SgOvkWIai+XSZdX9/mZoDFTy0Yn8n5c+pO3fxhoyuogqjPwsSWR05q6sB1v1jBGUfE2LR3IP60l03OPagSa8VYRy6HKqNWZihsPWGRbIIGVuHXJDuFfhkp/VFZbXHEAsT7fHR9Dt/jaAU8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764162298; c=relaxed/simple; bh=J9yUnSMRv9Tph8SjqcMrQkdXFrwHmRg+3/BxnDv5X2k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Q9RDK3CUILqoVlJmBrq3rLbKAtb6H9utaWHqqeix8TL8xTJ4BP8nYO1WpV1MrFnz6m7f80zINHLkCS6m4jLxoNGNzf/Xyh0p6wCAoYCz9o7h/wXxFQ9a54LE9gVNwmOm/xeu8ZIRJdfzoD0PqDPX3kTXiNPFG4H808H3tjlpiDY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: WZp3P4KRQAWOBdcMj8r8SQ== X-CSE-MsgGUID: yWByuc9OR5u5PPaTbabQDw== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 26 Nov 2025 22:04:55 +0900 Received: from demon-pc.localdomain (unknown [10.226.92.98]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 8B6EF400EF74; Wed, 26 Nov 2025 22:04:50 +0900 (JST) From: Cosmin Tanislav To: John Madieu , "Rafael J . Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Philipp Zabel Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Cosmin Tanislav Subject: [PATCH v3 2/9] thermal: renesas: rzg3e: make min and max temperature per-chip Date: Wed, 26 Nov 2025 15:03:49 +0200 Message-ID: <20251126130356.2768625-3-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251126130356.2768625-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20251126130356.2768625-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs have different minimum and maximum temperatures compared to the already supported RZ/G3E. Prepare for them by moving these into a chip-specific struct. Signed-off-by: Cosmin Tanislav --- V3: * no changes V2: * no changes drivers/thermal/renesas/rzg3e_thermal.c | 35 ++++++++++++++++--------- 1 file changed, 23 insertions(+), 12 deletions(-) diff --git a/drivers/thermal/renesas/rzg3e_thermal.c b/drivers/thermal/rene= sas/rzg3e_thermal.c index 86c10810e5bf..3c9ff5e43d7e 100644 --- a/drivers/thermal/renesas/rzg3e_thermal.c +++ b/drivers/thermal/renesas/rzg3e_thermal.c @@ -62,8 +62,6 @@ #define TSU_SICR_CMPCLR BIT(1) =20 /* Temperature calculation constants from datasheet */ -#define TSU_TEMP_D (-41) -#define TSU_TEMP_E 126 #define TSU_CODE_MAX 0xFFF =20 /* Timing specifications from datasheet */ @@ -72,6 +70,11 @@ #define TSU_POLL_DELAY_US 10 /* Polling interval */ #define TSU_MIN_CLOCK_RATE 24000000 /* TSU_PCLK minimum 24MHz */ =20 +struct rzg3e_thermal_info { + int temp_d_mc; + int temp_e_mc; +}; + /** * struct rzg3e_thermal_priv - RZ/G3E TSU private data * @base: TSU register base @@ -79,6 +82,7 @@ * @syscon: regmap for calibration values * @zone: thermal zone device * @rstc: reset control + * @info: chip type specific information * @trmval0: calibration value 0 (b) * @trmval1: calibration value 1 (c) * @trim_offset: offset for trim registers in syscon @@ -90,6 +94,7 @@ struct rzg3e_thermal_priv { struct regmap *syscon; struct thermal_zone_device *zone; struct reset_control *rstc; + const struct rzg3e_thermal_info *info; u16 trmval0; u16 trmval1; u32 trim_offset; @@ -161,17 +166,17 @@ static void rzg3e_thermal_power_off(struct rzg3e_ther= mal_priv *priv) */ static int rzg3e_thermal_code_to_temp(struct rzg3e_thermal_priv *priv, u16= code) { - int temp_e_mc =3D TSU_TEMP_E * MILLIDEGREE_PER_DEGREE; - int temp_d_mc =3D TSU_TEMP_D * MILLIDEGREE_PER_DEGREE; + const struct rzg3e_thermal_info *info =3D priv->info; s64 numerator, denominator; int temp_mc; =20 - numerator =3D (temp_e_mc - temp_d_mc) * (s64)(code - priv->trmval0); + numerator =3D (info->temp_e_mc - info->temp_d_mc) * + (s64)(code - priv->trmval0); denominator =3D priv->trmval1 - priv->trmval0; =20 - temp_mc =3D div64_s64(numerator, denominator) + temp_d_mc; + temp_mc =3D div64_s64(numerator, denominator) + info->temp_d_mc; =20 - return clamp(temp_mc, temp_d_mc, temp_e_mc); + return clamp(temp_mc, info->temp_d_mc, info->temp_e_mc); } =20 /* @@ -180,13 +185,12 @@ static int rzg3e_thermal_code_to_temp(struct rzg3e_th= ermal_priv *priv, u16 code) */ static u16 rzg3e_thermal_temp_to_code(struct rzg3e_thermal_priv *priv, int= temp_mc) { - int temp_e_mc =3D TSU_TEMP_E * MILLIDEGREE_PER_DEGREE; - int temp_d_mc =3D TSU_TEMP_D * MILLIDEGREE_PER_DEGREE; + const struct rzg3e_thermal_info *info =3D priv->info; s64 numerator, denominator; s64 code; =20 - numerator =3D (temp_mc - temp_d_mc) * (priv->trmval1 - priv->trmval0); - denominator =3D temp_e_mc - temp_d_mc; + numerator =3D (temp_mc - info->temp_d_mc) * (priv->trmval1 - priv->trmval= 0); + denominator =3D info->temp_e_mc - info->temp_d_mc; =20 code =3D div64_s64(numerator, denominator) + priv->trmval0; =20 @@ -392,6 +396,8 @@ static int rzg3e_thermal_probe(struct platform_device *= pdev) return ret; platform_set_drvdata(pdev, priv); =20 + priv->info =3D device_get_match_data(dev); + priv->base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(priv->base)) return PTR_ERR(priv->base); @@ -526,8 +532,13 @@ static const struct dev_pm_ops rzg3e_thermal_pm_ops = =3D { SYSTEM_SLEEP_PM_OPS(rzg3e_thermal_suspend, rzg3e_thermal_resume) }; =20 +static const struct rzg3e_thermal_info rzg3e_thermal_info =3D { + .temp_d_mc =3D -41000, + .temp_e_mc =3D 126000, +}; + static const struct of_device_id rzg3e_thermal_dt_ids[] =3D { - { .compatible =3D "renesas,r9a09g047-tsu" }, + { .compatible =3D "renesas,r9a09g047-tsu", .data =3D &rzg3e_thermal_info = }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, rzg3e_thermal_dt_ids); --=20 2.52.0