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[92.29.237.183]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4790ade13ddsm38630535e9.8.2025.11.26.03.26.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Nov 2025 03:26:57 -0800 (PST) From: Andrew Cooper To: LKML Cc: Andrew Cooper , Borislav Petkov , Mario Limonciello , x86@kernel.org Subject: [PATCH] x86/cpu/amd: Correct the microcode table for Zenbleed Date: Wed, 26 Nov 2025 11:26:55 +0000 Message-Id: <20251126112655.874792-1-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The good revisions are tied to exact steppings, meaning it's not valid to match on model number alone, let alone a range. This is probably only a latent issue. From public microcode archives, the followin CPUs exist 17-30-00, 17-60-00, 17-70-00 and would be captured by t= he model ranges. They're likely pre-production steppings, and likely didn't g= et Zenbleed microcode, but it's still incorrect to compare them to a different stepping's revision. Either way, convert the logic to use x86_match_min_microcode_rev(), which is the preferred mechanism. Fixes: 522b1d69219d ("x86/cpu/amd: Add a Zenbleed fix") Signed-off-by: Andrew Cooper --- CC: Borislav Petkov CC: Mario Limonciello CC: x86@kernel.org CC: linux-kernel@vger.kernel.org --- arch/x86/kernel/cpu/amd.c | 29 ++++++++--------------------- 1 file changed, 8 insertions(+), 21 deletions(-) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 5d46709c58d0..9721d24727e9 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -951,26 +951,13 @@ static void init_amd_zen1(struct cpuinfo_x86 *c) } } =20 -static bool cpu_has_zenbleed_microcode(void) -{ - u32 good_rev =3D 0; - - switch (boot_cpu_data.x86_model) { - case 0x30 ... 0x3f: good_rev =3D 0x0830107b; break; - case 0x60 ... 0x67: good_rev =3D 0x0860010c; break; - case 0x68 ... 0x6f: good_rev =3D 0x08608107; break; - case 0x70 ... 0x7f: good_rev =3D 0x08701033; break; - case 0xa0 ... 0xaf: good_rev =3D 0x08a00009; break; - - default: - return false; - } - - if (boot_cpu_data.microcode < good_rev) - return false; - - return true; -} +static const struct x86_cpu_id amd_zenbleed_microcode[] =3D { + ZEN_MODEL_STEP_UCODE(0x17, 0x31, 0x0, 0x0830107b), + ZEN_MODEL_STEP_UCODE(0x17, 0x60, 0x1, 0x0860010c), + ZEN_MODEL_STEP_UCODE(0x17, 0x68, 0x1, 0x08608107), + ZEN_MODEL_STEP_UCODE(0x17, 0x71, 0x0, 0x08701033), + ZEN_MODEL_STEP_UCODE(0x17, 0xa0, 0x0, 0x08a00009), +}; =20 static void zen2_zenbleed_check(struct cpuinfo_x86 *c) { @@ -980,7 +967,7 @@ static void zen2_zenbleed_check(struct cpuinfo_x86 *c) if (!cpu_has(c, X86_FEATURE_AVX)) return; =20 - if (!cpu_has_zenbleed_microcode()) { + if (!x86_match_min_microcode_rev(amd_zenbleed_microcode)) { pr_notice_once("Zenbleed: please update your microcode for the most opti= mal fix\n"); msr_set_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT); } else { base-commit: ac3fd01e4c1efce8f2c054cdeb2ddd2fc0fb150d --=20 2.39.5