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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Nov 2025 09:29:59.6273 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ff6dc82d-50e4-4e70-4c28-08de2cce5eb8 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.195];Helo=[lewvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7C.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR10MB7022 Content-Type: text/plain; charset="utf-8" Move register name constraints and reg description lists to appropriate compatibility sections to ensure correct register names are used with each compatible value. The j721e-integ registers are specific to TI SoCs and not required for other compatibles. Add DSC register descriptions to align bindings with hardware capabilities. Structure the reg and reg-names constraints as lists according to compatibles using oneOf schema construct. Fixes: 7169d082e7e6 ("dt-bindings: drm/bridge: MHDP8546 bridge binding chan= ges for HDCP") Signed-off-by: Harikrishna Shenoy --- Links to some discussions pointing to need for a fixes patch:=20 https://lore.kernel.org/all/20250903220312.GA2903503-robh@kernel.org/ https://lore.kernel.org/all/d2367789-6b54-4fc2-bb7c-609c0fe084d3@ti.com/ Link to v3: Changelog v3 --> v4: - Update top level constraints and commit message. - Update logs with processed schema- https://gist.github.com/h-shenoy/a422f= 7278859cd95447e674963caabd9 Link to v2: Changelog v2 --> v3: -Add the reg description list and reg-name list in top level constraints using oneOf for either of compatible. Logs after testing some cases: https://gist.github.com/h-shenoy/a422f727885= 9cd95447e674963caabd9 Link to v1: Changelog v1 --> v2: -Update the reg description list for each compatible and add register space for dsc to make the bindings reflect what hardware supports although=20 the driver doesn't support dsc yet. Note: j721e-integ are not optional registers for ti-compatible. .../display/bridge/cdns,mhdp8546.yaml | 85 ++++++++++++++----- 1 file changed, 66 insertions(+), 19 deletions(-) diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546= .yaml b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml index c2b369456e4e2..4cec0f4c22a2b 100644 --- a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml +++ b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml @@ -17,23 +17,45 @@ properties: - ti,j721e-mhdp8546 =20 reg: - minItems: 1 - items: - - description: - Register block of mhdptx apb registers up to PHY mapped area (AU= X_CONFIG_P). - The AUX and PMA registers are not part of this range, they are i= nstead - included in the associated PHY. - - description: - Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI = J7 SoCs. - - description: - Register block of mhdptx sapb registers. + oneOf: + - items: + - description: + Register block of mhdptx apb registers up to PHY mapped area= (AUX_CONFIG_P). + The AUX and PMA registers are not part of this range, they a= re instead + included in the associated PHY. + - description: + Register block for DSS_EDP0_INTG_CFG_VP registers in case of= TI J7 SoCs. + - description: + Register block of mhdptx sapb registers. + - description: + Register block for mhdptx DSC encoder registers. + minItems: 2 + + - items: + - description: + Register block of mhdptx apb registers up to PHY mapped area= (AUX_CONFIG_P). + The AUX and PMA registers are not part of this range, they a= re instead + included in the associated PHY. + - description: + Register block of mhdptx sapb registers. + - description: + Register block for mhdptx DSC encoder registers. + minItems: 1 =20 reg-names: - minItems: 1 - items: - - const: mhdptx - - const: j721e-intg - - const: mhdptx-sapb + oneOf: + - items: + - const: mhdptx + - const: j721e-intg + - const: mhdptx-sapb + - const: dsc + minItems: 2 + + - items: + - const: mhdptx + - const: mhdptx-sapb + - const: dsc + minItems: 1 =20 clocks: maxItems: 1 @@ -100,18 +122,43 @@ allOf: properties: reg: minItems: 2 - maxItems: 3 + items: + - description: + Register block of mhdptx apb registers up to PHY mapped ar= ea (AUX_CONFIG_P). + The AUX and PMA registers are not part of this range, they= are instead + included in the associated PHY. + - description: + Register block for DSS_EDP0_INTG_CFG_VP registers in case = of TI J7 SoCs. + - description: + Register block of mhdptx sapb registers. + - description: + Register block for mhdptx DSC encoder registers. reg-names: minItems: 2 - maxItems: 3 + items: + - const: mhdptx + - const: j721e-intg + - const: mhdptx-sapb + - const: dsc else: properties: reg: minItems: 1 - maxItems: 2 + items: + - description: + Register block of mhdptx apb registers up to PHY mapped ar= ea (AUX_CONFIG_P). + The AUX and PMA registers are not part of this range, they= are instead + included in the associated PHY. + - description: + Register block of mhdptx sapb registers. + - description: + Register block for mhdptx DSC encoder registers. reg-names: minItems: 1 - maxItems: 2 + items: + - const: mhdptx + - const: mhdptx-sapb + - const: dsc =20 required: - compatible --=20 2.34.1