From nobody Mon Dec 1 23:33:38 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 23F652D248C; Wed, 26 Nov 2025 07:56:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764143767; cv=none; b=t4NG2VhqsHTyRGcNuXggwU+KXZCMkzLUuToaB4iS8mOoLCd4nPQYSp3RjeswA2ZUi+7VBr0dFxz5rGxkQUQjbuC6k4qoMVOWAf1w56PYgkdUZyEEW2ZDRKkkkdJ4FGMv9ERNj58d0NLZWHYgiQFzfEOFdCJd85ko/BdZG0dv9VU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764143767; c=relaxed/simple; bh=i348gRZwFs1j437kjQtd2OZNYyRNL6pS+Luhhms/cVs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qHNi3U39ebie6DhmcblixfFyhH1AVvdSNrpN9Cwt2CO1ya/q+V2GpjOFVVuSr3H9qUmALEFVcBk+pnEZ9fbn9k42F52aK+5dKGKBE+Aj9zwV/OyOewagkulO+gLHKDIVbd1ReddK56AdUA7WVAb8U96uD4aAV7iEMUXSwxyxDNQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=bCNktjCM; arc=none smtp.client-ip=192.198.163.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="bCNktjCM" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1764143766; x=1795679766; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=i348gRZwFs1j437kjQtd2OZNYyRNL6pS+Luhhms/cVs=; b=bCNktjCMjRoF3kSSaMMH3Up6cOA212PW/b/mYqVZgb98BBMBAq21kxwz LvZysVgrW12jEf+7R6CnTNTpcug4yP+gcH5aVQjr4/xSI98eMT1HY98im 13o4vijPZwz/noU4laaSLfMLuoeN4Nlz+v3tRVNcgE/kCYyTV4PYSOE0T nUNCG5DIWyQmk7fq4MDazcbWybgJYUGAl513SLBGJaWjgB/1tzdF14Vpf epSrd6WTUAwUof0WWlFXJxH8rYeTR4rABKsqaAs0IrHZusGtZGvGLLFyx u1WGNpGr8wG0LCRLkIA7Js0RU/bPgdH9RTxyHiELzkmboTn6YOfQvYv0b Q==; X-CSE-ConnectionGUID: DelBNBZjT92lLdfvMT2/+Q== X-CSE-MsgGUID: YVJAW2OZQJ6JVgDhG1NwgQ== X-IronPort-AV: E=McAfee;i="6800,10657,11624"; a="77538901" X-IronPort-AV: E=Sophos;i="6.20,227,1758610800"; d="scan'208";a="77538901" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Nov 2025 23:56:03 -0800 X-CSE-ConnectionGUID: Z38RqhYvTe2RKATIFvt0NA== X-CSE-MsgGUID: bpe86PM0RRGm+5m2I4VXQA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.20,227,1758610800"; d="scan'208";a="197026112" Received: from black.igk.intel.com ([10.91.253.5]) by orviesa003.jf.intel.com with ESMTP; 25 Nov 2025 23:56:02 -0800 Received: by black.igk.intel.com (Postfix, from userid 1003) id 1BF19A1; Wed, 26 Nov 2025 08:56:00 +0100 (CET) From: Andy Shevchenko To: Andy Shevchenko , Prajna Rajendra Kumar , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Brown Subject: [PATCH v2 1/6] spi: microchip-core: use min() instead of min_t() Date: Wed, 26 Nov 2025 08:54:39 +0100 Message-ID: <20251126075558.2035012-2-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251126075558.2035012-1-andriy.shevchenko@linux.intel.com> References: <20251126075558.2035012-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" min_t(int, a, b) casts an 'unsigned int' to 'int'. This might lead to the cases when big number is wrongly chosen. On the other hand, the SPI transfer length is unsigned and driver uses signed type for an unknown reason. Change the type of the transfer length to be unsigned and convert use min() instead of min_t(). Signed-off-by: Andy Shevchenko Reviewed-by: David Laight Reviewed-by: Prajna Rajendra Kumar --- drivers/spi/spi-microchip-core-spi.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/spi/spi-microchip-core-spi.c b/drivers/spi/spi-microch= ip-core-spi.c index 16e0885474a0..08ccdc5f0cc9 100644 --- a/drivers/spi/spi-microchip-core-spi.c +++ b/drivers/spi/spi-microchip-core-spi.c @@ -74,8 +74,8 @@ struct mchp_corespi { u8 *rx_buf; u32 clk_gen; int irq; - int tx_len; - int rx_len; + unsigned int tx_len; + unsigned int rx_len; u32 fifo_depth; }; =20 @@ -214,7 +214,7 @@ static irqreturn_t mchp_corespi_interrupt(int irq, void= *dev_id) spi->regs + MCHP_CORESPI_REG_INTCLEAR); finalise =3D true; dev_err(&host->dev, - "RX OVERFLOW: rxlen: %d, txlen: %d\n", + "RX OVERFLOW: rxlen: %u, txlen: %u\n", spi->rx_len, spi->tx_len); } =20 @@ -223,7 +223,7 @@ static irqreturn_t mchp_corespi_interrupt(int irq, void= *dev_id) spi->regs + MCHP_CORESPI_REG_INTCLEAR); finalise =3D true; dev_err(&host->dev, - "TX UNDERFLOW: rxlen: %d, txlen: %d\n", + "TX UNDERFLOW: rxlen: %u, txlen: %u\n", spi->rx_len, spi->tx_len); } =20 @@ -283,7 +283,7 @@ static int mchp_corespi_transfer_one(struct spi_control= ler *host, spi->rx_len =3D xfer->len; =20 while (spi->tx_len) { - int fifo_max =3D min_t(int, spi->tx_len, spi->fifo_depth); + unsigned int fifo_max =3D min(spi->tx_len, spi->fifo_depth); =20 mchp_corespi_write_fifo(spi, fifo_max); mchp_corespi_read_fifo(spi, fifo_max); --=20 2.50.1 From nobody Mon Dec 1 23:33:38 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3450A28A1D5; Wed, 26 Nov 2025 07:56:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764143765; cv=none; b=gYOVg8wwzxlq1d3P80gRgtZZcjCUtFzMVTezxM6hJQX4air1HnM5nmkJTOTDlDNu1X0FUKn9U5cR3iBk9S7dD07y+MheIz8GsXDifiS+zRMHhIFuAgRm3hqktN4jqTGd0dlXt9SAG/sPu2Mtf1t+c37y4TxKwqMZIZfL38Ixpls= ARC-Message-Signature: i=1; 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d="scan'208";a="197026110" Received: from black.igk.intel.com ([10.91.253.5]) by orviesa003.jf.intel.com with ESMTP; 25 Nov 2025 23:56:02 -0800 Received: by black.igk.intel.com (Postfix, from userid 1003) id 202F1A2; Wed, 26 Nov 2025 08:56:00 +0100 (CET) From: Andy Shevchenko To: Andy Shevchenko , Prajna Rajendra Kumar , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Brown Subject: [PATCH v2 2/6] spi: microchip-core: Refactor FIFO read and write handlers Date: Wed, 26 Nov 2025 08:54:40 +0100 Message-ID: <20251126075558.2035012-3-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251126075558.2035012-1-andriy.shevchenko@linux.intel.com> References: <20251126075558.2035012-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Make both handlers to be shorter and easier to understand. While at it, unify their style. Signed-off-by: Andy Shevchenko --- drivers/spi/spi-microchip-core-spi.c | 32 +++++++++------------------- 1 file changed, 10 insertions(+), 22 deletions(-) diff --git a/drivers/spi/spi-microchip-core-spi.c b/drivers/spi/spi-microch= ip-core-spi.c index 08ccdc5f0cc9..f8184b711272 100644 --- a/drivers/spi/spi-microchip-core-spi.c +++ b/drivers/spi/spi-microchip-core-spi.c @@ -91,21 +91,14 @@ static inline void mchp_corespi_disable(struct mchp_cor= espi *spi) static inline void mchp_corespi_read_fifo(struct mchp_corespi *spi, u32 fi= fo_max) { for (int i =3D 0; i < fifo_max; i++) { - u32 data; - while (readb(spi->regs + MCHP_CORESPI_REG_STAT) & MCHP_CORESPI_STATUS_RXFIFO_EMPTY) ; =20 - data =3D readb(spi->regs + MCHP_CORESPI_REG_RXDATA); + if (spi->rx_buf) + *spi->rx_buf++ =3D readb(spi->regs + MCHP_CORESPI_REG_RXDATA); =20 spi->rx_len--; - if (!spi->rx_buf) - continue; - - *spi->rx_buf =3D data; - - spi->rx_buf++; } } =20 @@ -127,23 +120,18 @@ static void mchp_corespi_disable_ints(struct mchp_cor= espi *spi) =20 static inline void mchp_corespi_write_fifo(struct mchp_corespi *spi, u32 f= ifo_max) { - int i =3D 0; - - while ((i < fifo_max) && - !(readb(spi->regs + MCHP_CORESPI_REG_STAT) & - MCHP_CORESPI_STATUS_TXFIFO_FULL)) { - u32 word; - - word =3D spi->tx_buf ? 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Second, it's ignored by dev_err_probe(). Replace dead code by a simple return statement. Signed-off-by: Andy Shevchenko Reviewed-by: Prajna Rajendra Kumar --- drivers/spi/spi-microchip-core-spi.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/spi/spi-microchip-core-spi.c b/drivers/spi/spi-microch= ip-core-spi.c index f8184b711272..8ea382c6fee7 100644 --- a/drivers/spi/spi-microchip-core-spi.c +++ b/drivers/spi/spi-microchip-core-spi.c @@ -293,8 +293,7 @@ static int mchp_corespi_probe(struct platform_device *p= dev) =20 host =3D devm_spi_alloc_host(&pdev->dev, sizeof(*spi)); if (!host) - return dev_err_probe(&pdev->dev, -ENOMEM, - "unable to allocate host for SPI controller\n"); + return -ENOMEM; =20 platform_set_drvdata(pdev, host); =20 --=20 2.50.1 From nobody Mon Dec 1 23:33:38 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE3E028DB71; Wed, 26 Nov 2025 07:56:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764143766; cv=none; b=KJzlTZosDy6Rg33pxvk/w+KLwknaaxJKnM0Q4VqEu4Sq+RbKk7Sq+rZdLjTmdMJepUzTAz1vz7l7r3S3pCp53SrJRE1IzKJL7VdlP8/SoIAqPyP0pKFAog6/RGDGDSFf0Rm4L17Vy3QIyE7HvIEGFuWfExP81P9+R3tYJ8Yw7SQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764143766; c=relaxed/simple; bh=VU63BbmLmgOChGLd4KlK5mlVcUccPkxsI1Udw+sJqGA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cGekvlYIIblth7dWR7YYSBPW+nB0kHPzF5l//3y3f7lIUoO985m+oIKp9FYS76cZb8wtQ/4IkKCd02i0dgh8rGWQ7tEtt/Ue4/n0WDbz0W6MwLjyQwyMY0q7inPY5UxcHhxURA1DuDTQNDKrc9RwUPbf3buoHZz8c3e79DmfByg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=mHqGpUNj; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="mHqGpUNj" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1764143765; x=1795679765; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VU63BbmLmgOChGLd4KlK5mlVcUccPkxsI1Udw+sJqGA=; b=mHqGpUNjyGxqVdBPcSJoS4umLDdOuDv2QTjaOLfnr0csDRwT5vNPvZTk PSi7by1oiUvhiJnmMq9SBCg3GGwUlCSVa/oM9xDBSuMo/XpqTSyrjbxBp kiOdAGe0PlWMHDDrjZYTrRRgkL/nmLOtT3rRqsW0T/Uf7ZVk2dhcncoTi iPMnGMFQnrL8Ga73LREfl2KQqkw+kUKT8dsE588KsDiyhwiH2p63nLTyd qzoyn+iQlpriip9SrkVaR2GkW7bMYovCaTQbObeMx2v/mLtytJhZ94E56 AUh9eX/s/6U5Aw5yUnEBPbSJHUsOLGxORXVmhW4/UeGKgsKf0dZ6Hxfq1 Q==; X-CSE-ConnectionGUID: /gabddMlS2eXtZwmRHLesg== X-CSE-MsgGUID: fGqy2y/RQsmLLh51r/kfpA== X-IronPort-AV: E=McAfee;i="6800,10657,11624"; a="65360565" X-IronPort-AV: E=Sophos;i="6.20,227,1758610800"; d="scan'208";a="65360565" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Nov 2025 23:56:02 -0800 X-CSE-ConnectionGUID: nlaN5+TrTCiUEt7QQSpLpA== X-CSE-MsgGUID: mQEBwfZMQuWML/B3RnNwmg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.20,227,1758610800"; d="scan'208";a="192006618" Received: from black.igk.intel.com ([10.91.253.5]) by orviesa006.jf.intel.com with ESMTP; 25 Nov 2025 23:56:02 -0800 Received: by black.igk.intel.com (Postfix, from userid 1003) id 28818A4; Wed, 26 Nov 2025 08:56:00 +0100 (CET) From: Andy Shevchenko To: Andy Shevchenko , Prajna Rajendra Kumar , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Brown Subject: [PATCH v2 4/6] spi: microchip-core: Utilise temporary variable for struct device Date: Wed, 26 Nov 2025 08:54:42 +0100 Message-ID: <20251126075558.2035012-5-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251126075558.2035012-1-andriy.shevchenko@linux.intel.com> References: <20251126075558.2035012-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a temporary variable to keep a pointer to struct device. Utilise it where it makes sense. Signed-off-by: Andy Shevchenko Reviewed-by: Prajna Rajendra Kumar --- drivers/spi/spi-microchip-core-spi.c | 44 +++++++++++++--------------- 1 file changed, 21 insertions(+), 23 deletions(-) diff --git a/drivers/spi/spi-microchip-core-spi.c b/drivers/spi/spi-microch= ip-core-spi.c index 8ea382c6fee7..0dca46dcdc2f 100644 --- a/drivers/spi/spi-microchip-core-spi.c +++ b/drivers/spi/spi-microchip-core-spi.c @@ -284,6 +284,7 @@ static int mchp_corespi_transfer_one(struct spi_control= ler *host, static int mchp_corespi_probe(struct platform_device *pdev) { const char *protocol =3D "motorola"; + struct device *dev =3D &pdev->dev; struct spi_controller *host; struct mchp_corespi *spi; struct resource *res; @@ -291,13 +292,13 @@ static int mchp_corespi_probe(struct platform_device = *pdev) bool assert_ssel; int ret =3D 0; =20 - host =3D devm_spi_alloc_host(&pdev->dev, sizeof(*spi)); + host =3D devm_spi_alloc_host(dev, sizeof(*spi)); if (!host) return -ENOMEM; =20 platform_set_drvdata(pdev, host); =20 - if (of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs)) + if (of_property_read_u32(dev->of_node, "num-cs", &num_cs)) num_cs =3D MCHP_CORESPI_MAX_CS; =20 /* @@ -305,12 +306,12 @@ static int mchp_corespi_probe(struct platform_device = *pdev) * CoreSPI can be configured for Motorola, TI or NSC. * The current driver supports only Motorola mode. */ - ret =3D of_property_read_string(pdev->dev.of_node, "microchip,protocol-co= nfiguration", + ret =3D of_property_read_string(dev->of_node, "microchip,protocol-configu= ration", &protocol); if (ret && ret !=3D -EINVAL) - return dev_err_probe(&pdev->dev, ret, "Error reading protocol-configurat= ion\n"); + return dev_err_probe(dev, ret, "Error reading protocol-configuration\n"); if (strcmp(protocol, "motorola") !=3D 0) - return dev_err_probe(&pdev->dev, -EINVAL, + return dev_err_probe(dev, -EINVAL, "CoreSPI: protocol '%s' not supported by this driver\n", protocol); =20 @@ -318,11 +319,11 @@ static int mchp_corespi_probe(struct platform_device = *pdev) * Motorola mode (0-3): CFG_MOT_MODE * Mode is fixed in the IP configurator. */ - ret =3D of_property_read_u32(pdev->dev.of_node, "microchip,motorola-mode"= , &mode); + ret =3D of_property_read_u32(dev->of_node, "microchip,motorola-mode", &mo= de); if (ret) mode =3D MCHP_CORESPI_DEFAULT_MOTOROLA_MODE; else if (mode > 3) - return dev_err_probe(&pdev->dev, -EINVAL, + return dev_err_probe(dev, -EINVAL, "invalid 'microchip,motorola-mode' value %u\n", mode); =20 /* @@ -330,9 +331,9 @@ static int mchp_corespi_probe(struct platform_device *p= dev) * The hardware allows frame sizes <=3D APB data width. * However, this driver currently only supports 8-bit frames. */ - ret =3D of_property_read_u32(pdev->dev.of_node, "microchip,frame-size", &= frame_size); + ret =3D of_property_read_u32(dev->of_node, "microchip,frame-size", &frame= _size); if (!ret && frame_size !=3D 8) - return dev_err_probe(&pdev->dev, -EINVAL, + return dev_err_probe(dev, -EINVAL, "CoreSPI: frame size %u not supported by this driver\n", frame_size); =20 @@ -342,9 +343,9 @@ static int mchp_corespi_probe(struct platform_device *p= dev) * To prevent CS deassertion when TX FIFO drains, the ssel-active property * keeps CS asserted for the full SPI transfer. */ - assert_ssel =3D of_property_read_bool(pdev->dev.of_node, "microchip,ssel-= active"); + assert_ssel =3D of_property_read_bool(dev->of_node, "microchip,ssel-activ= e"); if (!assert_ssel) - return dev_err_probe(&pdev->dev, -EINVAL, + return dev_err_probe(dev, -EINVAL, "hardware must enable 'microchip,ssel-active' to keep CS asserted= for the SPI transfer\n"); =20 spi =3D spi_controller_get_devdata(host); @@ -356,9 +357,9 @@ static int mchp_corespi_probe(struct platform_device *p= dev) host->bits_per_word_mask =3D SPI_BPW_RANGE_MASK(4, 32); host->transfer_one =3D mchp_corespi_transfer_one; host->set_cs =3D mchp_corespi_set_cs; - host->dev.of_node =3D pdev->dev.of_node; + host->dev.of_node =3D dev->of_node; =20 - ret =3D of_property_read_u32(pdev->dev.of_node, "fifo-depth", &spi->fifo_= depth); + ret =3D of_property_read_u32(dev->of_node, "fifo-depth", &spi->fifo_depth= ); if (ret) spi->fifo_depth =3D MCHP_CORESPI_DEFAULT_FIFO_DEPTH; =20 @@ -370,24 +371,21 @@ static int mchp_corespi_probe(struct platform_device = *pdev) if (spi->irq < 0) return spi->irq; =20 - ret =3D devm_request_irq(&pdev->dev, spi->irq, mchp_corespi_interrupt, - IRQF_SHARED, dev_name(&pdev->dev), host); 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charset="utf-8" Use SPI_MODE_X_MASK instead of open coded variant. Signed-off-by: Andy Shevchenko Reviewed-by: Prajna Rajendra Kumar --- drivers/spi/spi-microchip-core-spi.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/spi/spi-microchip-core-spi.c b/drivers/spi/spi-microch= ip-core-spi.c index 0dca46dcdc2f..941b7e23eac3 100644 --- a/drivers/spi/spi-microchip-core-spi.c +++ b/drivers/spi/spi-microchip-core-spi.c @@ -148,8 +148,6 @@ static void mchp_corespi_set_cs(struct spi_device *spi,= bool disable) =20 static int mchp_corespi_setup(struct spi_device *spi) { - u32 dev_mode =3D spi->mode & (SPI_CPOL | SPI_CPHA); - if (spi_get_csgpiod(spi, 0)) return 0; =20 @@ -158,7 +156,7 @@ static int mchp_corespi_setup(struct spi_device *spi) return -EOPNOTSUPP; } =20 - if (dev_mode & ~spi->controller->mode_bits) { + if (spi->mode & SPI_MODE_X_MASK & ~spi->controller->mode_bits) { dev_err(&spi->dev, "incompatible CPOL/CPHA, must match controller's Moto= rola mode\n"); return -EINVAL; } --=20 2.50.1 From nobody Mon Dec 1 23:33:38 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32DD92BD597; Wed, 26 Nov 2025 07:56:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764143766; cv=none; b=MtU8qZtcHQTTSUDLGxgwvncstlIn9eLhInzpycoj3L1GJHr+ytc9YkUQoioyFhjvejo/P6iGbzyfy5bEP4NlkQMCpVXK9ZeUkv8/qUn+q/tvMoHOtsm06Ho91dEu9sjiWdiQ7xHCGkGwaf1s5HzZJ05Q5w8whfmmJGn7aYXRWfM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764143766; c=relaxed/simple; bh=WpIlFW+rHIItQ6Zy5VuzO39Uv5jKLGU+mvQaSFeRR+U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=IubKzm48DXs2xwDleYe1IVewG67a1RFoVc9ZmFrD/t9WjODhgzMnN4gFB8jlBd71Q3nPauE+GQrenon2UZBm7dN/BGXLYdTUyERQ6mS0IfOEBJeWRJ6vNip0ep00oXGTXZ1qtnmgm4kypo4yN4YPjDfnezvS3AIzNoZZ3uQwFwQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=bPIXGJXs; arc=none smtp.client-ip=192.198.163.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="bPIXGJXs" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1764143765; x=1795679765; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=WpIlFW+rHIItQ6Zy5VuzO39Uv5jKLGU+mvQaSFeRR+U=; b=bPIXGJXs/gczLb+vvdkCXBXPxDK66HFe2tTO2fX6iu64py3XsEqLMybu jOoAlJjmfoSTD9hUGCOJxdKJyOLABH5O9MiEGixbnquXstwWSmjg/7h5h S14MQPUUZrYBg3kPOnWHjznDhgX//bK5KYmi/eC6tCxLV7OS97CDE1qZV T4KDnfIG46rlq6PKrOKfFkgZwxf/Omkr5LLlfAo0SLZbKuGGn//GdYFSb z3O4MFsA0sr1g1Y0qd06VzSzav/eIj58qAKmpBTtsgfG+q1M9Jl7haL9a VfzmeHhZ9wR79wSfoRyy+pcw1+04vrcQF8x/y3jxlTlTuUuySUahvvfAK Q==; X-CSE-ConnectionGUID: L5FzSXJkQIOynEPRpqL7Cw== X-CSE-MsgGUID: Fv8boAA7S/+tZPtaYDOY2Q== X-IronPort-AV: E=McAfee;i="6800,10657,11624"; a="77538908" X-IronPort-AV: E=Sophos;i="6.20,227,1758610800"; d="scan'208";a="77538908" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Nov 2025 23:56:04 -0800 X-CSE-ConnectionGUID: bcqtT2DBT7C8r4EI8R4YLg== X-CSE-MsgGUID: AZmjadbMS5GmtqvXeyN52g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.20,227,1758610800"; d="scan'208";a="197026119" Received: from black.igk.intel.com ([10.91.253.5]) by orviesa003.jf.intel.com with ESMTP; 25 Nov 2025 23:56:04 -0800 Received: by black.igk.intel.com (Postfix, from userid 1003) id 308BDA6; Wed, 26 Nov 2025 08:56:00 +0100 (CET) From: Andy Shevchenko To: Andy Shevchenko , Prajna Rajendra Kumar , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Brown Subject: [PATCH v2 6/6] spi: microchip-core: Remove unneeded PM related macro Date: Wed, 26 Nov 2025 08:54:44 +0100 Message-ID: <20251126075558.2035012-7-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251126075558.2035012-1-andriy.shevchenko@linux.intel.com> References: <20251126075558.2035012-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Static declaration by default are 0 or NULL, no need to initialise them explicitly. Remove unneeded PM related macro. Signed-off-by: Andy Shevchenko Reviewed-by: Prajna Rajendra Kumar --- drivers/spi/spi-microchip-core-spi.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/spi/spi-microchip-core-spi.c b/drivers/spi/spi-microch= ip-core-spi.c index 941b7e23eac3..1e62af20d6f2 100644 --- a/drivers/spi/spi-microchip-core-spi.c +++ b/drivers/spi/spi-microchip-core-spi.c @@ -398,8 +398,6 @@ static void mchp_corespi_remove(struct platform_device = *pdev) mchp_corespi_disable(spi); } =20 -#define MICROCHIP_SPI_PM_OPS (NULL) - /* * Platform driver data structure */ @@ -416,7 +414,6 @@ static struct platform_driver mchp_corespi_driver =3D { .probe =3D mchp_corespi_probe, .driver =3D { .name =3D "microchip-corespi", - .pm =3D MICROCHIP_SPI_PM_OPS, .of_match_table =3D of_match_ptr(mchp_corespi_dt_ids), }, .remove =3D mchp_corespi_remove, --=20 2.50.1