From nobody Mon Dec 1 23:02:30 2025 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 91392322A3E for ; Wed, 26 Nov 2025 10:57:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764154676; cv=none; b=tixYDySwzCsIdi0RTZpbJQndS+6psp/qQKui23cqLREDbG+hFy7WUQnh+K0jN6snkvOY7TDGPwGFpvp0gk5JJOBlluS6ep1+/z6NcHFPgsX3tbRbkdl53gUlqBz/3WpjBrFlT0tRbBIkMqgP/a8Zzb/B7qDRNywa5K65bWDBDiE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764154676; c=relaxed/simple; bh=LNCyuYyZmkWFZcCqoVNFMP/DsVAdzv6MiorRrcgFSHM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=UXxQvJac5rMfpV19ObTwFR+TYkriJ+vPLZBWda34OME7mDeDMx3TUcQa/XhULuk10PEphjerKGQx8NQRCzJ1eez2fueGzvTpwCCmeW/Iv1j/AD6FV8imZKUvpGUqtsEnIhGbY5Z0gncDC073JZigsYZM60YK8JJCETa0hGRakI8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=vYuiwAQj; arc=none smtp.client-ip=209.85.128.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="vYuiwAQj" Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-477a2ab455fso70023335e9.3 for ; Wed, 26 Nov 2025 02:57:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1764154672; x=1764759472; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=izIPWfoS9urp2dV3KvMRs2YvnYc7bdRi1OjC6bRCVDU=; b=vYuiwAQjExtVgjiUxJgfJuSREOqO+DrzX8ypIUL53sNMoCjsYZq6MUD2h92fa2sPUA SyXA3PSk3UuC8aqFyBITdminyybWze/Kr3C+pu2VP24YCS48J/iRY2NHZqRxf1F7f+O5 L4TQ3JULkmDIdNmcy0lUwUYFhim29z+UbEpto44jpTtBCcYxSbBuSsBRZUxeIszd0Nbh p8B95okImEOyMg5rz4i59Qhg19Ing/HMWIMMMgIeS6Zvk6dsx46VKECeOZte37Lx8Mh8 2XNrpDbr+f8UvQMxo/7FEGVwcnV1HGLcjsLVAAkQhRe0833xI+greuhNor/La4kHS3nr y7ZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764154672; x=1764759472; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=izIPWfoS9urp2dV3KvMRs2YvnYc7bdRi1OjC6bRCVDU=; b=MzJpHMoZKJopdPxVUG03XNEXVRQSs+o7KDYWLUcomOAf3EpEXcSzYibtcN7KpRknvd Min40jZh8UtUfLvK8EoblTln2GXuS61R1Ak1bSh79n/z1F+g97dZe5cOo1vDwY9UrfUp WTiDUOVdOo/jetV1sBmILE6K+FRbSkyyRbDnKkcu0y7mrfSM0h0SbCCp+yo0OiBg2EsZ SnxdKit30ANJDwusya5PyUBukJXwcUSNwhY/TLEyjVoXuAajkJ4TaC16JPXip3ItB4bL hfArrrn/TePNJ7DsHZWrfLOqvtQOy2TiHQ1TQfaxlWQv/V9r5x/4JUB4TKdAlYWqrLdw oYmQ== X-Forwarded-Encrypted: i=1; AJvYcCXgoCDUwT+Be2zHVQUNANj1dLqm83fXaA25zvDpq56eFPBNC/crcUB4YWlhK0G79Rk9skOm2CdX3b1quGI=@vger.kernel.org X-Gm-Message-State: AOJu0YyZRqLHC1w+1ugBzBeXp+tOS8wgVGif3TfmhZxnGqk0p9iMWBbs RUmc5GFrTnVcHuIrO8X20ItVwBLJ9y5zsfZNvyA+6N17JPHVPMEApf7cz8ro080sMGk= X-Gm-Gg: ASbGncsx5O4lxPnr07DcAS5xj0y0DjiC7a+0tqeZB/G/oKSRyxhe10Nm3R6Z+UEPsIu G3trHcCFmaqcU0Hu2/EHNGaPbeoQcUIFbiug2nMvSdYSKwTQIG7VCGU5jOK6Di8ksG6g6q/PYWT J0RqEfxQllavwN3b4XdH7ewM/M0yCadw1OeECAP3pzR8WcVrZ0CSJoNC8/QQ9XGxjU2KeLURRsZ QB9rqhVOx3X2lnxpCXfzD362X19VUsZ1t2t8iaeJ4Yroj+yC9eP06HBvrBTzV85b861Ir+c+upN IInsCjwlod1o0RQFrOgqy55ULPo5C3wQ4j3FO9LiJHkiqZHGQ/QXAZjMxdBYa5fcSiW0rf9W/7G 8pMb8T6o06o1VlOu1sTVxaA0ZwflOl756mq0H8Xf2PWDRh7QyOnYmr1qhJHxlfuo/b0I8c6DNwf dfkz3e5SYxt2q5VWxABKzC X-Google-Smtp-Source: AGHT+IFAR6c195gOhTQz8dx6OF6n9ZtTYJ2jnLXbzOQvfTE9XO9dATUae/AlsEqPzIc2s5OhSaCgDQ== X-Received: by 2002:a05:600c:46cd:b0:475:dc5c:3a89 with SMTP id 5b1f17b1804b1-477c1136b7fmr175263115e9.34.1764154671907; Wed, 26 Nov 2025 02:57:51 -0800 (PST) Received: from ho-tower-lan.lan ([185.48.77.170]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4790ade13ddsm36991765e9.8.2025.11.26.02.57.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Nov 2025 02:57:50 -0800 (PST) From: James Clark Date: Wed, 26 Nov 2025 10:54:38 +0000 Subject: [PATCH v7 09/13] coresight: Interpret ETMv4 config with ATTR_CFG_GET_FLD() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251126-james-cs-syncfreq-v7-9-7fae5e0e5e16@linaro.org> References: <20251126-james-cs-syncfreq-v7-0-7fae5e0e5e16@linaro.org> In-Reply-To: <20251126-james-cs-syncfreq-v7-0-7fae5e0e5e16@linaro.org> To: Suzuki K Poulose , Mike Leach , Alexander Shishkin , Jonathan Corbet , Leo Yan , Randy Dunlap Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, James Clark X-Mailer: b4 0.14.0 Remove hard coded bitfield extractions and shifts and replace with ATTR_CFG_GET_FLD(). ETM4_CFG_BIT_BB was defined to give the register bit positions to userspace, TRCCONFIGR_BB should be used in the kernel so replace it. Reviewed-by: Leo Yan Reviewed-by: Mike Leach Signed-off-by: James Clark --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 44 ++++++++++--------= ---- 1 file changed, 19 insertions(+), 25 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/h= wtracing/coresight/coresight-etm4x-core.c index 2ec2ae1fef58..b457f182efbe 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -780,17 +781,17 @@ static int etm4_parse_event_config(struct coresight_d= evice *csdev, goto out; =20 /* Go from generic option to ETMv4 specifics */ - if (attr->config & BIT(ETM_OPT_CYCACC)) { + if (ATTR_CFG_GET_FLD(attr, cycacc)) { config->cfg |=3D TRCCONFIGR_CCI; /* TRM: Must program this for cycacc to work */ - cc_threshold =3D attr->config3 & ETM_CYC_THRESHOLD_MASK; + cc_threshold =3D ATTR_CFG_GET_FLD(attr, cc_threshold); if (!cc_threshold) cc_threshold =3D ETM_CYC_THRESHOLD_DEFAULT; if (cc_threshold < drvdata->ccitmin) cc_threshold =3D drvdata->ccitmin; config->ccctlr =3D cc_threshold; } - if (attr->config & BIT(ETM_OPT_TS)) { + if (ATTR_CFG_GET_FLD(attr, timestamp)) { /* * Configure timestamps to be emitted at regular intervals in * order to correlate instructions executed on different CPUs @@ -810,17 +811,17 @@ static int etm4_parse_event_config(struct coresight_d= evice *csdev, } =20 /* Only trace contextID when runs in root PID namespace */ - if ((attr->config & BIT(ETM_OPT_CTXTID)) && + if (ATTR_CFG_GET_FLD(attr, contextid1) && task_is_in_init_pid_ns(current)) /* bit[6], Context ID tracing bit */ config->cfg |=3D TRCCONFIGR_CID; =20 /* - * If set bit ETM_OPT_CTXTID2 in perf config, this asks to trace VMID - * for recording CONTEXTIDR_EL2. Do not enable VMID tracing if the - * kernel is not running in EL2. + * If set bit contextid2 in perf config, this asks to trace VMID for + * recording CONTEXTIDR_EL2. Do not enable VMID tracing if the kernel + * is not running in EL2. */ - if (attr->config & BIT(ETM_OPT_CTXTID2)) { + if (ATTR_CFG_GET_FLD(attr, contextid2)) { if (!is_kernel_in_hyp_mode()) { ret =3D -EINVAL; goto out; @@ -831,26 +832,22 @@ static int etm4_parse_event_config(struct coresight_d= evice *csdev, } =20 /* return stack - enable if selected and supported */ - if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack) + if (ATTR_CFG_GET_FLD(attr, retstack) && drvdata->retstack) /* bit[12], Return stack enable bit */ config->cfg |=3D TRCCONFIGR_RS; =20 /* - * Set any selected configuration and preset. - * - * This extracts the values of PMU_FORMAT_ATTR(configid) and PMU_FORMAT_A= TTR(preset) - * in the perf attributes defined in coresight-etm-perf.c. - * configid uses bits 63:32 of attr->config2, preset uses bits 3:0 of att= r->config. - * A zero configid means no configuration active, preset =3D 0 means no p= reset selected. + * Set any selected configuration and preset. A zero configid means no + * configuration active, preset =3D 0 means no preset selected. */ - if (attr->config2 & GENMASK_ULL(63, 32)) { - cfg_hash =3D (u32)(attr->config2 >> 32); - preset =3D attr->config & 0xF; + cfg_hash =3D ATTR_CFG_GET_FLD(attr, configid); + if (cfg_hash) { + preset =3D ATTR_CFG_GET_FLD(attr, preset); ret =3D cscfg_csdev_enable_active_config(csdev, cfg_hash, preset); } =20 /* branch broadcast - enable if selected and supported */ - if (attr->config & BIT(ETM_OPT_BRANCH_BROADCAST)) { + if (ATTR_CFG_GET_FLD(attr, branch_broadcast)) { if (!drvdata->trcbb) { /* * Missing BB support could cause silent decode errors @@ -859,7 +856,7 @@ static int etm4_parse_event_config(struct coresight_dev= ice *csdev, ret =3D -EINVAL; goto out; } else { - config->cfg |=3D BIT(ETM4_CFG_BIT_BB); + config->cfg |=3D TRCCONFIGR_BB; } } =20 @@ -1083,11 +1080,8 @@ static int etm4_disable_perf(struct coresight_device= *csdev, return -EINVAL; =20 etm4_disable_hw(drvdata); - /* - * The config_id occupies bits 63:32 of the config2 perf event attr - * field. If this is non-zero then we will have enabled a config. - */ - if (attr->config2 & GENMASK_ULL(63, 32)) + /* If configid is non-zero then we will have enabled a config. */ + if (ATTR_CFG_GET_FLD(attr, configid)) cscfg_csdev_disable_active_config(csdev); =20 /* --=20 2.34.1