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Wed, 26 Nov 2025 01:57:37 -0800 (PST) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3476a43ac07sm2042843a91.0.2025.11.26.01.57.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Nov 2025 01:57:36 -0800 (PST) From: Taniya Das Date: Wed, 26 Nov 2025 15:27:17 +0530 Subject: [PATCH v4 3/4] clk: qcom: Add TCSR clock driver for Kaanapali Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251126-gcc_kaanapali-v3-v4-3-0fe73d6898e9@oss.qualcomm.com> References: <20251126-gcc_kaanapali-v3-v4-0-0fe73d6898e9@oss.qualcomm.com> In-Reply-To: <20251126-gcc_kaanapali-v3-v4-0-0fe73d6898e9@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Taniya Das , Dmitry Baryshkov , Konrad Dybcio , Abel Vesa X-Mailer: b4 0.15-dev-aa3f6 X-Authority-Analysis: v=2.4 cv=PJgCOPqC c=1 sm=1 tr=0 ts=6926cf13 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=hY4tN0yg6o136M3hR0AA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTI2MDA4MSBTYWx0ZWRfX6GmcClT7laaH 5c19xljSxsfJ0iB2DDlRWVPuPT8C7gTYvM1QBDuEGiuKIJ51XSFep871j70zyHECsj0J4wkWSs7 UImsfwIUWPg6RXRs1Tb+kioxTXcFGOKWeaZhhpoDio0DvFeyep9/fdrZYpZRkinsz6A8E0zXsPX ToDfBFGq1tI/TUz5/hFwXL4Q4SXDndbRgpSy+gWcSk3EISORklAd8dSaZhkrPJRASxRbfyIPvpG lCnO6mg2oE8pfsqfabIpFPleYen+SYf8RpH4kHVcFARfufW0gXbu0aJEw3p3gGPL6zRQFAPRAwk bJBrYvjTYD8oRPuEIE3Mw6OvpGrxJJV/h3nCjeZhd7W0Tg/5l/5PsxI5LNpKHb2AwsKLNERr6af oBclqIRCxhBwb4aqhUe2n3PXSViqiw== X-Proofpoint-GUID: cP8tIlqkPzADD7KvshSw9wFQk8CFQbH- X-Proofpoint-ORIG-GUID: cP8tIlqkPzADD7KvshSw9wFQk8CFQbH- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-25_02,2025-11-25_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 suspectscore=0 adultscore=0 spamscore=0 malwarescore=0 clxscore=1015 phishscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511260081 Add the TCSR clock controller that provides the refclks on Kaanapali platform for PCIe, USB and UFS subsystems. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Signed-off-by: Taniya Das --- drivers/clk/qcom/Kconfig | 8 ++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/tcsrcc-kaanapali.c | 141 ++++++++++++++++++++++++++++++++= ++++ 3 files changed, 150 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index a284ba040b78ba2f7b7c7ead14023c0ec637f841..efaf32bb517e47be3da59410eca= 5332abe5bc25c 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -46,6 +46,14 @@ config CLK_GLYMUR_TCSRCC Support for the TCSR clock controller on GLYMUR devices. Say Y if you want to use peripheral devices such as USB/PCIe/EDP. =20 +config CLK_KAANAPALI_TCSRCC + tristate "Kaanapali TCSR Clock Controller" + depends on ARM64 || COMPILE_TEST + select QCOM_GDSC + help + Support for the TCSR clock controller on Kaanapali devices. + Say Y if you want to use peripheral devices such as PCIe, USB, UFS. + config CLK_X1E80100_CAMCC tristate "X1E80100 Camera Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 0ac8a9055a43230d848c6a0c1ac118c03c3e18d2..6e45410d572bdb9f088a32095fe= 78a81ba176c09 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_CLK_GFM_LPASS_SM8250) +=3D lpass-gfm-sm8250.o obj-$(CONFIG_CLK_GLYMUR_DISPCC) +=3D dispcc-glymur.o obj-$(CONFIG_CLK_GLYMUR_GCC) +=3D gcc-glymur.o obj-$(CONFIG_CLK_GLYMUR_TCSRCC) +=3D tcsrcc-glymur.o +obj-$(CONFIG_CLK_KAANAPALI_TCSRCC) +=3D tcsrcc-kaanapali.o obj-$(CONFIG_CLK_X1E80100_CAMCC) +=3D camcc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_DISPCC) +=3D dispcc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_GCC) +=3D gcc-x1e80100.o diff --git a/drivers/clk/qcom/tcsrcc-kaanapali.c b/drivers/clk/qcom/tcsrcc-= kaanapali.c new file mode 100644 index 0000000000000000000000000000000000000000..4da77367c9e035e036f63440dcf= 66a4e3a03ea84 --- /dev/null +++ b/drivers/clk/qcom/tcsrcc-kaanapali.c @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include + +#include + +#include "clk-branch.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" + +enum { + DT_BI_TCXO_PAD, +}; + +static struct clk_branch tcsr_pcie_0_clkref_en =3D { + .halt_reg =3D 0x15044, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x15044, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "tcsr_pcie_0_clkref_en", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_usb3_clkref_en =3D { + .halt_reg =3D 0x1504c, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x1504c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "tcsr_usb3_clkref_en", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO_PAD, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_ufs_clkref_en =3D { + .halt_reg =3D 0x15054, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x15054, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "tcsr_ufs_clkref_en", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO_PAD, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_usb2_clkref_en =3D { + .halt_reg =3D 0x1505c, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x1505c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "tcsr_usb2_clkref_en", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO_PAD, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *tcsr_cc_kaanapali_clocks[] =3D { + [TCSR_PCIE_0_CLKREF_EN] =3D &tcsr_pcie_0_clkref_en.clkr, + [TCSR_UFS_CLKREF_EN] =3D &tcsr_ufs_clkref_en.clkr, + [TCSR_USB2_CLKREF_EN] =3D &tcsr_usb2_clkref_en.clkr, + [TCSR_USB3_CLKREF_EN] =3D &tcsr_usb3_clkref_en.clkr, +}; + +static const struct regmap_config tcsr_cc_kaanapali_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x3d000, + .fast_io =3D true, +}; + +static const struct qcom_cc_desc tcsr_cc_kaanapali_desc =3D { + .config =3D &tcsr_cc_kaanapali_regmap_config, + .clks =3D tcsr_cc_kaanapali_clocks, + .num_clks =3D ARRAY_SIZE(tcsr_cc_kaanapali_clocks), +}; + +static const struct of_device_id tcsr_cc_kaanapali_match_table[] =3D { + { .compatible =3D "qcom,kaanapali-tcsr" }, + { } +}; +MODULE_DEVICE_TABLE(of, tcsr_cc_kaanapali_match_table); + +static int tcsr_cc_kaanapali_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &tcsr_cc_kaanapali_desc); +} + +static struct platform_driver tcsr_cc_kaanapali_driver =3D { + .probe =3D tcsr_cc_kaanapali_probe, + .driver =3D { + .name =3D "tcsr_cc-kaanapali", + .of_match_table =3D tcsr_cc_kaanapali_match_table, + }, +}; + +static int __init tcsr_cc_kaanapali_init(void) +{ + return platform_driver_register(&tcsr_cc_kaanapali_driver); +} +subsys_initcall(tcsr_cc_kaanapali_init); + +static void __exit tcsr_cc_kaanapali_exit(void) +{ + platform_driver_unregister(&tcsr_cc_kaanapali_driver); +} +module_exit(tcsr_cc_kaanapali_exit); + +MODULE_DESCRIPTION("QTI TCSR_CC Kaanapali Driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1