From nobody Mon Dec 1 23:09:41 2025 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B839033EB15 for ; Wed, 26 Nov 2025 17:36:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764178615; cv=none; b=eJVhPLZviTox/wU2iAlt+BUTp1GScE5gGE8L1Yx2t0F4wauVMZ7x5qPLalXBzX1r3wI7BdQRbYZDP1scfGMebr5ynLuULTqd3QI8eqdc+MwoEmJkwgFeesJTqWvLDf8lOLa5dPd8wj27gbKiKDxPCU7IQWwRmvF6+NauWbsNsR0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764178615; c=relaxed/simple; bh=35hEHjwEAu2u+NrlDnWa+uc4uMBasamSA3A1Kisq66o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DDMDjB5GwaY+PWZo6/JFF6ZlpTAqtdi05Nk4N5nPV0gF4yCWFkOPPTM/OdkoONBnTasjW9zRTpwkrdeMVCfV0sWUD/l6lr+4wwB1WQPuyH6pCTrZ0tNdDnBQ6Fhc49fgeeiOJnhgWDi5yl6oJc7uO90lP062PHrz3lPqu0V+xAA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=dbOe6nvT; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="dbOe6nvT" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 7027DC16A0D; Wed, 26 Nov 2025 17:36:29 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 37ED460721; Wed, 26 Nov 2025 17:36:52 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id C1501102F2334; Wed, 26 Nov 2025 18:36:48 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1764178610; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=8TfK+4PegTpbC0dzvRLmi5aNfYCQa5XXLe69RiPnQcY=; b=dbOe6nvTTRT3KyxTM0HZMVyjYxjsxEVyjrBR2sL0RV3JL/toUrH7apvFsou7CQSCyf+bVf Asoyscn89JIcI5txhm/zJ1Iu4GjPsKjKSIzB3sPyuWDxGYEbl2OWN2U91hd1+Xay2Lp+oY b3ZHwEyv9bzLzRGdcBj/3z7deDxy3PhUlKtAljDKtLoloZSrnf+C2LOgCnEAAAj2PIjGIE Mr9xnaDiR+swuF8PCQjwYvH5aUXC/gqV+NNzndsSGaPlZeJ/lIKYeI+Ei+tKoHo7l35nvL JALtExV+DFvkXaKBhRCoHlKl58B0+MLKkD7dhY8x9/fqK9C+I2D67PinkipMiA== From: "Kory Maincent (TI.com)" Date: Wed, 26 Nov 2025 18:35:44 +0100 Subject: [PATCH 02/21] dt-bindings: display: tilcdc: Add fifo-threshold property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251126-feature_tilcdc-v1-2-49b9ef2e3aa0@bootlin.com> References: <20251126-feature_tilcdc-v1-0-49b9ef2e3aa0@bootlin.com> In-Reply-To: <20251126-feature_tilcdc-v1-0-49b9ef2e3aa0@bootlin.com> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Russell King , Bartosz Golaszewski , Tony Lindgren , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec Cc: Markus Schneider-Pargmann , Luca Ceresoli , Louis Chauvet , Thomas Petazzoni , Miguel Gazquez , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-omap@vger.kernel.org, "Kory Maincent (TI.com)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Add the fifo-threshold property to control the DMA FIFO threshold level, which specifies the number of words that must be loaded before the DMA FIFO becomes ready. This property is needed to support the da850-evm board configuration which requires a non-default FIFO threshold value. Currently, this value is specified through the deprecated ti,tilcdc,panel binding. Adding this property to the tilcdc binding allows for proper configuration while migrating away from the non-standard panel binding. The default value is 8 words, with valid values being powers of 2 from 8 to 512. Related commit: 55da73fa7a68c ("ARM: dts: davinci: da850-evm: Increase fifo threshold") Signed-off-by: Kory Maincent (TI.com) --- Documentation/devicetree/bindings/display/tilcdc/tilcdc.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/display/tilcdc/tilcdc.yaml b= /Documentation/devicetree/bindings/display/tilcdc/tilcdc.yaml index 34ac1fd04d5c6..bf6d506e25e17 100644 --- a/Documentation/devicetree/bindings/display/tilcdc/tilcdc.yaml +++ b/Documentation/devicetree/bindings/display/tilcdc/tilcdc.yaml @@ -46,6 +46,13 @@ properties: The maximum pixel clock that can be supported by the lcd controller in KHz. =20 + fifo-threshold: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [8, 16, 32, 64, 128, 256, 512] + description: + Number of words loaded before the DMA fifo becomes ready. The default + value is 8. + blue-and-red-wiring: enum: [straight, crossed] description: --=20 2.43.0