From nobody Mon Dec 1 22:41:52 2025 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 897D030E85E for ; Wed, 26 Nov 2025 17:36:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764178614; cv=none; b=QTV12OwLUFwwJH713ccIqCNA+sTnNj+iDnQq8q8hwm/h8a1kfrGyvff/93X55owXHtRI2vPjtpxLWx2jPE/dktnoQ0HjLaoah4xyznh9BbiLrfX77eCtQjgl9yttpVd0nN+KqWAys5bF6NpeWJijndEBB3mMyQ4jUph+/7BaZvY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764178614; c=relaxed/simple; bh=NObLl9fDFrFZkTv9xsvJQK5vK4J1/jFJFVcI30Ygmfw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=euiFFG6gQbkTlJ5HR0xRICf3gx1ynE+aeX+AWISs7ZrIEnmO8BD0/HbS4B9EPSgkPPc201vvr0Zt1c08zQJtb/ll1Cx2FfOftbrT6H1/30xk6H3DLo2Exh0qAyh/+XIxqZac1bCfcO/ksiDzPcd3NLzZOftPQYxVtS/NcyOqeLs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=XdIHFCWM; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="XdIHFCWM" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id EED5AC16A0C; Wed, 26 Nov 2025 17:36:26 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id B41D560721; Wed, 26 Nov 2025 17:36:49 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id C6A24102F221D; Wed, 26 Nov 2025 18:36:45 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1764178608; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=0CUr9ddV3oZ41q3/D/0z/oo3oYkxXbRVdv8SyL1wMI0=; b=XdIHFCWMG+5JwqdNGZHvzcPTLjOUAqtIc13sFCqdx8WbFpzLBq7SdG5+3ABrAJ8zaffh5F tkcakLaIexbu6VluNW93m3bfPyk0TfF53m9C03x3trO4Uacq1qfZzewsxrv5K+BrLiC+WZ VDS74JMKtjMMvi+/Dkcfzet1BBW4jP23Z9t4SWYxNpEcFDv23hnIL5Jug3P9Sv3GD5AYYM vR4A3S477UtgpN6NysxxlAHkihiyW4fRxuk0fH7h9iFbQ5+O6OTy7ZIa5gwhz7zI391bbq I1AuNnFoS50wmEKc3LcPCiOu2zUlf+h+p4i1Oz0kvLA/x2t3qH4+tAhyhDC0PQ== From: "Kory Maincent (TI.com)" Date: Wed, 26 Nov 2025 18:35:43 +0100 Subject: [PATCH 01/21] dt-bindings: display: tilcdc: Convert to DT schema Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251126-feature_tilcdc-v1-1-49b9ef2e3aa0@bootlin.com> References: <20251126-feature_tilcdc-v1-0-49b9ef2e3aa0@bootlin.com> In-Reply-To: <20251126-feature_tilcdc-v1-0-49b9ef2e3aa0@bootlin.com> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Russell King , Bartosz Golaszewski , Tony Lindgren , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec Cc: Markus Schneider-Pargmann , Luca Ceresoli , Louis Chauvet , Thomas Petazzoni , Miguel Gazquez , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-omap@vger.kernel.org, "Kory Maincent (TI.com)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Convert the device tree binding documentation for tilcdc from plain text to DT binding schema. Signed-off-by: Kory Maincent (TI.com) --- .../devicetree/bindings/display/tilcdc/tilcdc.txt | 82 ------------------ .../devicetree/bindings/display/tilcdc/tilcdc.yaml | 96 ++++++++++++++++++= ++++ 2 files changed, 96 insertions(+), 82 deletions(-) diff --git a/Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt b/= Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt deleted file mode 100644 index 3b3d0bbfcfff4..0000000000000 --- a/Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt +++ /dev/null @@ -1,82 +0,0 @@ -Device-Tree bindings for tilcdc DRM driver - -Required properties: - - compatible: value should be one of the following: - - "ti,am33xx-tilcdc" for AM335x based boards - - "ti,da850-tilcdc" for DA850/AM18x/OMAP-L138 based boards - - interrupts: the interrupt number - - reg: base address and size of the LCDC device - -Recommended properties: - - ti,hwmods: Name of the hwmod associated to the LCDC - -Optional properties: - - max-bandwidth: The maximum pixels per second that the memory - interface / lcd controller combination can sustain - - max-width: The maximum horizontal pixel width supported by - the lcd controller. - - max-pixelclock: The maximum pixel clock that can be supported - by the lcd controller in KHz. - - blue-and-red-wiring: Recognized values "straight" or "crossed". - This property deals with the LCDC revision 2 (found on AM335x) - color errata [1]. - - "straight" indicates normal wiring that supports RGB565, - BGR888, and XBGR8888 color formats. - - "crossed" indicates wiring that has blue and red wires - crossed. This setup supports BGR565, RGB888 and XRGB8888 - formats. - - If the property is not present or its value is not recognized - the legacy mode is assumed. This configuration supports RGB565, - RGB888 and XRGB8888 formats. However, depending on wiring, the red - and blue colors are swapped in either 16 or 24-bit color modes. - -Optional nodes: - - - port/ports: to describe a connection to an external encoder. The - binding follows Documentation/devicetree/bindings/graph.txt and - supports a single port with a single endpoint. - - - See also Documentation/devicetree/bindings/display/tilcdc/panel.txt and - Documentation/devicetree/bindings/display/bridge/ti,tfp410.yaml for con= necting - tfp410 DVI encoder or lcd panel to lcdc - -[1] There is an errata about AM335x color wiring. For 16-bit color mode - the wires work as they should (LCD_DATA[0:4] is for Blue[3:7]), - but for 24 bit color modes the wiring of blue and red components is - crossed and LCD_DATA[0:4] is for Red[3:7] and LCD_DATA[11:15] is - for Blue[3-7]. For more details see section 3.1.1 in AM335x - Silicon Errata: - https://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNu= mber=3Dsprz360 - -Example: - - fb: fb@4830e000 { - compatible =3D "ti,am33xx-tilcdc", "ti,da850-tilcdc"; - reg =3D <0x4830e000 0x1000>; - interrupt-parent =3D <&intc>; - interrupts =3D <36>; - ti,hwmods =3D "lcdc"; - - blue-and-red-wiring =3D "crossed"; - - port { - lcdc_0: endpoint { - remote-endpoint =3D <&hdmi_0>; - }; - }; - }; - - tda19988: tda19988 { - compatible =3D "nxp,tda998x"; - reg =3D <0x70>; - - pinctrl-names =3D "default", "off"; - pinctrl-0 =3D <&nxp_hdmi_bonelt_pins>; - pinctrl-1 =3D <&nxp_hdmi_bonelt_off_pins>; - - port { - hdmi_0: endpoint { - remote-endpoint =3D <&lcdc_0>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/tilcdc/tilcdc.yaml b= /Documentation/devicetree/bindings/display/tilcdc/tilcdc.yaml new file mode 100644 index 0000000000000..34ac1fd04d5c6 --- /dev/null +++ b/Documentation/devicetree/bindings/display/tilcdc/tilcdc.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/tilcdc/tilcdc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI LCD Controller, found on AM335x, DA850, AM18x and OMAP-L138 + +maintainers: + - Kory Maincent + +properties: + compatible: + enum: + - ti,am33xx-tilcdc + - ti,da850-tilcdc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + port: + $ref: /schemas/graph.yaml#/properties/port + + ti,hwmods: + $ref: /schemas/types.yaml#/definitions/string + description: + Name of the hwmod associated to the LCDC + + max-bandwidth: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The maximum pixels per second that the memory interface / lcd + controller combination can sustain + + max-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The maximum horizontal pixel width supported by the lcd controller. + + max-pixelclock: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The maximum pixel clock that can be supported by the lcd controller + in KHz. + + blue-and-red-wiring: + enum: [straight, crossed] + description: + This property deals with the LCDC revision 2 (found on AM335x) + color errata [1]. + - "straight" indicates normal wiring that supports RGB565, + BGR888, and XBGR8888 color formats. + - "crossed" indicates wiring that has blue and red wires + crossed. This setup supports BGR565, RGB888 and XRGB8888 + formats. + - If the property is not present or its value is not recognized + the legacy mode is assumed. This configuration supports RGB565, + RGB888 and XRGB8888 formats. However, depending on wiring, the red + and blue colors are swapped in either 16 or 24-bit color modes. + + [1] There is an errata about AM335x color wiring. For 16-bit color + mode the wires work as they should (LCD_DATA[0:4] is for Blue[3:7]), + but for 24 bit color modes the wiring of blue and red components is + crossed and LCD_DATA[0:4] is for Red[3:7] and LCD_DATA[11:15] is + for Blue[3-7]. For more details see section 3.1.1 in AM335x + Silicon Errata + https://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratur= eNumber=3Dsprz360 + +required: + - compatible + - interrupts + - reg + - port + +additionalProperties: false + +examples: + - | + tilcdc: tilcdc@4830e000 { + compatible =3D "ti,am33xx-tilcdc"; + reg =3D <0x4830e000 0x1000>; + interrupt-parent =3D <&intc>; + interrupts =3D <36>; + ti,hwmods =3D "lcdc"; + + blue-and-red-wiring =3D "crossed"; + + port { + lcdc_0: endpoint { + remote-endpoint =3D <&hdmi_0>; + }; + }; + }; --=20 2.43.0 From nobody Mon Dec 1 22:41:52 2025 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B839033EB15 for ; Wed, 26 Nov 2025 17:36:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764178615; cv=none; b=eJVhPLZviTox/wU2iAlt+BUTp1GScE5gGE8L1Yx2t0F4wauVMZ7x5qPLalXBzX1r3wI7BdQRbYZDP1scfGMebr5ynLuULTqd3QI8eqdc+MwoEmJkwgFeesJTqWvLDf8lOLa5dPd8wj27gbKiKDxPCU7IQWwRmvF6+NauWbsNsR0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764178615; c=relaxed/simple; bh=35hEHjwEAu2u+NrlDnWa+uc4uMBasamSA3A1Kisq66o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DDMDjB5GwaY+PWZo6/JFF6ZlpTAqtdi05Nk4N5nPV0gF4yCWFkOPPTM/OdkoONBnTasjW9zRTpwkrdeMVCfV0sWUD/l6lr+4wwB1WQPuyH6pCTrZ0tNdDnBQ6Fhc49fgeeiOJnhgWDi5yl6oJc7uO90lP062PHrz3lPqu0V+xAA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=dbOe6nvT; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="dbOe6nvT" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 7027DC16A0D; Wed, 26 Nov 2025 17:36:29 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 37ED460721; Wed, 26 Nov 2025 17:36:52 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id C1501102F2334; Wed, 26 Nov 2025 18:36:48 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1764178610; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=8TfK+4PegTpbC0dzvRLmi5aNfYCQa5XXLe69RiPnQcY=; b=dbOe6nvTTRT3KyxTM0HZMVyjYxjsxEVyjrBR2sL0RV3JL/toUrH7apvFsou7CQSCyf+bVf Asoyscn89JIcI5txhm/zJ1Iu4GjPsKjKSIzB3sPyuWDxGYEbl2OWN2U91hd1+Xay2Lp+oY b3ZHwEyv9bzLzRGdcBj/3z7deDxy3PhUlKtAljDKtLoloZSrnf+C2LOgCnEAAAj2PIjGIE Mr9xnaDiR+swuF8PCQjwYvH5aUXC/gqV+NNzndsSGaPlZeJ/lIKYeI+Ei+tKoHo7l35nvL JALtExV+DFvkXaKBhRCoHlKl58B0+MLKkD7dhY8x9/fqK9C+I2D67PinkipMiA== From: "Kory Maincent (TI.com)" Date: Wed, 26 Nov 2025 18:35:44 +0100 Subject: [PATCH 02/21] dt-bindings: display: tilcdc: Add fifo-threshold property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251126-feature_tilcdc-v1-2-49b9ef2e3aa0@bootlin.com> References: <20251126-feature_tilcdc-v1-0-49b9ef2e3aa0@bootlin.com> In-Reply-To: <20251126-feature_tilcdc-v1-0-49b9ef2e3aa0@bootlin.com> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Russell King , Bartosz Golaszewski , Tony Lindgren , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec Cc: Markus Schneider-Pargmann , Luca Ceresoli , Louis Chauvet , Thomas Petazzoni , Miguel Gazquez , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-omap@vger.kernel.org, "Kory Maincent (TI.com)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Add the fifo-threshold property to control the DMA FIFO threshold level, which specifies the number of words that must be loaded before the DMA FIFO becomes ready. This property is needed to support the da850-evm board configuration which requires a non-default FIFO threshold value. Currently, this value is specified through the deprecated ti,tilcdc,panel binding. Adding this property to the tilcdc binding allows for proper configuration while migrating away from the non-standard panel binding. The default value is 8 words, with valid values being powers of 2 from 8 to 512. Related commit: 55da73fa7a68c ("ARM: dts: davinci: da850-evm: Increase fifo threshold") Signed-off-by: Kory Maincent (TI.com) --- Documentation/devicetree/bindings/display/tilcdc/tilcdc.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/display/tilcdc/tilcdc.yaml b= /Documentation/devicetree/bindings/display/tilcdc/tilcdc.yaml index 34ac1fd04d5c6..bf6d506e25e17 100644 --- a/Documentation/devicetree/bindings/display/tilcdc/tilcdc.yaml +++ b/Documentation/devicetree/bindings/display/tilcdc/tilcdc.yaml @@ -46,6 +46,13 @@ properties: The maximum pixel clock that can be supported by the lcd controller in KHz. =20 + fifo-threshold: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [8, 16, 32, 64, 128, 256, 512] + description: + Number of words loaded before the DMA fifo becomes ready. The default + value is 8. + blue-and-red-wiring: enum: [straight, crossed] description: --=20 2.43.0 From nobody Mon Dec 1 22:41:52 2025 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E11E63115A6; Wed, 26 Nov 2025 17:36:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764178619; cv=none; b=hWHAcNlM1hOvTc5ykdBNSN1Ds7WbLAARfRxSSOto8sHbAcUgYnkMAij42rwey5NamKC809MgL9df9U8Cg9aEWSMkeNM1cQdsRk6UN82JqkUxUM8MFrHMVvcbNIr80N7SkoC1rQlX+/dxXZsKm/AIs9+UCzHiNKhOZu6BmUvhLc4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764178619; c=relaxed/simple; bh=pd0fwM8OpssesecVe5jYsKCLeoyXlOaIEtG7sseqEuY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=N5nqemjWYlmAUSM7xlVUVnGFvnVHWNzOnE0rV0XgCcYOvyYPeRvBlslF9eHTCINZVN7RD/B1bCoGF5B+p6kcILBLGO1fDyn2J+wv3EVnyB/hLknNUIrfL+Xb+MPp+nBhLH9Zm/RuHS9tylBbiBNhB3WwbeSXlpm4Sgeha5VZlJY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=oAhKwQJb; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="oAhKwQJb" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 270AF1A1D86; Wed, 26 Nov 2025 17:36:55 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id EE4BB60721; Wed, 26 Nov 2025 17:36:54 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 484F2102F1D8D; Wed, 26 Nov 2025 18:36:51 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1764178613; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=i06U48V1QlfdC71Az6GT0AOQaJkHqXg7US8ufDzb8no=; b=oAhKwQJbXv1B8OIDDEkR/Pl5h1rjaKwT0MbKkEtkULn2G/7yxDc7yOGnNLXZN3Xs7Fptjq tunuXn4gCrA3lX64/cG3BjB9z6L/rklyyo1Bo7QcJMUAhDyqV2HQqA8dz9XtvMR+2Wx33m lgeiU788HZYm8Q7XQUkwg7jeMlWbx2g313bGuC/el00k3X4ZsC2n/k/Wx1pVTcaqlcEzRQ N38WyJ94yc4AslbZJ/D2TKdVLQcY/jBmcofuhVhsqQ16xARbMkwdKNAJpl6SiSFeXE8YGA gdSKgIeSjfoQE0xBo1Aly43VYA8Jg5PdaYzQcdayRqmGTHVItN/VHwqX/2n2qg== From: "Kory Maincent (TI.com)" Date: Wed, 26 Nov 2025 18:35:45 +0100 Subject: [PATCH 03/21] drm/tilcdc: Remove simulate_vesa_sync flag Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251126-feature_tilcdc-v1-3-49b9ef2e3aa0@bootlin.com> References: <20251126-feature_tilcdc-v1-0-49b9ef2e3aa0@bootlin.com> In-Reply-To: <20251126-feature_tilcdc-v1-0-49b9ef2e3aa0@bootlin.com> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Russell King , Bartosz Golaszewski , Tony Lindgren , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec Cc: Markus Schneider-Pargmann , Luca Ceresoli , Louis Chauvet , Thomas Petazzoni , Miguel Gazquez , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-omap@vger.kernel.org, "Kory Maincent (TI.com)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The tilcdc hardware does not generate VESA-compliant sync signals. It aligns the vertical sync (VS) on the second edge of the horizontal sync (HS) instead of the first edge. To compensate for this hardware behavior, the driver applies a timing adjustment in mode_fixup(). Previously, this adjustment was conditional based on the simulate_vesa_sync flag, which was only set when using external encoders. This appears problematic because: 1. The timing adjustment seems needed for the hardware behavior regardless of whether an external encoder is used 2. The external encoder infrastructure is driver-specific and being removed due to design issues 3. Boards using tilcdc without bridges (e.g., am335x-evm, am335x-evmsk) may not be getting the necessary timing adjustments Remove the simulate_vesa_sync flag and apply the VESA sync timing adjustment unconditionally, ensuring consistent behavior across all configurations. While it's unclear if the previous conditional behavior was causing actual issues, the unconditional adjustment better reflects the hardware's characteristics. Signed-off-by: Kory Maincent (TI.com) --- Only few board currently use tilcdc not associated to a bridge like the am335x_evm or the am335x-evmsk. --- drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 16 ---------------- drivers/gpu/drm/tilcdc/tilcdc_drv.h | 2 -- drivers/gpu/drm/tilcdc/tilcdc_external.c | 1 - 3 files changed, 19 deletions(-) diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c b/drivers/gpu/drm/tilcdc/= tilcdc_crtc.c index 52c95131af5af..b06b1453db2dd 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c @@ -47,9 +47,6 @@ struct tilcdc_crtc { =20 struct drm_framebuffer *next_fb; =20 - /* Only set if an external encoder is connected */ - bool simulate_vesa_sync; - int sync_lost_count; bool frame_intact; struct work_struct recover_work; @@ -642,11 +639,6 @@ static bool tilcdc_crtc_mode_fixup(struct drm_crtc *cr= tc, const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) { - struct tilcdc_crtc *tilcdc_crtc =3D to_tilcdc_crtc(crtc); - - if (!tilcdc_crtc->simulate_vesa_sync) - return true; - /* * tilcdc does not generate VESA-compliant sync but aligns * VS on the second edge of HS instead of first edge. @@ -866,14 +858,6 @@ void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc, tilcdc_crtc->info =3D info; } =20 -void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc, - bool simulate_vesa_sync) -{ - struct tilcdc_crtc *tilcdc_crtc =3D to_tilcdc_crtc(crtc); - - tilcdc_crtc->simulate_vesa_sync =3D simulate_vesa_sync; -} - void tilcdc_crtc_update_clk(struct drm_crtc *crtc) { struct drm_device *dev =3D crtc->dev; diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.h b/drivers/gpu/drm/tilcdc/t= ilcdc_drv.h index 58b276f82a669..3aba3a1155ba0 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_drv.h +++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.h @@ -160,8 +160,6 @@ irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc); void tilcdc_crtc_update_clk(struct drm_crtc *crtc); void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc, const struct tilcdc_panel_info *info); -void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc, - bool simulate_vesa_sync); void tilcdc_crtc_shutdown(struct drm_crtc *crtc); void tilcdc_crtc_destroy(struct drm_crtc *crtc); int tilcdc_crtc_update_fb(struct drm_crtc *crtc, diff --git a/drivers/gpu/drm/tilcdc/tilcdc_external.c b/drivers/gpu/drm/til= cdc/tilcdc_external.c index 3b86d002ef62e..da755a411d9ff 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_external.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_external.c @@ -80,7 +80,6 @@ int tilcdc_add_component_encoder(struct drm_device *ddev) return -ENODEV; =20 /* Only tda998x is supported at the moment. */ - tilcdc_crtc_set_simulate_vesa_sync(priv->crtc, true); tilcdc_crtc_set_panel_info(priv->crtc, &panel_info_tda998x); =20 return 0; --=20 2.43.0 From nobody Mon Dec 1 22:41:52 2025 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 75589341050 for ; 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bh=/0rPK6beH6AckUJmL2vrwOQlS80WMvwhCKTP9WHJs4k=; b=kdjWgvyTz00gcyMZ6nHqPphHqp8JXUsfKKrV8SynMj3/cweCesoFg5Y3Uu2GEpEuMK68Z+ +7K0nb55DueYUOtLI3SvfbOgqcfcf9keAfKvszVCp7Cas6SHnuzNkcRFwBVBTrpSu+351Q xNI+SR4KfG0DHb6u9ycsBmXONtaetbrrD4oar1sH0+A0Gy23dMORwJ6NrYrBO9oAiqQpeV KKvA8dO5TvEhhf59Moiu4cSqi3ByZy9TF+0mC2i0OCdRrjAzNj6QgSRZmbXORo6avc7K+j OYv5XrrOq4nbwg8XefASzfwdAy6LoalgC6iBe1eacbjBr6gZdHboGNjSNn3KLQ== From: "Kory Maincent (TI.com)" Date: Wed, 26 Nov 2025 18:35:46 +0100 Subject: [PATCH 04/21] drm/tilcdc: Add support for DRM bus flags and simplify panel config Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251126-feature_tilcdc-v1-4-49b9ef2e3aa0@bootlin.com> References: <20251126-feature_tilcdc-v1-0-49b9ef2e3aa0@bootlin.com> In-Reply-To: <20251126-feature_tilcdc-v1-0-49b9ef2e3aa0@bootlin.com> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Russell King , Bartosz Golaszewski , Tony Lindgren , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec Cc: Markus Schneider-Pargmann , Luca Ceresoli , Louis Chauvet , Thomas Petazzoni , Miguel Gazquez , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-omap@vger.kernel.org, "Kory Maincent (TI.com)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Migrate CRTC mode configuration to use standard DRM bus flags in preparation for removing the tilcdc_panel driver and its custom tilcdc_panel_info structure. Add support for DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE and DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE flags to control pixel clock and sync signal edge polarity, while maintaining backward compatibility with the existing tilcdc panel info structure. Simplify several hardware parameters by setting them to fixed defaults based on common usage across existing device trees: - DMA burst size: 16 (previously configurable via switch statement) - AC bias frequency: 255 (previously panel-specific) - FIFO DMA request delay: 128 (previously panel-specific) These parameters show no variation in real-world usage, so hardcoding them simplifies the driver without losing functionality. Preserve FIFO threshold configurability by adding a new "fifo-threshold" device tree property at the display controller level, as this parameter varies across different display configurations in existing device trees. Signed-off-by: Kory Maincent (TI.com) --- drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 48 ++++++++++++++------------------= ---- drivers/gpu/drm/tilcdc/tilcdc_drv.c | 2 ++ drivers/gpu/drm/tilcdc/tilcdc_drv.h | 2 ++ 3 files changed, 22 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c b/drivers/gpu/drm/tilcdc/= tilcdc_crtc.c index b06b1453db2dd..1b5475c48f6ad 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c @@ -285,27 +285,15 @@ static void tilcdc_crtc_set_mode(struct drm_crtc *crt= c) =20 /* Configure the Burst Size and fifo threshold of DMA: */ reg =3D tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770; - switch (info->dma_burst_sz) { - case 1: - reg |=3D LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_1); - break; - case 2: - reg |=3D LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_2); - break; - case 4: - reg |=3D LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_4); - break; - case 8: - reg |=3D LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_8); - break; - case 16: - reg |=3D LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16); - break; - default: - dev_err(dev->dev, "invalid burst size\n"); - return; + /* Use 16 bit DMA burst size by default */ + reg |=3D LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16); + if (priv->fifo_th) { + int fifo_th_val =3D const_ilog2(priv->fifo_th) - 3; + + reg |=3D (fifo_th_val << 8); + } else { + reg |=3D (info->fifo_th << 8); } - reg |=3D (info->fifo_th << 8); tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg); =20 /* Configure timings: */ @@ -321,8 +309,8 @@ static void tilcdc_crtc_set_mode(struct drm_crtc *crtc) =20 /* Set AC Bias Period and Number of Transitions per Interrupt: */ reg =3D tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00; - reg |=3D LCDC_AC_BIAS_FREQUENCY(info->ac_bias) | - LCDC_AC_BIAS_TRANSITIONS_PER_INT(info->ac_bias_intrpt); + /* Use 255 AC Bias Pin Frequency by default */ + reg |=3D LCDC_AC_BIAS_FREQUENCY(255); =20 /* * subtract one from hfp, hbp, hsw because the hardware uses @@ -392,20 +380,20 @@ static void tilcdc_crtc_set_mode(struct drm_crtc *crt= c) return; } } - reg |=3D info->fdd << 12; + /* Use 128 FIFO DMA Request Delay by default */ + reg |=3D 128 << 12; tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg); =20 - if (info->invert_pxl_clk) + if (info->invert_pxl_clk || + mode->flags =3D=3D DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) + tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK); else tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK); =20 - if (info->sync_ctrl) - tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL); - else - tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL); - - if (info->sync_edge) + tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL); + if (info->sync_edge || + mode->flags =3D=3D DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE) tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE); else tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE); diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.c b/drivers/gpu/drm/tilcdc/t= ilcdc_drv.c index 3dcbec312bacb..76eb336b5d4e7 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_drv.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.c @@ -309,6 +309,8 @@ static int tilcdc_init(const struct drm_driver *ddrv, s= truct device *dev) =20 DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock); =20 + of_property_read_u32(node, "fifo-threshold", &priv->fifo_th); + ret =3D tilcdc_crtc_create(ddev); if (ret < 0) { dev_err(dev, "failed to create crtc\n"); diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.h b/drivers/gpu/drm/tilcdc/t= ilcdc_drv.h index 3aba3a1155ba0..79078b4ae7393 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_drv.h +++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.h @@ -61,6 +61,8 @@ struct tilcdc_drm_private { */ uint32_t max_width; =20 + u32 fifo_th; + /* Supported pixel formats */ const uint32_t *pixelformats; uint32_t num_pixelformats; --=20 2.43.0 From nobody Mon Dec 1 22:41:52 2025 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9244E341AAF; Wed, 26 Nov 2025 17:37:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; 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spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="01lxaJvy" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 2F2551A1D85; Wed, 26 Nov 2025 17:37:01 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 0359460721; Wed, 26 Nov 2025 17:37:01 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id E57BA102F22B1; Wed, 26 Nov 2025 18:36:56 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1764178619; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=IJWtf2kIy8lCBpcz/JyBziECbeFa7hVjHuwMzNqnPPg=; b=01lxaJvy4NvnD7Bd7na8RY3i95UleIWUh8amKU6GPWbeGPSOgB6sIoOBbKxdQPfJvJuvAg B4gll/zh9mLakH7nQjwwJ9dPhtOCmGs+4uIVsaVx+26avrGtGArYrNAR72Mxg/iTZcEGdI 4SF3dWBYfcrC1hj7IQnDBQatbJ4BM10+4yJSSGFUOBSTE8GRwSYPZCMvTo7IVV2wBky1Xo thBSdQwQR5wp9SYaDT9g/AjY7xzr8fqaRPYB1PvS2YUTui3bfSWKoarRBGgqcTXUTERybS XaJLTRjpIJYpVVzuOSoN0EFVeddiy8URdVKQ1UyxCx0gHYvLxQRJQF1C7cSNcw== From: "Kory Maincent (TI.com)" Date: Wed, 26 Nov 2025 18:35:47 +0100 Subject: [PATCH 05/21] ARM: dts: omap: Bind panel to panel-dpi instead of ti,tilcdc,panel driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251126-feature_tilcdc-v1-5-49b9ef2e3aa0@bootlin.com> References: <20251126-feature_tilcdc-v1-0-49b9ef2e3aa0@bootlin.com> In-Reply-To: <20251126-feature_tilcdc-v1-0-49b9ef2e3aa0@bootlin.com> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Russell King , Bartosz Golaszewski , Tony Lindgren , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec Cc: Markus Schneider-Pargmann , Luca Ceresoli , Louis Chauvet , Thomas Petazzoni , Miguel Gazquez , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-omap@vger.kernel.org, "Kory Maincent (TI.com)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Use panel-dpi driver instead of the deprecated tilcdc-panel driver in preparation for removing the tilcdc-panel driver and binding. Signed-off-by: Kory Maincent (TI.com) --- This patch is not tested. It would be nice if someone with one of this board could test and validate it. --- arch/arm/boot/dts/ti/davinci/da850-evm.dts | 26 +++++++++++++----------= --- arch/arm/boot/dts/ti/omap/am335x-guardian.dts | 25 +++++++++--------------= -- arch/arm/boot/dts/ti/omap/am335x-pdu001.dts | 21 ++++++++++----------- arch/arm/boot/dts/ti/omap/am335x-pepper.dts | 22 +++++++++++----------- arch/arm/boot/dts/ti/omap/am335x-sbc-t335.dts | 25 +++++++++++++----------= -- arch/arm/boot/dts/ti/omap/am335x-sl50.dts | 25 ++++++++++++-----------= -- 6 files changed, 68 insertions(+), 76 deletions(-) diff --git a/arch/arm/boot/dts/ti/davinci/da850-evm.dts b/arch/arm/boot/dts= /ti/davinci/da850-evm.dts index 38a191fb04149..79cca1f6205ef 100644 --- a/arch/arm/boot/dts/ti/davinci/da850-evm.dts +++ b/arch/arm/boot/dts/ti/davinci/da850-evm.dts @@ -40,7 +40,7 @@ backlight: backlight-pwm { }; =20 panel { - compatible =3D "ti,tilcdc,panel"; + compatible =3D "panel-dpi"; pinctrl-names =3D "default"; pinctrl-0 =3D <&lcd_pins>; /* @@ -50,17 +50,10 @@ panel { */ status =3D "okay"; enable-gpios =3D <&gpio 40 GPIO_ACTIVE_HIGH>; /* lcd_panel_pwr */ - - panel-info { - ac-bias =3D <255>; - ac-bias-intrpt =3D <0>; - dma-burst-sz =3D <16>; - bpp =3D <16>; - fdd =3D <0x80>; - sync-edge =3D <0>; - sync-ctrl =3D <1>; - raster-order =3D <0>; - fifo-th =3D <1>; + port { + panel_in: endpoint { + remote-endpoint =3D <&lcdc_out>; + }; }; =20 display-timings { @@ -222,6 +215,13 @@ &rtc0 { }; =20 &lcdc { + fifo-threshold =3D <16>; + + port { + lcdc_out: endpoint { + remote-endpoint =3D <&panel_in>; + }; + }; status =3D "okay"; }; =20 @@ -459,7 +459,7 @@ &vpif { pinctrl-0 =3D <&vpif_capture_pins>, <&vpif_display_pins>; /* * The vpif and the LCD are mutually exclusive. - * To enable VPIF, disable the ti,tilcdc,panel then + * To enable VPIF, disable the panel-dpi then * change the status below to 'okay' */ status =3D "disabled"; diff --git a/arch/arm/boot/dts/ti/omap/am335x-guardian.dts b/arch/arm/boot/= dts/ti/omap/am335x-guardian.dts index 4b070e634b281..f38ce9be2c106 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-guardian.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-guardian.dts @@ -68,10 +68,15 @@ gpio-poweroff { }; =20 panel { - compatible =3D "ti,tilcdc,panel"; + compatible =3D "panel-dpi"; pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <&lcd_pins_default &lcd_disen_pins>; pinctrl-1 =3D <&lcd_pins_sleep>; + port { + panel_in: endpoint { + remote-endpoint =3D <&lcdc_out>; + }; + }; =20 display-timings { timing-320x240 { @@ -86,21 +91,9 @@ timing-320x240 { clock-frequency =3D <9000000>; hsync-active =3D <0>; vsync-active =3D <0>; + pixelclk-active =3D <1>; }; }; - panel-info { - ac-bias =3D <255>; - ac-bias-intrpt =3D <0>; - dma-burst-sz =3D <16>; - bpp =3D <24>; - bus-width =3D <16>; - fdd =3D <0x80>; - sync-edge =3D <0>; - sync-ctrl =3D <1>; - raster-order =3D <0>; - fifo-th =3D <0>; - }; - }; =20 guardian_beeper: pwm-7 { @@ -265,8 +258,8 @@ &lcdc { blue-and-red-wiring =3D "crossed"; status =3D "okay"; port { - lcdc_0: endpoint@0 { - remote-endpoint =3D <0>; + lcdc_out: endpoint@0 { + remote-endpoint =3D <&panel_in>; }; }; }; diff --git a/arch/arm/boot/dts/ti/omap/am335x-pdu001.dts b/arch/arm/boot/dt= s/ti/omap/am335x-pdu001.dts index c9ccb9de21ad7..2c5229d05ade7 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-pdu001.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-pdu001.dts @@ -50,20 +50,14 @@ lis3_reg: fixedregulator@1 { }; =20 panel { - compatible =3D "ti,tilcdc,panel"; + compatible =3D "panel-dpi"; status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&lcd_pins_s0>; - panel-info { - ac-bias =3D <255>; - ac-bias-intrpt =3D <0>; - dma-burst-sz =3D <16>; - bpp =3D <16>; - fdd =3D <0x80>; - sync-edge =3D <0>; - sync-ctrl =3D <1>; - raster-order =3D <0>; - fifo-th =3D <0>; + port { + panel_in: endpoint { + remote-endpoint =3D <&lcdc_out>; + }; }; =20 display-timings { @@ -395,6 +389,11 @@ &rtc { =20 &lcdc { status =3D "okay"; + port { + lcdc_out: endpoint { + remote-endpoint =3D <&panel_in>; + }; + }; }; =20 &elm { diff --git a/arch/arm/boot/dts/ti/omap/am335x-pepper.dts b/arch/arm/boot/dt= s/ti/omap/am335x-pepper.dts index e7d561a527fdd..2760c0eab50c2 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-pepper.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-pepper.dts @@ -31,7 +31,7 @@ leds: user-leds-pins { }; =20 panel: lcd_panel { - compatible =3D "ti,tilcdc,panel"; + compatible =3D "panel-dpi"; }; =20 sound: sound_iface { @@ -189,16 +189,10 @@ &panel { status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&lcd_pins>; - panel-info { - ac-bias =3D <255>; - ac-bias-intrpt =3D <0>; - dma-burst-sz =3D <16>; - bpp =3D <32>; - fdd =3D <0x80>; - sync-edge =3D <0>; - sync-ctrl =3D <1>; - raster-order =3D <0>; - fifo-th =3D <0>; + port { + panel_in: endpoint { + remote-endpoint =3D <&lcdc_out>; + }; }; display-timings { native-mode =3D <&timing0>; @@ -214,12 +208,18 @@ timing0: timing-480x272 { vsync-len =3D <10>; hsync-active =3D <1>; vsync-active =3D <1>; + pixelclk-active =3D <1>; }; }; }; =20 &lcdc { status =3D "okay"; + port { + lcdc_out: endpoint { + remote-endpoint =3D <&panel_in>; + }; + }; }; =20 &am33xx_pinmux { diff --git a/arch/arm/boot/dts/ti/omap/am335x-sbc-t335.dts b/arch/arm/boot/= dts/ti/omap/am335x-sbc-t335.dts index 2841e95d9a094..25ee855dd21a7 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-sbc-t335.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-sbc-t335.dts @@ -13,23 +13,17 @@ / { =20 /* DRM display driver */ panel { - compatible =3D "ti,tilcdc,panel"; + compatible =3D "panel-dpi"; status =3D "okay"; pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <&lcd_pins_default>; pinctrl-1 =3D <&lcd_pins_sleep>; - - panel-info { - ac-bias =3D <255>; - ac-bias-intrpt =3D <0>; - dma-burst-sz =3D <16>; - bpp =3D <32>; - fdd =3D <0x80>; - sync-edge =3D <0>; - sync-ctrl =3D <1>; - raster-order =3D <0>; - fifo-th =3D <0>; + port { + panel_in: endpoint { + remote-endpoint =3D <&lcdc_out>; + }; }; + display-timings { /* Timing selection performed by U-Boot */ timing0: lcd {/* 800x480p62 */ @@ -44,6 +38,7 @@ timing0: lcd {/* 800x480p62 */ vsync-len =3D <2>; hsync-active =3D <1>; vsync-active =3D <1>; + pixelclk-active =3D <1>; }; timing1: dvi { /* 1024x768p60 */ clock-frequency =3D <65000000>; @@ -57,6 +52,7 @@ timing1: dvi { /* 1024x768p60 */ vsync-len =3D <6>; hsync-active =3D <0>; vsync-active =3D <0>; + pixelclk-active =3D <1>; }; }; }; @@ -173,4 +169,9 @@ lcd-ena-hog { /* Display */ &lcdc { status =3D "okay"; + port { + lcdc_out: endpoint { + remote-endpoint =3D <&panel_in>; + }; + }; }; diff --git a/arch/arm/boot/dts/ti/omap/am335x-sl50.dts b/arch/arm/boot/dts/= ti/omap/am335x-sl50.dts index f3524e5ee43e2..b4b2b6d18d646 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-sl50.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-sl50.dts @@ -123,22 +123,14 @@ audio_mclk: audio_mclk_gate@0 { }; =20 panel: lcd_panel { - compatible =3D "ti,tilcdc,panel"; + compatible =3D "panel-dpi"; pinctrl-names =3D "default"; pinctrl-0 =3D <&lcd_pins>; =20 - panel-info { - ac-bias =3D <255>; - ac-bias-intrpt =3D <0>; - dma-burst-sz =3D <16>; - bpp =3D <16>; - fdd =3D <0x80>; - tft-alt-mode =3D <0>; - mono-8bit-mode =3D <0>; - sync-edge =3D <0>; - sync-ctrl =3D <1>; - raster-order =3D <0>; - fifo-th =3D <0>; + port { + panel_in: endpoint { + remote-endpoint =3D <&lcdc_out>; + }; }; =20 display-timings { @@ -157,6 +149,8 @@ timing0: 960x128 { vfront-porch =3D <8>; vsync-len =3D <4>; vsync-active =3D <0>; + + pixelclk-active =3D <1>; }; }; }; @@ -711,6 +705,11 @@ &ehrpwm1 { =20 &lcdc { status =3D "okay"; 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Wed, 26 Nov 2025 17:37:04 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id E28F4102F22D9; Wed, 26 Nov 2025 18:36:59 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1764178622; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=EWslL5MJAu1ktwPaDyDYlweDV4/0Xu50P9NpGLLvPzI=; b=urmWOWiOCRBQAaoKMUKHRNe7j5UlKQhDEabtHMlCvM1TGAhlLuB+6X45QYYWZNSKGwwm69 l3PZTZjW3W6qIfDfh/qnPs3VW+hLmQ+MfuadSI3knL03/q0LZ1eM5N8kx7JkuyjppmOTc8 b9GVdtvZ6b20OoB/85QkDEDzmcDujK+oYN24M5A/fLSuGuVdh4NdEhYkUc5WnuO2mqggJa 3vEk7KOmZQGFpmcX15aegIJY2/WRrOq6pQDQMhlUyw8G5TttJqc7qvbarJ9o2r7csdbJ/H Jy8lJW2nADY63oCd7wPItAFFyEpdjeh5fWz6eH8nur/0b2LUpJAJZv24W/wh8Q== From: "Kory Maincent (TI.com)" Date: Wed, 26 Nov 2025 18:35:48 +0100 Subject: [PATCH 06/21] dt-bindings: display: tilcdc: Remove panel binding Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251126-feature_tilcdc-v1-6-49b9ef2e3aa0@bootlin.com> References: <20251126-feature_tilcdc-v1-0-49b9ef2e3aa0@bootlin.com> In-Reply-To: <20251126-feature_tilcdc-v1-0-49b9ef2e3aa0@bootlin.com> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Russell King , Bartosz Golaszewski , Tony Lindgren , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec Cc: Markus Schneider-Pargmann , Luca Ceresoli , Louis Chauvet , Thomas Petazzoni , Miguel Gazquez , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-omap@vger.kernel.org, "Kory Maincent (TI.com)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Remove the deprecated ti,tilcdc,panel binding which violates devicetree design principles by placing display controller configuration (DMA burst size, FIFO thresholds, AC bias, etc.) inside the panel node instead of the controller node where it belongs. This non-standard binding has several critical issues: - Mixes controller-specific hardware parameters with panel properties - Lacks the standard port/endpoint graph for panel connections - Cannot work with the standard DRM panel infrastructure - Forces vendor-specific binding instead of reusable panel-dpi binding The tilcdc driver has been updated to work with standard DRM panels and bridges, and all in-tree users have been migrated to use the generic panel-dpi binding with proper port/endpoint connections. Controller parameters like fifo-threshold are now correctly specified in the tilcdc node itself. While removing bindings is exceptional, keeping this binding would: - Perpetuate incorrect devicetree design patterns - Require maintaining a non-standard panel driver solely for tilcdc - Block proper integration with the DRM panel subsystem - Prevent devicetree reusability across different display controllers This removal completes the migration to standard DRM panel bindings. Signed-off-by: Kory Maincent (TI.com) --- .../devicetree/bindings/display/tilcdc/panel.txt | 66 ------------------= ---- 1 file changed, 66 deletions(-) diff --git a/Documentation/devicetree/bindings/display/tilcdc/panel.txt b/D= ocumentation/devicetree/bindings/display/tilcdc/panel.txt deleted file mode 100644 index 808216310ea27..0000000000000 --- a/Documentation/devicetree/bindings/display/tilcdc/panel.txt +++ /dev/null @@ -1,66 +0,0 @@ -Device-Tree bindings for tilcdc DRM generic panel output driver - -Required properties: - - compatible: value should be "ti,tilcdc,panel". - - panel-info: configuration info to configure LCDC correctly for the panel - - ac-bias: AC Bias Pin Frequency - - ac-bias-intrpt: AC Bias Pin Transitions per Interrupt - - dma-burst-sz: DMA burst size - - bpp: Bits per pixel - - fdd: FIFO DMA Request Delay - - sync-edge: Horizontal and Vertical Sync Edge: 0=3Drising 1=3Dfalling - - sync-ctrl: Horizontal and Vertical Sync: Control: 0=3Dignore - - raster-order: Raster Data Order Select: 1=3DMost-to-least 0=3DLeast-t= o-most - - fifo-th: DMA FIFO threshold - - display-timings: typical videomode of lcd panel. Multiple video modes - can be listed if the panel supports multiple timings, but the 'native-m= ode' - should be the preferred/default resolution. Refer to - Documentation/devicetree/bindings/display/panel/display-timing.txt for = display - timing binding details. - -Optional properties: -- backlight: phandle of the backlight device attached to the panel -- enable-gpios: GPIO pin to enable or disable the panel - -Recommended properties: - - pinctrl-names, pinctrl-0: the pincontrol settings to configure - muxing properly for pins that connect to TFP410 device - -Example: - - /* Settings for CDTech_S035Q01 / LCD3 cape: */ - lcd3 { - compatible =3D "ti,tilcdc,panel"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&bone_lcd3_cape_lcd_pins>; - backlight =3D <&backlight>; - enable-gpios =3D <&gpio3 19 0>; - - panel-info { - ac-bias =3D <255>; - ac-bias-intrpt =3D <0>; - dma-burst-sz =3D <16>; - bpp =3D <16>; - fdd =3D <0x80>; - sync-edge =3D <0>; - sync-ctrl =3D <1>; - raster-order =3D <0>; - fifo-th =3D <0>; - }; - display-timings { - native-mode =3D <&timing0>; - timing0: 320x240 { - hactive =3D <320>; - vactive =3D <240>; - hback-porch =3D <21>; - hfront-porch =3D <58>; - hsync-len =3D <47>; - vback-porch =3D <11>; - vfront-porch =3D <23>; - vsync-len =3D <2>; - clock-frequency =3D <8000000>; - hsync-active =3D <0>; - vsync-active =3D <0>; - }; - }; - }; --=20 2.43.0 From nobody Mon Dec 1 22:41:52 2025 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3B533342525 for ; Wed, 26 Nov 2025 17:37:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764178630; cv=none; b=f7/HO56wW2lgNU6DiqDDSmC2UiZPT74VrAsRMwfKahm58cqJ/G5gnVc4UkPoFU2P++MXrmZiG/n7apQzAWUall9XbctUrjVKBLzsx3lidJFc8YVSsa7MrD/971RoSBRcibBx233Ni/OAu7GMpnEp640MXLu13LD+JLq1RZkZDt8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764178630; 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Wed, 26 Nov 2025 17:36:44 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id C1AB260721; Wed, 26 Nov 2025 17:37:06 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 03AEF102F2328; Wed, 26 Nov 2025 18:37:02 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1764178625; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=COV/iHr/jAimfUtavyABJWkAYddjEoAQigrBOEkAvAs=; b=1SlxCcyq++X+yDbZTHNbKRhGO0dC/wWB4WdGbtDswySPV3pz8SaE3es7FKDnXe6peIjpBB FB3+BAhYcRa1TEYBQ+SoAlY2g1VPFUWsh5izkiOkK4qc5H88s6Zzw0JR4yLgcgh9tVXEuC lKhjastQhkXTU9jGCdlHNrJo3bD/NV2cPPWDSXgl+vZnkRdRxcVEAS6gG/N5Yy8yxMvxIk lZBAetud3u4TDiYWD82IY9Xq+Vj1YvTFImQMBDRX6tXaWpBPwu8Jq/fF0HmWesLVlSZOgn ds1J3NSGQ/o3OZc91cgLq7BTgKh0zGqdB9nMXRamwrh1PF7Aveb9v343tKuOAQ== From: "Kory Maincent (TI.com)" Date: Wed, 26 Nov 2025 18:35:49 +0100 Subject: [PATCH 07/21] drm/tilcdc: Remove tilcdc panel driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251126-feature_tilcdc-v1-7-49b9ef2e3aa0@bootlin.com> References: <20251126-feature_tilcdc-v1-0-49b9ef2e3aa0@bootlin.com> In-Reply-To: <20251126-feature_tilcdc-v1-0-49b9ef2e3aa0@bootlin.com> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Russell King , Bartosz Golaszewski , Tony Lindgren , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec Cc: Markus Schneider-Pargmann , Luca Ceresoli , Louis Chauvet , Thomas Petazzoni , Miguel Gazquez , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-omap@vger.kernel.org, "Kory Maincent (TI.com)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The tilcdc panel subdriver is a legacy, non-standard driver that has been replaced by the standard panel-dpi driver and panel-simple infrastructure. With the device tree bindings removed and all in-tree users migrated to use panel-dpi, this driver no longer has any associated device tree bindings or users. The panel-dpi driver combined with DRM bus flags provides equivalent functionality in a standard way that is compatible with the broader DRM panel ecosystem. This removal eliminates 400+ lines of redundant code and completes the migration to standard panel handling. Signed-off-by: Kory Maincent (TI.com) --- drivers/gpu/drm/tilcdc/Makefile | 1 - drivers/gpu/drm/tilcdc/tilcdc_drv.c | 3 - drivers/gpu/drm/tilcdc/tilcdc_panel.c | 408 ------------------------------= ---- drivers/gpu/drm/tilcdc/tilcdc_panel.h | 15 -- 4 files changed, 427 deletions(-) diff --git a/drivers/gpu/drm/tilcdc/Makefile b/drivers/gpu/drm/tilcdc/Makef= ile index f5190477de721..b24122bea2596 100644 --- a/drivers/gpu/drm/tilcdc/Makefile +++ b/drivers/gpu/drm/tilcdc/Makefile @@ -6,7 +6,6 @@ endif tilcdc-y :=3D \ tilcdc_plane.o \ tilcdc_crtc.o \ - tilcdc_panel.o \ tilcdc_external.o \ tilcdc_drv.o =20 diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.c b/drivers/gpu/drm/tilcdc/t= ilcdc_drv.c index 76eb336b5d4e7..411f0767d112d 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_drv.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.c @@ -28,7 +28,6 @@ =20 #include "tilcdc_drv.h" #include "tilcdc_external.h" -#include "tilcdc_panel.h" #include "tilcdc_regs.h" =20 static LIST_HEAD(module_list); @@ -623,7 +622,6 @@ static int __init tilcdc_drm_init(void) return -ENODEV; =20 DBG("init"); - tilcdc_panel_init(); return platform_driver_register(&tilcdc_platform_driver); } =20 @@ -631,7 +629,6 @@ static void __exit tilcdc_drm_fini(void) { DBG("fini"); platform_driver_unregister(&tilcdc_platform_driver); - tilcdc_panel_fini(); } =20 module_init(tilcdc_drm_init); diff --git a/drivers/gpu/drm/tilcdc/tilcdc_panel.c b/drivers/gpu/drm/tilcdc= /tilcdc_panel.c deleted file mode 100644 index 262f290d85d91..0000000000000 --- a/drivers/gpu/drm/tilcdc/tilcdc_panel.c +++ /dev/null @@ -1,408 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments - * Author: Rob Clark - */ - -#include -#include -#include - -#include