From nobody Tue Dec 2 00:05:24 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E3D81308F38 for ; Wed, 26 Nov 2025 09:40:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764150013; cv=none; b=QgHlMY2WIle9ngYyoePD/TCqaKvN6cuCmdPggexAbBcWDUmmpE8o4BC+FlgB5x0XvIOosaOpqBw50mLi/q9tP09kxHL+LIpy3X1OFP3XpzwGf1DMeKjgu9BXF99ONbwZfreKPdd6AUOnsrlxGWmR0adKU3zCeIIb1IHxKvuIa7E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764150013; c=relaxed/simple; bh=aUWZVnSGJaoOnG4FwYntjaIOEF973QdxdoMUNrAWxCY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bQXrLAz1cozls8NG0beAxOtuR5s1uqC4xiZn1Z2Ef6sW/k3joI3NnWb1rcbNVjTbKUp+yAiJclFCBJUVJ78W4HyS3BRH8uWC300Z7NvvdlWsrhQAiVXmrL/Lpy1bH5m87QgjbRByRl5QqyV/IZiQAZv3HJ1XbmSf+cket3PQtA8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=IRFXx+xl; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=VkHb5EcH; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="IRFXx+xl"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="VkHb5EcH" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5AQ6vAV51458075 for ; Wed, 26 Nov 2025 09:40:08 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= lXi0hQF+CXjVt8VwjHLDzMhyGix4gzAjer2rjFjzzx8=; b=IRFXx+xlOFYjUxYO 4KmHsOwAjlKgcvgu32eQuIu6LhRRvuZaBSuqbjvW7pxFmejLQm5hycv8h4V9fRJW ynUPIVv/S4qzntAZvHEjT+Qj3f6vCfMB07iGxWt7L3FUTZEt5dQ0jCrhCEO6e603 NUmCznHYZqUsCKfdXHlDEt589p40toF5R1mvXjlB9L7lMttJIKMWxgefyXkUDNx8 BUobbnqmc4ibBqiAjqmtVHZSRwVR4bq+SZuwgOCSUsGYBRNi/1YFlpN8YYGM/S/3 ci9aTbDgY3G4Ps/5aheinvJzYTpAJ2qG1/8rw9lzkHjr5wLTxxNa9FhrBF29YFFO YLHabw== Received: from mail-pl1-f198.google.com (mail-pl1-f198.google.com [209.85.214.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4anvqvgfpv-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 26 Nov 2025 09:40:08 +0000 (GMT) Received: by mail-pl1-f198.google.com with SMTP id d9443c01a7336-295595cd102so138521065ad.3 for ; Wed, 26 Nov 2025 01:40:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1764150007; x=1764754807; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=lXi0hQF+CXjVt8VwjHLDzMhyGix4gzAjer2rjFjzzx8=; b=VkHb5EcH7gYDszfQ7vl3OM8qJ7yr95QqZ12Sxgc1JO7dESlVXRFWWK5iQ+i4SMhVu3 SYNgcpfYjZzKyWSG5iahuyiofQOCQtCiKUirU5FCazx6/DGlcH7wMChpYOoyDZfbm69p n8aSEa/CnBqrjou0i1r5Ws2ygiCHSrLXH59Jnn4l47BArERaqW5fqBLaxhDSlEfjBsMo tLY/jvTqXbe4lJl2tiAxd0acUwE8LJoS8ekBPuYZyNLGA1bfy0mDB9qIn0/pxTzxbthv tIpRUHh15Xon8sBU6WGzSLY1d79f0/BLumcCjuHIiexT45lORxOGBJ4NPQ1zMbrb7lE5 o5Ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764150007; x=1764754807; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=lXi0hQF+CXjVt8VwjHLDzMhyGix4gzAjer2rjFjzzx8=; b=PTqXLgdNgBmzxmpMbnTe9OA+zL02jaN4S9G8cY6A3Xa+3Umrl4bECNQ7H8mz9e03kz xujQeqXW7bmW1ntvnT7cNOY6UIwSI0CFKr3MdF9xBSaJ/ubYahbJk3u3I0e/Kqu+Mk34 QuYfXl0wzYWIgg4xn1P5PnSsHOrFFQ1PC+i0xI9BXt6ixLRG4ZeKek1tStd55f+/Szw1 krpTTQq5nqmcXpF9gzkwzgzwyhS6EYm3VVaN41W19hLzKs/ASNgiNb5vM8EzYa3wYMd9 xBpDjm/zyrqCtYJWnPdpwqEM/do4XgCTlNA6rlzqPAA7Vuaq5Vdj2xDqRFxihcCZUCz0 v3cw== X-Forwarded-Encrypted: i=1; AJvYcCVOHubbk+41ZWcz7qC2AfhOoXtmzCZ2GilxSRbS73f5Dw6yYBn72GUXguknvVmOBRE2mEFEOqD51aQZ+aM=@vger.kernel.org X-Gm-Message-State: AOJu0YxOQFjKr95U6xq7lM7q3IkubynkmEg7sx0g2+rTXB5+s+D7y/WO V1NSPcCRmxkvGfjz3coKfLNUOn5Z7DMXUn92pUwe6o/wM3SuTMgacMAwRYHTgbsVfRfxpV95eYL yqwbPZ7wmAkzPyprSk9Hd4ZLb5qsdknoj+IcHE3amzXRvXDLwoq6/VSt9LVjpFjVtsPlrjxKeTL o= X-Gm-Gg: ASbGnctWTPT9Owu01I2/oa3kvKS9GypQOanpPkZwvI8xPkAtR5a26TU9AYNDnWagRvP YkQTJ6oH/mirRdz+7MWF5yv11EI4sVcllxolrjprkjdzHONzYTOZHj2ueClFZpLMO5JxWDfrdeD 4NhFZ+QSE63FlLESzDqsxsyaxeuhic+VJaOBoIEJ3DL31jRZvXB+ZngmitX63kyCtke2tfdDHxF hXSnRVYaCcQe5KTGa+jutNaY1VVsP03DayMDfqBrkPrJiUy4GWhA3cV6k4fnKRamFrEJA2KQvO7 CSlgZxEtB4ExM37y7R+adz6Gny9PkNBbP0egMOMBW2lipGQqk+QeZwVvcPED+ojL1QsXfHdj4bl sB398t6IptgRk5IAv2WfE4KpLHrapSk36QtJPVKLNFHbirf0yAALwAc4N4ricp1vT X-Received: by 2002:a05:7022:4292:b0:11a:37a7:3d30 with SMTP id a92af1059eb24-11c9d712792mr12989539c88.11.1764150007047; Wed, 26 Nov 2025 01:40:07 -0800 (PST) X-Google-Smtp-Source: AGHT+IGsCVKKBgztWpkYDz3XVCE1j/r0Je4XaWNMw2bXD/GzT9Ni3auZwGWTys1EWNdxqaPUMSA0xQ== X-Received: by 2002:a05:7022:4292:b0:11a:37a7:3d30 with SMTP id a92af1059eb24-11c9d712792mr12989487c88.11.1764150006171; Wed, 26 Nov 2025 01:40:06 -0800 (PST) Received: from hu-hangxian-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11c93e3e784sm69150307c88.5.2025.11.26.01.40.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Nov 2025 01:40:05 -0800 (PST) From: Hangxiang Ma Date: Wed, 26 Nov 2025 01:38:35 -0800 Subject: [PATCH 2/7] media: dt-bindings: Add CAMSS device for SM8750 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251126-add-support-for-camss-on-sm8750-v1-2-646fee2eb720@oss.qualcomm.com> References: <20251126-add-support-for-camss-on-sm8750-v1-0-646fee2eb720@oss.qualcomm.com> In-Reply-To: <20251126-add-support-for-camss-on-sm8750-v1-0-646fee2eb720@oss.qualcomm.com> To: Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Todor Tomov , Vladimir Zapolskiy , Mauro Carvalho Chehab , Bryan O'Donoghue Cc: linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, jeyaprakash.soundrapandian@oss.qualcomm.com, Vijay Kumar Tumati , Hangxiang Ma X-Mailer: b4 0.14.3 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTI2MDA3OCBTYWx0ZWRfX51FmdqvCzVIr b8MERmv+yLwc6stONfJAU6+0WwBznzjNQDaFsSfHFU+0JeZ+8bNQpfIS1dIA8AmjxXmvOnAB+gG i+f6v7leuOYgdQbzF9HCoXish405NO6ynUBm14PlL1NKP5OV9sUe7Zd9DaJs02RS8pUMy/gWBll ECjJ1wtX80JtsL051B9dWzOM2enoT/5/CfToBt+FgkDeEW62H/mWQ4k+sIg05ekEHdyhEZ94yh6 waJj8MNq0sccq+j0FZFdMEtRvOH0v3XD3SrOcKf57LI3sR/LrrWyfoFssb6txNxJ0x7Bs0iXuJ5 V7GRVqTgQ1FbhZaLUNhmvUV2VS/OOFBlKQlcryQb1NENRfzOhQJzdnrJ6csbYN5LwqzmNoRLxdF Ez9EpSYC1vDByUCwx84D4Y9W81o0aQ== X-Proofpoint-GUID: kPZ-EH3L7XdlDM-gWyjGetGm6TxQ4OQL X-Proofpoint-ORIG-GUID: kPZ-EH3L7XdlDM-gWyjGetGm6TxQ4OQL X-Authority-Analysis: v=2.4 cv=feugCkQF c=1 sm=1 tr=0 ts=6926caf8 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=dpxBiYkotQz7p_VYlh4A:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-25_02,2025-11-25_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 phishscore=0 spamscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511260078 Add the compatible string "qcom,sm8750-camss" to support the Camera Subsystem (CAMSS) on the Qualcomm SM8750 platform. The SM8750 platform provides: - 3 x VFE, 5 RDI per VFE - 2 x VFE Lite, 4 RDI per VFE Lite - 3 x CSID - 2 x CSID Lite - 6 x CSIPHY - 2 x ICP - 1 x IPE - 2 x JPEG DMA & Downscaler - 2 x JPEG Encoder - 1 x OFE - 5 x RT CDM - 3 x TPG Signed-off-by: Hangxiang Ma Reviewed-by: Bryan O'Donoghue --- .../bindings/media/qcom,sm8750-camss.yaml | 664 +++++++++++++++++= ++++ 1 file changed, 664 insertions(+) diff --git a/Documentation/devicetree/bindings/media/qcom,sm8750-camss.yaml= b/Documentation/devicetree/bindings/media/qcom,sm8750-camss.yaml new file mode 100644 index 000000000000..6b2b0b5a7e19 --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,sm8750-camss.yaml @@ -0,0 +1,664 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,sm8750-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8750 Camera Subsystem (CAMSS) + +maintainers: + - Hangxiang Ma + +description: + This binding describes the camera subsystem hardware found on SM8750 Qua= lcomm + SoCs. It includes submodules such as CSIPHY (CSI Physical layer) and CSID + (CSI Decoder), which comply with the MIPI CSI2 protocol. + + The subsystem also integrates a set of real-time image processing engine= s and + their associated configuration modules, as well as non-real-time engines. + + Additionally, it encompasses a test pattern generator (TPG) submodule. + +properties: + compatible: + const: qcom,sm8750-camss + + reg: + items: + - description: Registers for CSID 0 + - description: Registers for CSID 1 + - description: Registers for CSID 2 + - description: Registers for CSID Lite 0 + - description: Registers for CSID Lite 1 + - description: Registers for CSIPHY 0 + - description: Registers for CSIPHY 1 + - description: Registers for CSIPHY 2 + - description: Registers for CSIPHY 3 + - description: Registers for CSIPHY 4 + - description: Registers for CSIPHY 5 + - description: Registers for VFE (Video Front End) 0 + - description: Registers for VFE 1 + - description: Registers for VFE 2 + - description: Registers for VFE Lite 0 + - description: Registers for VFE Lite 1 + - description: Registers for ICP (Imaging Control Processor) 0 + - description: Registers for ICP SYS 0 + - description: Registers for ICP 1 + - description: Registers for ICP SYS 1 + - description: Registers for IPE (Image Processing Engine) + - description: Registers for JPEG DMA & Downscaler 0 + - description: Registers for JPEG Encoder 0 + - description: Registers for JPEG DMA & Downscaler 1 + - description: Registers for JPEG Encoder 1 + - description: Registers for OFE (Offline Front End) + - description: Registers for RT CDM (Camera Data Mover) 0 + - description: Registers for RT CDM 1 + - description: Registers for RT CDM 2 + - description: Registers for RT CDM 3 + - description: Registers for RT CDM 4 + - description: Registers for TPG 0 + - description: Registers for TPG 1 + - description: Registers for TPG 2 + + reg-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: csiphy4 + - const: csiphy5 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite0 + - const: vfe_lite1 + - const: icp0 + - const: icp0_sys + - const: icp1 + - const: icp1_sys + - const: ipe + - const: jpeg_dma0 + - const: jpeg_enc0 + - const: jpeg_dma1 + - const: jpeg_enc1 + - const: ofe + - const: rt_cdm0 + - const: rt_cdm1 + - const: rt_cdm2 + - const: rt_cdm3 + - const: rt_cdm4 + - const: tpg0 + - const: tpg1 + - const: tpg2 + + clocks: + maxItems: 61 + + clock-names: + items: + - const: camnoc_nrt_axi + - const: camnoc_rt_axi + - const: camnoc_rt_vfe0 + - const: camnoc_rt_vfe1 + - const: camnoc_rt_vfe2 + - const: camnoc_rt_vfe_lite + - const: cam_top_ahb + - const: cam_top_fast_ahb + - const: csid + - const: csid_csiphy_rx + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy1 + - const: csiphy1_timer + - const: csiphy2 + - const: csiphy2_timer + - const: csiphy3 + - const: csiphy3_timer + - const: csiphy4 + - const: csiphy4_timer + - const: csiphy5 + - const: csiphy5_timer + - const: gcc_hf_axi + - const: vfe0 + - const: vfe0_fast_ahb + - const: vfe1 + - const: vfe1_fast_ahb + - const: vfe2 + - const: vfe2_fast_ahb + - const: vfe_lite + - const: vfe_lite_ahb + - const: vfe_lite_cphy_rx + - const: vfe_lite_csid + - const: qdss_debug_xo + - const: camnoc_ipe_nps + - const: camnoc_ofe + - const: gcc_sf_axi + - const: icp0 + - const: icp0_ahb + - const: icp1 + - const: icp1_ahb + - const: ipe_nps + - const: ipe_nps_ahb + - const: ipe_nps_fast_ahb + - const: ipe_pps + - const: ipe_pps_fast_ahb + - const: jpeg0 + - const: jpeg1 + - const: ofe_ahb + - const: ofe_anchor + - const: ofe_anchor_fast_ahb + - const: ofe_hdr + - const: ofe_hdr_fast_ahb + - const: ofe_main + - const: ofe_main_fast_ahb + - const: vfe0_bayer + - const: vfe0_bayer_fast_ahb + - const: vfe1_bayer + - const: vfe1_bayer_fast_ahb + - const: vfe2_bayer + - const: vfe2_bayer_fast_ahb + + interrupts: + maxItems: 32 + + interrupt-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: csiphy4 + - const: csiphy5 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite0 + - const: vfe_lite1 + - const: camnoc_nrt + - const: camnoc_rt + - const: icp0 + - const: icp1 + - const: jpeg_dma0 + - const: jpeg_enc0 + - const: jpeg_dma1 + - const: jpeg_enc1 + - const: rt_cdm0 + - const: rt_cdm1 + - const: rt_cdm2 + - const: rt_cdm3 + - const: rt_cdm4 + - const: tpg0 + - const: tpg1 + - const: tpg2 + + interconnects: + maxItems: 4 + + interconnect-names: + items: + - const: ahb + - const: hf_mnoc + - const: sf_icp_mnoc + - const: sf_mnoc + + iommus: + items: + - description: VFE non-protected stream + - description: ICP0 shared stream + - description: ICP1 shared stream + - description: IPE CDM non-protected stream + - description: IPE non-protected stream + - description: JPEG non-protected stream + - description: OFE CDM non-protected stream + - description: OFE non-protected stream + - description: VFE / VFE Lite CDM non-protected stream + + power-domains: + items: + - description: + VFE0 GDSC - Global Distributed Switch Controller for VFE0. + - description: + VFE1 GDSC - Global Distributed Switch Controller for VFE1. + - description: + VFE2 GDSC - Global Distributed Switch Controller for VFE2. + - description: + Titan GDSC - Global Distributed Switch Controller for the entire= camss. + - description: + IPE GDSC - Global Distributed Switch Controller for IPE. + - description: + OFE GDSC - Block Global Distributed Switch Controller for OFE. + + power-domain-names: + items: + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: top + - const: ipe + - const: ofe + + vdd-csiphy0-0p88-supply: + description: + Phandle to a 0.88V regulator supply to CSIPHY0 core block. + + vdd-csiphy0-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY0 pll block. + + vdd-csiphy1-0p88-supply: + description: + Phandle to a 0.88V regulator supply to CSIPHY1 core block. + + vdd-csiphy1-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY1 pll block. + + vdd-csiphy2-0p88-supply: + description: + Phandle to a 0.88V regulator supply to CSIPHY2 core block. + + vdd-csiphy2-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY2 pll block. + + vdd-csiphy3-0p88-supply: + description: + Phandle to a 0.88V regulator supply to CSIPHY3 core block. + + vdd-csiphy3-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY3 pll block. + + vdd-csiphy4-0p88-supply: + description: + Phandle to a 0.88V regulator supply to CSIPHY4 core block. + + vdd-csiphy4-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY4 pll block. + + vdd-csiphy5-0p88-supply: + description: + Phandle to a 0.88V regulator supply to CSIPHY5 core block. + + vdd-csiphy5-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY5 pll block. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + + patternProperties: + "^port@[0-5]$": + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input ports for receiving CSI data on CSIPHY 0-5. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - data-lanes + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + - interconnects + - interconnect-names + - iommus + - power-domains + - power-domain-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + isp@ad27000 { + compatible =3D "qcom,sm8750-camss"; + + reg =3D <0x0 0x0ad27000 0x0 0x2b00>, + <0x0 0x0ad2a000 0x0 0x2b00>, + <0x0 0x0ad2d000 0x0 0x2b00>, + <0x0 0x0ad6d000 0x0 0xa00>, + <0x0 0x0ad72000 0x0 0xa00>, + <0x0 0x0ada9000 0x0 0x2000>, + <0x0 0x0adab000 0x0 0x2000>, + <0x0 0x0adad000 0x0 0x2000>, + <0x0 0x0adaf000 0x0 0x2000>, + <0x0 0x0adb1000 0x0 0x2000>, + <0x0 0x0adb3000 0x0 0x2000>, + <0x0 0x0ac86000 0x0 0x10000>, + <0x0 0x0ac96000 0x0 0x10000>, + <0x0 0x0aca6000 0x0 0x10000>, + <0x0 0x0ad6e000 0x0 0x1800>, + <0x0 0x0ad73000 0x0 0x1800>, + <0x0 0x0ac06000 0x0 0x1000>, + <0x0 0x0ac05000 0x0 0x1000>, + <0x0 0x0ac16000 0x0 0x1000>, + <0x0 0x0ac15000 0x0 0x1000>, + <0x0 0x0ac42000 0x0 0x18000>, + <0x0 0x0ac26000 0x0 0x1000>, + <0x0 0x0ac25000 0x0 0x1000>, + <0x0 0x0ac28000 0x0 0x1000>, + <0x0 0x0ac27000 0x0 0x1000>, + <0x0 0x0ac2a000 0x0 0x18000>, + <0x0 0x0ac7f000 0x0 0x580>, + <0x0 0x0ac80000 0x0 0x580>, + <0x0 0x0ac81000 0x0 0x580>, + <0x0 0x0ac82000 0x0 0x580>, + <0x0 0x0ac83000 0x0 0x580>, + <0x0 0x0ad8b000 0x0 0x400>, + <0x0 0x0ad8c000 0x0 0x400>, + <0x0 0x0ad8d000 0x0 0x400>; + reg-names =3D "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1", + "icp0", + "icp0_sys", + "icp1", + "icp1_sys", + "ipe", + "jpeg_dma0", + "jpeg_enc0", + "jpeg_dma1", + "jpeg_enc1", + "ofe", + "rt_cdm0", + "rt_cdm1", + "rt_cdm2", + "rt_cdm3", + "rt_cdm4", + "tpg0", + "tpg1", + "tpg2"; + + clocks =3D <&camcc_cam_cc_camnoc_nrt_axi_clk>, + <&camcc_cam_cc_camnoc_rt_axi_clk>, + <&camcc_cam_cc_camnoc_rt_vfe_0_main_clk>, + <&camcc_cam_cc_camnoc_rt_vfe_1_main_clk>, + <&camcc_cam_cc_camnoc_rt_vfe_2_main_clk>, + <&camcc_cam_cc_camnoc_rt_vfe_lite_clk>, + <&camcc_cam_cc_cam_top_ahb_clk>, + <&camcc_cam_cc_cam_top_fast_ahb_clk>, + <&camcc_cam_cc_csid_clk>, + <&camcc_cam_cc_csid_csiphy_rx_clk>, + <&camcc_cam_cc_csiphy0_clk>, + <&camcc_cam_cc_csi0phytimer_clk>, + <&camcc_cam_cc_csiphy1_clk>, + <&camcc_cam_cc_csi1phytimer_clk>, + <&camcc_cam_cc_csiphy2_clk>, + <&camcc_cam_cc_csi2phytimer_clk>, + <&camcc_cam_cc_csiphy3_clk>, + <&camcc_cam_cc_csi3phytimer_clk>, + <&camcc_cam_cc_csiphy4_clk>, + <&camcc_cam_cc_csi4phytimer_clk>, + <&camcc_cam_cc_csiphy5_clk>, + <&camcc_cam_cc_csi5phytimer_clk>, + <&gcc_gcc_camera_hf_axi_clk>, + <&camcc_cam_cc_vfe_0_main_clk>, + <&camcc_cam_cc_vfe_0_main_fast_ahb_clk>, + <&camcc_cam_cc_vfe_1_main_clk>, + <&camcc_cam_cc_vfe_1_main_fast_ahb_clk>, + <&camcc_cam_cc_vfe_2_main_clk>, + <&camcc_cam_cc_vfe_2_main_fast_ahb_clk>, + <&camcc_cam_cc_vfe_lite_clk>, + <&camcc_cam_cc_vfe_lite_ahb_clk>, + <&camcc_cam_cc_vfe_lite_cphy_rx_clk>, + <&camcc_cam_cc_vfe_lite_csid_clk>, + <&camcc_cam_cc_qdss_debug_xo_clk>, + <&camcc_cam_cc_camnoc_nrt_ipe_nps_clk>, + <&camcc_cam_cc_camnoc_nrt_ofe_main_clk>, + <&gcc_gcc_camera_sf_axi_clk>, + <&camcc_cam_cc_icp_0_clk>, + <&camcc_cam_cc_icp_0_ahb_clk>, + <&camcc_cam_cc_icp_1_clk>, + <&camcc_cam_cc_icp_1_ahb_clk>, + <&camcc_cam_cc_ipe_nps_clk>, + <&camcc_cam_cc_ipe_nps_ahb_clk>, + <&camcc_cam_cc_ipe_nps_fast_ahb_clk>, + <&camcc_cam_cc_ipe_pps_clk>, + <&camcc_cam_cc_ipe_pps_fast_ahb_clk>, + <&camcc_cam_cc_jpeg_0_clk>, + <&camcc_cam_cc_jpeg_1_clk>, + <&camcc_cam_cc_ofe_ahb_clk>, + <&camcc_cam_cc_ofe_anchor_clk>, + <&camcc_cam_cc_ofe_anchor_fast_ahb_clk>, + <&camcc_cam_cc_ofe_hdr_clk>, + <&camcc_cam_cc_ofe_hdr_fast_ahb_clk>, + <&camcc_cam_cc_ofe_main_clk>, + <&camcc_cam_cc_ofe_main_fast_ahb_clk>, + <&camcc_cam_cc_vfe_0_bayer_clk>, + <&camcc_cam_cc_vfe_0_bayer_fast_ahb_clk>, + <&camcc_cam_cc_vfe_1_bayer_clk>, + <&camcc_cam_cc_vfe_1_bayer_fast_ahb_clk>, + <&camcc_cam_cc_vfe_2_bayer_clk>, + <&camcc_cam_cc_vfe_2_bayer_fast_ahb_clk>; + clock-names =3D "camnoc_nrt_axi", + "camnoc_rt_axi", + "camnoc_rt_vfe0", + "camnoc_rt_vfe1", + "camnoc_rt_vfe2", + "camnoc_rt_vfe_lite", + "cam_top_ahb", + "cam_top_fast_ahb", + "csid", + "csid_csiphy_rx", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "csiphy4", + "csiphy4_timer", + "csiphy5", + "csiphy5_timer", + "gcc_hf_axi", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe2", + "vfe2_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid", + "qdss_debug_xo", + "camnoc_ipe_nps", + "camnoc_ofe", + "gcc_sf_axi", + "icp0", + "icp0_ahb", + "icp1", + "icp1_ahb", + "ipe_nps", + "ipe_nps_ahb", + "ipe_nps_fast_ahb", + "ipe_pps", + "ipe_pps_fast_ahb", + "jpeg0", + "jpeg1", + "ofe_ahb", + "ofe_anchor", + "ofe_anchor_fast_ahb", + "ofe_hdr", + "ofe_hdr_fast_ahb", + "ofe_main", + "ofe_main_fast_ahb", + "vfe0_bayer", + "vfe0_bayer_fast_ahb", + "vfe1_bayer", + "vfe1_bayer_fast_ahb", + "vfe2_bayer", + "vfe2_bayer_fast_ahb"; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1", + "camnoc_nrt", + "camnoc_rt", + "icp0", + "icp1", + "jpeg_dma0", + "jpeg_enc0", + "jpeg_dma1", + "jpeg_enc1", + "rt_cdm0", + "rt_cdm1", + "rt_cdm2", + "rt_cdm3", + "rt_cdm4", + "tpg0", + "tpg1", + "tpg2"; + + interconnects =3D <&gem_noc_master_appss_proc QCOM_ICC_TAG_ACT= IVE_ONLY + &config_noc_slave_camera_cfg QCOM_ICC_TAG_ACT= IVE_ONLY>, + <&mmss_noc_master_camnoc_hf QCOM_ICC_TAG_ALWAYS + &mc_virt_slave_ebi1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc_master_camnoc_nrt_icp_sf QCOM_ICC_T= AG_ALWAYS + &mc_virt_slave_ebi1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc_master_camnoc_sf QCOM_ICC_TAG_ALWAYS + &mc_virt_slave_ebi1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "ahb", + "hf_mnoc", + "sf_icp_mnoc", + "sf_mnoc"; + + iommus =3D <&apps_smmu 0x1c00 0x00>, + <&apps_smmu 0x18c0 0x00>, + <&apps_smmu 0x1980 0x00>, + <&apps_smmu 0x1840 0x00>, + <&apps_smmu 0x1800 0x00>, + <&apps_smmu 0x18a0 0x00>, + <&apps_smmu 0x1880 0x00>, + <&apps_smmu 0x1820 0x00>, + <&apps_smmu 0x1860 0x00>; + + power-domains =3D <&camcc_cam_cc_vfe_0_gdsc>, + <&camcc_cam_cc_vfe_1_gdsc>, + <&camcc_cam_cc_vfe_2_gdsc>, + <&camcc_cam_cc_titan_top_gdsc>, + <&camcc_cam_cc_ipe_0_gdsc>, + <&camcc_cam_cc_ofe_gdsc>; + power-domain-names =3D "vfe0", + "vfe1", + "vfe2", + "top", + "ipe", + "ofe"; + + vdd-csiphy0-0p88-supply =3D <&vreg_0p88_supply>; + vdd-csiphy0-1p2-supply =3D <&vreg_1p2_supply>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + csiphy_ep0: endpoint { + data-lanes =3D <0 1>; + remote-endpoint =3D <&sensor_ep>; + }; + }; + }; + }; + }; --=20 2.34.1